KR970003427B1 - Converting device of scan speed of digital video signal - Google Patents

Abstract

A power control circuit of the monitor using the video RAM like the dual port memory in order to solve the complexity of the logic for switching of the column address strove signal frequently. The said circuit consist of a data bit extension means(20), a video RAM(30), a video RAM address generation means(50), a video RAM control signal generation means(70), a scanning timing generation means(80) and a output means(40).

Description

Scan speed converter of digital video signal

1 is a block diagram of an apparatus for converting a scan rate of a digital video signal according to the present invention.

2 is a circuit diagram of a latch control signal generator of FIG.

3 is a circuit diagram of the latch portion of FIG.

FIG. 4 is a waveform diagram of each sub-signal of the data bit extension of FIG.

5 is a circuit diagram of a video RAM control signal generator.

6 is a state variation diagram of the video RAM control signals of FIG.

7 is a state variation diagram of the video RAM serial register conversion control signals of FIG.

8 is a circuit diagram of the video RAM address generator of FIG.

9 is a conceptual diagram of video RAM address generation.

10 is a state variation diagram of a multiplex output port terminal selection signal of a video RAM write address generator and a video RAM serial register conversion address generator.

11 is a state variation diagram of video RAM address generation control signals.

12 is an operational waveform diagram of video RAM control signals during a video RAM write cycle.

13 is an operational waveform diagram of video RAM control signals during a video RAM serial register conversion period.

* Explanation of symbols for main parts of the drawings

1 digital video signal generator 10 latch unit

15: latch control signal generator 20: data bit expansion unit

30: video RAM 40: output unit

50: video RAM address generator 70: video RAM control signal generator

80: scan timing generator

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an apparatus for converting scan rates of digital video signals. In particular, the present invention relates to digital video for converting scan rates so that a computer can process interlaced digital video signals. A scan rate converter for a signal.

Recently, digital video signals output from image processing devices such as television (TV), VCS (Video Cassette Recorder) or Laser Disk Player (LDP: Laser Disk Player) are processed by computer to realize more diverse images. Various attempts have been made, and the most important task in processing a video signal with a computer is that the video signal output from the image processing apparatuses listed above may be processed by a display device in a computer environment having a different signal processing method. To change the scan speed.

To this end, conventionally, memory is divided into column address strobes (CAS) to process 16-bit data, and the memory is divided into two banks. The two banks had to be switched one by one. In this case, due to frequent switching of the CAS signal, the logic for implementing the CAS signal is very complicated.

Accordingly, an object of the present invention is to store the interlaced video data inputted using video RAM as a dual port memory in the video RAM in order to solve the above problems. By interlaced output to the serial port of the video RAM to provide a digital video scan rate converter that can be implemented with a simpler logic.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

As shown in FIG. 1, the digital scan rate converter of the present invention includes a video RAM 30, a digital video signal generator 1 for applying 16-bit digital video data signals of an interlaced scanning method, The data bit extension unit 2 expands the 32-bit digital video signal into 32 bits so as to be processed by the dual port of the video RAM 30, and generates the address and transmits the video information corresponding to the address to the video RAM 30. The video RAM address generator 50 stores the video RAM address generator 50, the video RAM control signal generator 70 for controlling the video RAM 30, and the video signals transmitted from the video RAM 30. It is composed of an output unit 40 and a timing generator 80 to selectively output according to the signal, the schematic operation is as follows.

The 16-bit digital video signal output from the digital video signal generator 1 extends the 16-bit digital video signal to 32 bits before being stored in the video RAM 30 which is a frame buffer. The data bit expansion unit 20 including the latch unit 10 for controlling the latch unit 10 and the latch control signal generator 15 for controlling the latch unit 10 is set to 32 bits so as to be suitable for the operation timing of the video RAM 30. Is expanded.

The video RAM address generator 50 is configured to store digital video data 1p [0:31] extended to 32 bits in the data bit expansion unit 20 at an appropriate position of the video RAM 30. An address is output, and the video RAM control signal generator 70 outputs signals for controlling the video RAM 30 as shown in FIGS. 12 and 13, and a video RAM write cycle and a video RAM serial register. It is generated to match the conversion period, and the scan timing generator 80 provides a basic timing for outputting video data stored in the video RAM 30.

As illustrated in FIGS. 2 and 3, the data bit extension unit 20 includes a first latch 11 and an output terminal of the second latch 12 for processing pixel data of 16 bits, respectively. The latch unit 10 connected to the self-connected point a1, the inverter 17 commonly connected to the input terminal D and the inverted output terminal (/ Q) of the third latch 16, and the inversion of the third latch 16. And a latch control signal generator 15 having an output terminal / Q and a NAND gate 18 for receiving a signal transmitted from the inverter 17 as an input.

The latch control signal generator 15 uses a 16-bit pixel clock ([1:15]) generated from the digital video signal generator 1 as a synchronization signal and horizontal synchronization signal / HS (Horizontal Synchronizing). output signal of the NAND gate 18 which inputs the inverted signal of the first signal LDL outputted through the output terminal Q and the second signal LDH outputted through the inverted output terminal / Q with the signal) as a clear signal. Print / LOE.

In the latch unit 10, even-numbered data corresponding to the lower 16 bits among the pixel clocks P [1: 15] are latched in the first signal rising unit as shown in FIG. 4 in the first latch 11. The second latch 12 is outputted from the output terminal Q of the first latch 11 to Q [0:15], and odd-numbered data corresponding to upper 16 bits are latched on the rising part of the second signal LDH. Is outputted from the output terminal Q of the signal to Q [16:31], which is the first latch 11 and the second latch 12 when the output signal / LOE of the NAND gate 18 is low. Are all outputted from the clock terminal of < RTI ID = 0.0 >) < / RTI > and expanded to 32-bit data LP [0:31].

The video RAM control signal generator 70 is connected to the video RAM write control signal generator 71, the video RAM serial register conversion control signal generator 72, and the first multiplexer 73 as shown in FIG. The video RAM write control signal generator 71 may include a reset (/ reset) signal, a horizontal sync signal (/ HS), and a vertical sync signal (/ VS) from the digital video signal generator 1. ), A horizontal blanking signal (/ HBL), a vertical blanking signal (/ VBL), a first pixel clock (px1), and a second pixel clock (px2) doubled by the first pixel clock (px1). A video RAM row address control signal (/ MRAS) which is a video RAM control signal having a proper timing when writing video data to the video RAM 30 to perform a video RAM write cycle as shown in FIG. 12; Video RAM column address control signal (/ MCAS) and Video RAM write enable signal (/ MWE) Output, and wherein the reset signal is used as a signal for resetting of the entire block.

As shown in FIG. 6, the state transition of the video RAM control signals is a reset signal when the video RAM row address control signal MRAS of (a) is in an inactive state. ) Or when the horizontal blanking signal HBL or the vertical blanking signal VBL is inactive, no transition of the state occurs, and the horizontal blanking signal HBL is inactive and the first pixel clock px1 is inactive. In this active state, when the reset signal and the vertical blanking signal VBL are in an inactive state, a transition of the state occurs and becomes an active state.

On the other hand, when the video RAM row address control signal / MRAS is active, a transition occurs when the reset signal, the horizontal blanking signal HBL, or the vertical blanking signal VBL is active. do. At this time, if the state transition condition expression of (a), (b), (c) of FIG. 6 is '!', It indicates inactive state, if not, it indicates inactive state, false indicates inactive state, and true indicates active state. The base clock of the transition is the second pixel clock (px2).

The video RAM serial register conversion control signal generator 72 applies a first pixel clock px1, a reset signal / reset, and a second pixel clock px2 from the digital video signal generator 1. And the non-interlacing scanning horizontal synchronization signal (/ HSN), the non-interlacing scanning horizontal blanking signal (/ HBN), and the non-interlacing scanning vertical synchronization from the scan timing generating unit 80. A serial row address control signal (/ SRAL), a serial column address control signal (/ SCAS) and a gate signal (/ GATE) for receiving the signal / VSN and performing a video RAM serial register cycle as shown in FIG. ), And their state transitions are shown in (a), (b) and (c) of FIG. 7, and the symbols of the state transition condition equations are the same as those of FIG. 6.

As described above, the control signals output from the video RAM write control signal generator 71 and the video RAM serial register conversion control signal generator 72 are switched by the first multiplexer 73 so that the video RAM 30 is controlled. Is optionally entered. At this time, the switching operation of the first multiplexer 73 is controlled by a horizontal synchronization signal (/ HS). When the signal is in a low state, the switching operation is input to the B port of the first multiplexer 73. The signal to be output is output. When the signal is high, the signal input to the A port is output as a write cycle.

As shown in FIG. 8, the video RAM address generator 50 includes a first row address generator 51, a first column address generator 52, a third latch 53, and a second multiplexer ( A video RAM write address generator 58 including a video RAM write address generator 58, a second row address generator 61, a third multiplexer 64, and a video RAM serial register conversion address generator 58; And a fourth multiplexer 69 for selectively outputting a signal transmitted from the RAM write address generator 58 and the video RAM serial register conversion address generator 58.

The address generating principle of the video RAM address generating section 50 is to distinguish whether the currently input data is an odd field or an even field, as shown in FIG. An even number of addresses is generated, and an even field generates an odd number of row addresses.

Thus, in the write cycle, the column address clock is counted each time and generated. In the convert cycle, the row address counts each horizontal synchronization signal and increases by one each time a new line is output from the video RAM 30. Since only the tap point is specified due to the characteristics of the video RAM 30, the output is always output as Oh.

In the operation of the video RAM address generator 50, as shown in FIG. 11, in the first row address generator 51 of (a), the number of falling portions of the horizontal synchronization signal (/ HS) is designed. And outputs only A [10:17], and A9 checks whether the field is odd or even and generates an even or odd row address corresponding thereto. In the first column address generator 52 of (b), Only A [0: 9] is output, and thus the address A [0:17] output from each address generator 51 or 52 is a signal MRASel for selecting the A port or the B port of the second multiplexer 54. It is multiplexed by and output to MA [0: 8].

As shown in FIG. 12, the MRASel signal operates to output a row address when it is high and a column address when it is low, and the state transition is as shown in FIG.

On the other hand, in the second row address generator 61 of the video RAM serial register conversion address generator 68, the third multiplexer 64 is connected to the third multiplexer 64 by a selection signal SRASel for finally selecting the A port or B port selection signal. The multiplexed signal SA [0: 8] is output.

The operation of the SRASel signal outputs a row address only when it is high as shown in FIG. 13, and the state transition is as shown in (b) of FIG.

As described above, the present invention stores the data in the video RAM according to the video data rate input using the video RAM, which is a dual port memory, and stores the stored data again in a non-interlaced manner. By outputting the video signal, a video signal output from an image processing apparatus such as a television or a VCR can be displayed on a computer monitor, and a video inputted by adding a logic circuit that can interface with a host central processing unit can be used. The screen may be stored on a hard disk, automatically capture a video signal without interference from the host CPU, and may be applied to an external video signal input terminal in a multimedia system.

Claims (6)

A data bit expansion unit 20 for receiving an interlaced scanning digital video data signal and expanding the N times bit, and storing the bit-extended data from the data bit expansion unit 20 and outputting the data in an interlaced scanning method. And a video RAM address generator 50 for generating an address such that the digital video data is stored at an appropriate position of the video RAM 30 when the digital video data is stored in the video RAM 30. Interlacing the digital video data stored in the video RAM 30 and the video RAM control signal generator 70 for selectively outputting the digital video data stored in the video RAM 30. A scan timing generator 80 that adjusts timing to output in a manner of output, and an output portion 40 for outputting a non-interlaced scanning digital video signal. Scan speed conversion apparatus for a digital video signal, characterized in that provided. The first and second latches 11 and 12 of claim 1, wherein the data bit extension unit 20 receives the interlaced digital video data signals and latches them, respectively, and then outputs them through the same line. And a latch control signal generator (15) for controlling the first and second latches (11, 12). 2. The video RAM address generator 50 further includes a video RAM write address generator 58 for generating an address during a video RAM write cycle, and a video for generating an address during a video RAM serial register conversion cycle. A RAM serial register translation address generator 68, a video RAM write address generator 58, and a fourth multiplexer 69 for selectively outputting an address generated from the video RAM serial register translation address generator 68; Scan speed conversion apparatus for a digital video signal, characterized in that made by. 4. The video RAM write address generator 58 further comprises: a first row address generator 51 for generating a row address, a first column address generator 52 for generating a column address, and The third latch 53 and the first row address generator 51 and the first column address generator 52 generate an even number of row addresses if the input data is an odd field and an odd number of row addresses if the even field is an odd field. And a second multiplexer (54) for selectively outputting the address generated by the < RTI ID = 0.0 > 4. The video RAM write address generator 58 selectively selects the second row address generator 16, the second row address, and the address generated from the generator 61 for generating a row address. And a third multiplexer (64) for outputting. The video RAM control signal generator 70 of claim 1, wherein the video RAM control signal generator 70 generates a control signal for controlling the video RAM 30 and the output unit 40 during a video RAM write cycle. 71) and a video RAM serial register conversion control signal generator 72 and a video RAM write control signal generated to generate a control signal for controlling the video RAM 30 and the output unit 40 during the video RAM serial register conversion period. And a first multiplexer (73) for selectively outputting the control signals generated from the unit (71) and the video RAM serial register conversion control signal generator (72). .