JP3061158B2 - Video signal conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal conversion method, and more particularly to a signal conversion method for displaying a video signal from a computer device on a television receiver (hereinafter abbreviated as TV receiver).

[0002]

2. Description of the Related Art The image size of a video signal output from a computer device is set to a size smaller than the effective screen size of a monitor for a computer device so that the entire image including a peripheral portion is displayed on the monitor screen. ing. In general, there are few monitors for computer devices with a large screen, so if a large screen can be displayed on an easily available TV receiver, it is convenient for viewing by a large number of people. It is also possible to record a video signal by a computer device on a magnetic recording tape or the like and send it to a partner who does not have a monitor, reproduce the video signal on site, and display it on a TV receiver. In order to realize this, it is necessary to convert a line-sequential scanning video signal from a computer into an interlaced scanning video signal, which is a standard television signal, in addition to the above-described image size reduction processing. However, simply converting line-sequential scanning into interlaced scanning causes flicker (flickering of the screen), so that flicker-less processing is performed and output.

FIG. 4 is a block diagram of a main part of a conventional example for performing the above-mentioned processing. In FIG. 4, a video signal of line sequential scanning from a computer or the like input to a video signal input unit 21 is A The signal is input to a / D conversion unit 22 and converted into a digital signal. The compression processing of the number of scanning lines is performed by a scanning line compression unit 23, and the data of each frame is stored in a frame memory 24 (for example, for odd fields) and a frame memory 25 (for example, for even fields) at the same time, and thereafter, the data recorded in these frame memories is read out and input to the flickerless processing unit 26. Memory 24
The data of each odd-order scan line is mixed with the data of each even-order scan line from the frame memory 25 to generate an odd-order field, and then the data of each even-order scan line from the frame memory 25 is generated. A process of mixing data of each odd-order scanning line from the frame memory 24 to generate an even-order field is generated as a signal of the interlaced scanning, and this is repeated for each frame, and this signal is converted to a D / A signal. The conversion unit 27 converts the signal into an analog signal and outputs the analog signal. This causes flicker that occurs when there is a difference in luminance between the scan line of the odd-order field and the scan line of the even-order field adjacent to the scan line. I try to reduce it.

[0004]

According to the above-mentioned conventional method, two frame memories are required for flickerless processing. In view of the foregoing, the present invention performs a scanning line compression process on a line-sequential scanning video signal from a computer device, thereby reducing the vertical size of a computer image, and then using only one frame memory to perform flickering. It is another object of the present invention to provide a signal processing apparatus which performs a signal processing, converts this signal into an interlaced scanning signal, and outputs the signal.

[0005]

In order to solve the above-mentioned problems, the present invention provides an input section for inputting a line-sequential scanning video signal, and an A / D converter for converting the video signal from the input section into a digital signal. A scanning line compression unit for compressing the number of scanning lines of a signal from the A / D conversion unit; a line memory for recording scanning line data from the scanning line compression unit; and scanning line data read from the line memory A mixing unit for mixing data of the scanning line next to the scanning line, and a frame memory for recording the data of the scanning line from the mixing unit frame by frame.
A scan converter for reading data recorded in the frame memory separately for odd and even fields, and converting the data into an interlaced scan signal; a D / A converter for converting a signal from the scan converter to an analog signal; A clock signal generation unit that generates a required clock signal based on a synchronization signal input simultaneously with the signal and generates a clock signal that is used as a reference for the operation of each unit, and is analog-converted by the D / A conversion unit. It is an object of the present invention to provide a video signal conversion method for outputting a video signal.

[0006]

With the above arrangement, in the video signal conversion system according to the present invention, in order to convert a video signal from a computer or the like into a digital signal and reduce the vertical size of an image, for example, the number of scanning lines is reduced. A process for compressing from six lines to five lines is performed, and a process for reducing flicker caused by conversion into an interlaced scanning signal is performed using one frame memory, converted to an interlaced scanning signal, and converted to an analog signal. And output.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a video signal conversion system according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of a main part of an embodiment of a video signal conversion system according to the present invention. In the figure, reference numeral 1 denotes a video signal input unit which inputs a video signal of line sequential scanning from a computer device or the like. 2 is A /
The D converter converts the video signal from the video signal input unit 1 into a digital signal. Reference numeral 3 denotes a line memory for recording data of each scanning line from the A / D converter 2. Reference numeral 4 denotes a synchronizing signal input unit for inputting a synchronizing signal output from a computer or the like simultaneously with the video signal. Reference numeral 5 denotes a clock signal generator which generates a required clock signal based on the horizontal synchronization signal from the synchronization signal input unit 4. Reference numeral 6 denotes an interpolation coefficient calculation unit which calculates a required interpolation coefficient for each order of the scanning line of the video signal. A multiplier 7 multiplies the data of the scanning line read from the line memory 3 by an interpolation coefficient of the order of the scanning line from the interpolation coefficient calculator 6. Numeral 8 denotes a multiplier which multiplies the data of the scanning line next to the scanning line read from the line memory 3 by the interpolation coefficient of the order of the scanning line from the interpolation coefficient calculator 6. Reference numeral 9 denotes an adder for adding data from the multipliers 7 and 8. 10 is a multiplier,
Multiply the required coefficient.

Reference numeral 11 denotes a line memory for recording data of each scanning line from the multiplier 10. 12 is a mixing unit, line memory
The data of the next scanning line from the multiplier 10 is mixed with the data of the scanning line read from 11. A frame memory 13 records data of each scanning line from the mixing unit 12 for one frame. Reference numeral 14 denotes a scan converter which reads out frame data recorded in the frame memory 13 by dividing the data into odd fields and even fields. Reference numeral 15 denotes a D / A converter, which converts data from the scan converter 14 into an analog signal. A control unit 16 controls each unit of the apparatus.

Next, the operation of the video signal conversion system according to the present invention will be described. A line-sequential scanning video signal from a computer device is input via a video signal input unit 1. This video signal is input to the A / D converter 2 and is converted into a digital signal. The converted data is transferred to the line memory 3,
It is recorded one scanning line at a time. On the other hand, a synchronization signal output simultaneously with the video signal from a computer device or the like is input to the synchronization signal input unit 4. This synchronization signal is input to the clock signal generation unit 5 and is generated as, for example, a clock signal having a frequency that is an integral multiple of the frequency of the horizontal synchronization signal. And
The interpolation coefficient calculation unit 6 calculates a required interpolation coefficient for each order of the scanning line based on the signal from the clock signal generation unit 5.

The data of the scanning line written in the line memory 3 and the data of the scanning line next to the scanning line are:
The processing is performed by the multiplier 7 or the multiplier 8, the adder 9, and the multiplier 10, respectively. These processes will be described with reference to a conceptual diagram of scanning lines shown in FIG. In the figure, for example, the horizontal scanning frequency of a video signal from a computer device is about 31 KH
In the case of a signal of z (kilohertz) line-sequential scanning method, when the number of scanning lines in one frame is 480, image data of 480 lines is compressed so as to be displayed by 400 scanning lines, that is, horizontal scanning. This is an example of the case where the number of lines is reduced to 5/6.

That is, the line memory 3 stores L1
The data of the (first scanning line) is read out, transferred to the multiplier 7, multiplied by the interpolation coefficient 5/5 of the scanning line from the interpolation coefficient calculation unit 6 via the control unit 15, and , The data of the scanning line L2 next to the scanning line from the A / D converter 2 is input to the multiplier 8, and the interpolation coefficient 1/5 of the scanning line from the interpolation coefficient calculator 6 is calculated. Multiply. After the data from the multiplier 7 and the data from the multiplier 8 are input to the adder 9 and added, the multiplier 10 multiplies the data by a required coefficient 5/6, whereby L1 '= (L1 × 5/5 + L2 × 1/5) × 5/6, as shown in FIG. Further, L2 ′ = (L2 × 4/5 + L3 × 2/5) × 5/6, L3 ′ = (L3 × 3/5 + L4 × 3/5) × 5/6, L4 ′ = (L4 × 2 / 5 + L5 x 4/5) x 5/6, L5 '= (L5 x 1/5 + L6 x 5/5) x 5/6, ..., ..., ..., ..., ... 5 scan lines are generated by the scan line data, and the same processing is performed for each of the subsequent scan lines. As a result, the image data of 480 scan lines in one frame becomes 400 scan lines. Is converted into image data by the above. In the above description, the data from the multipliers 7 and 8 are added by the adder 9 and then multiplied by the coefficient 5/6 by the multiplier 10. However, in the multipliers 7 and 8, The coefficient 5
/ 6, and the multiplier 10 may be omitted.

Next, the operation of the flickerless processing will be described with reference to a conceptual diagram shown in FIG. The data of each scanning line processed by the multiplier 10 is input to a line memory 11 and is recorded one scanning line at a time. And the recorded scanning line, for example,
The data of L1 'is read and input to the mixing unit 12, and at the same time, the data of the next scanning line L2' from the multiplier 10 is input to the mixing unit 12, and these data are mixed and scanned. A line Lo1 (odd order, first line) is generated, the generated data is recorded in the frame memory 13, and then the data of L2 'is read out from the line memory 11 and input to the mixing unit 12, where the multiplier 10 Scan line L next to the next scan line L2 '
The data of 3 'is input to the mixing unit 12 and mixed to form the scanning line Le.
1 (even-order / first-order), record this data in the frame memory 13, and thereafter generate data of each scanning line such as Lo2, Le2,. Is recorded in the frame memory 13. After these recordings are completed, the frame memory 13 sends
For example, the data of the scanning lines Lo1, Lo2, Lo3,... Are read and generated in odd fields, and then the data of the scanning lines Le1, Le2, Le3,.

As described above, the line-sequential scanning type video signal input to the video signal input unit 1 is obtained by compressing the number of scanning lines to 5/6, performing flickerless processing, and converting the signal into an interlaced scanning type signal. Becomes This signal is input to the D / A converter 15, converted into an analog signal and output.

[0014]

As described above, according to the video signal conversion system according to the present invention, the video signal of the line sequential scanning from the computer device performs a compression process on the number of scanning lines, performs a flickerless process, and Since the image is converted into an interlaced scanning signal and output, when the image is input to the TV receiver, the computer image falls within the effective screen of the receiver, and an image free from flicker due to the interlaced scanning signal conversion is displayed. In the flickerless processing, two frame memories are conventionally required, but in the method according to the present invention, only one frame memory is required.

[Brief description of the drawings]

FIG. 1 is a main block diagram of an embodiment of a video signal conversion system according to the present invention.

FIG. 2 is a diagram illustrating a scanning line compression processing operation of a video signal conversion system according to the present invention.

FIG. 3 is a diagram illustrating a flickerless processing operation of a video signal conversion system according to the present invention.

FIG. 4 is a main block diagram showing an example of a conventional video signal conversion system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Video signal input part 2 A / D conversion part 3 Line memory 4 Synchronization signal input part 5 Clock signal generation part 6 Interpolation coefficient calculation part 7 Multiplier 8 Multiplier 9 Adder 10 Multiplier 11 Line memory 12 Mixing part 13 Frame memory 14 Scan converter 15 D / A converter 16 Controller

Claims (1)

(57) [Claims] 1. An input section for inputting a line-sequential scanning video signal, an A / D conversion section for converting a video signal from the input section into a digital signal, and a scanning line number of a signal from the A / D conversion section. A scanning line compression section for performing compression processing, a line memory for recording scanning line data from the scanning line compression section, and a mixture for mixing scanning line data read from the line memory and data for the next scanning line. A frame memory for recording the data of the scanning lines from the mixing unit one frame at a time;
A scan converter for reading data recorded in the frame memory separately for odd and even fields, and converting the data into an interlaced scan signal; a D / A converter for converting a signal from the scan converter to an analog signal; A clock signal generation unit that generates a required clock signal based on a synchronization signal input simultaneously with the signal and generates a clock signal that is used as a reference for the operation of each unit, and is analog-converted by the D / A conversion unit. A video signal conversion method for outputting a video signal.