JP3057259B2 - Video camera signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is particularly suitable for use in synchronously driving a plurality of video cameras when constructing a security system in which a plurality of video cameras are installed. The present invention relates to a signal processing circuit of a camera.

[Summary of the Invention]

The present invention relates to a signal processing circuit of a video camera suitable for synchronously driving a plurality of video cameras,
A synchronization pulse is generated from a synchronization generation circuit according to the output of the voltage-controlled oscillator, and the phase of the synchronization pulse output from the synchronization generation circuit is compared with the phase of a signal formed based on a commercial AC power supply, By controlling the voltage-controlled oscillator based on the phase comparison output, it is possible to reduce the effects of phase distortion and amplitude distortion of the commercial AC power supply when AC locking is performed.

[Conventional technology]

2. Description of the Related Art A security system in which a video camera is provided in each room and the situation of each room is centrally monitored at one place has become widespread. When constructing such a security system, make sure that synchronization is not lost when switching cameras.
It is necessary to operate a plurality of video cameras synchronously.

In order to operate multiple video cameras synchronously, it is usually necessary to send a common synchronization signal from the controller to each video camera.However, as in the United States, the frequency of the commercial AC power supply matches the field frequency of the television. In some countries, by using a commercial AC power supply, a plurality of video cameras can be operated synchronously without sending a synchronization signal from the controller to each video camera. Such a synchronous operation of a plurality of video cameras using a commercial AC power supply is called an AC lock.

6 and 7 show an example of a conventional video camera in which a plurality of video cameras are operated synchronously using a commercial AC power supply. In this example, the frequency of the commercial AC power supply is 60 Hz, and a television system having a field frequency of 60 Hz is adopted.

FIG. 10 is an example in the case where an image pickup tube is used. In FIG. 10, reference numeral 51 denotes a synchronization generation counter that generates a vertical pulse V _PLS and a horizontal pulse H _PLS . The synchronization occurrence counter 51
Reference clock CK (for example, frequency 4f _sc (f _sc = 14.3MH)
The horizontal pulse _HPLS and the vertical pulse _VPLS are formed by counting z)). The synchronization generation counter 51 is supplied with a vertical reset signal from the shaping circuit 53.

Horizontal pulse H _PLS and vertical pulse V _PLS from sync generator counter 51 is supplied to the deflection circuit 52. In the deflection circuit 52, the horizontal pulse _HPLS and the vertical pulse from the synchronization generation counter 51 are output.
Based on _VPLS , sawtooth waves for horizontal deflection and vertical deflection are formed. The output of the deflection circuit 52 is supplied to the image pickup tube 54, and the electron beam is scanned according to the output of the deflection circuit 52.

A subject image is picked up by the pick-up tube 54, and the picked-up output is supplied to the video signal processing circuit 55. Video signal processing circuit 55
Then, the composite synchronization signal from the synchronization generation counter 51 is added to the imaging output of the imaging tube 54, and a video signal of a television system with a field frequency of 60 Hz is formed. This video signal is extracted from the output terminal 56.

The commercial AC power supply 57 having a frequency of 60 Hz is sent to the shaping circuit 53, and the shaping circuit 53 outputs a frequency 60 corresponding to the commercial AC power supply 57.
A pulse signal of Hz is formed. The pulse signal having the frequency of 60 Hz is supplied to the vertical reset terminal of the synchronization generation counter 51.

The synchronization generation counter 51 is reset by a pulse signal having a frequency of 60 Hz from the shaping circuit 53. Thereby, the vertical cycle of the video signal and the phase of the commercial AC power supply 57 are forcibly synchronized.

FIG. 7 is an example using a solid-state imaging device. In FIG. 7, a synchronization generation counter 61 counts a reference clock CK, thereby generating a horizontal pulse _HPLS and a vertical pulse VPLS.
With _PLS, forming a field identification signal _{S F.} The horizontal pulse H _PLS and vertical pulse V _PLS, the field identification signal S _F is supplied to the clock driver 62. The clock driver 62 forms a horizontal pixel transfer clock and a vertical pixel transfer clock based on the horizontal pulse _HPLS and the vertical pulse _VPLS . The horizontal pixel transfer clock and the vertical pixel transfer clock are supplied to a solid-state image sensor 64 such as a CCD image sensor.

A subject image is captured by the solid-state imaging device 64, and the captured output is supplied to a video signal processing circuit 65. In the video signal processing circuit 65, the composite synchronization signal from the synchronization generation counter 61 is added to the imaging output of the solid-state imaging device 64, and a television video signal having a field frequency of 60 Hz is formed.
This video signal is extracted from the output terminal 66.

The waveform of the commercial AC power supply 67 having a frequency of 60 Hz is shaped by a shaping circuit 63 to form a pulse signal having a frequency of 60 Hz. The pulse signal having the frequency of 60 Hz is supplied to the synchronization generation counter 61 as a reset signal.

The reset signal is supplied to the synchronization generation counter 61 from the output of the shaping circuit 63. This allows the synchronization occurrence counter
61 is forcibly reset in synchronization with a commercial AC power supply having a frequency of 60 Hz. Thereby, the vertical cycle of the video signal and the phase of the commercial AC power supply 62 are forcibly synchronized.

[Problems to be solved by the invention]

In the video signal processing circuit shown in FIGS. 6 and 7, the synchronization generation counters 51 and 61 are forcibly reset by the outputs of the shaping circuits 53 and 63 for shaping the commercial power supplies 57 and 67,
The vertical cycle is synchronized with the AC commercial power supply.

However, the frequency and amplitude of the commercial AC power supply are not strictly managed, and the commercial AC power supply has slight phase distortion and amplitude distortion.

In the conventional video signal processing circuit shown in FIGS. 6 and 7, if the commercial AC power supplies 57 and 67 have time-axis fluctuation components, the number of horizontal scanning lines differs for each field, and vertical jitter may occur. is there.

Further, in the example using the image pickup tube 54 shown in FIG. 6, if the commercial AC power supply 57 fluctuates with time, the number of scanning lines is the same in the even field and the odd field, and interlaced scanning may not be performed. . If interlaced scanning is not possible,
The resolution is degraded, and the problem that the image pickup screen cannot be recorded on the VTR arises.

In the example using the solid-state imaging device 54 shown in FIG. 7, when the commercial AC power supply 67 fluctuates in time and the number of scanning lines is the same in the even field and the odd field, the vertical shift register is changed to the even field and the odd field. , The operation cannot be performed. Therefore, the solid-state imaging device
In the example using 64, the clock driver 62 needs to be configured as a PLL. However, since such a PLL must be configured using a high-speed element,
If the 62 is configured as a PLL, the cost is greatly increased.

Therefore, an object of the present invention is to provide a signal processing circuit of a video camera capable of performing a stable operation even when a phase distortion or an amplitude distortion is generated in a commercial AC power supply or when noise is generated when an AC lock is performed. It is in.

[Means for solving the problem]

According to the present invention, a voltage-controlled oscillator 2 whose oscillation frequency is controlled in accordance with a control signal, a synchronization generation circuit 1 that generates a synchronization pulse in accordance with an output of the voltage-controlled oscillator 2, and an output from the synchronization generation circuit 1 A phase comparison circuit 3 for comparing the phase of the synchronization pulse with the phase of a signal formed based on the commercial AC power supply 11, and controls the voltage-controlled oscillator 2 by the output of the phase comparison circuit 3. 1 is a signal processing circuit of a video camera.

[Action]

The sample and hold circuit 3 compares the phase of the vertical synchronization pulse _VPLS from the synchronization generation counter 1 with the phase of the commercial AC power supply 11 delayed by a predetermined amount by the _monomulti 14, and controls the VCO 2 with this comparison output to generate synchronization. Counter 1 outputs VCO2 output f _VCO
Are used to form a phase control loop such as that formed by the horizontal pulse _HPLS and the vertical pulse _VPLS . When the video camera is operated synchronously using the commercial AC power supply, such a phase control loop absorbs phase distortion and amplitude distortion in the commercial AC power supply 11, and the horizontal pulse _HPLS from the synchronization generation counter 1 and the vertical synchronization Pulse _VPLS stabilizes.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, 1 is a synchronization occurrence counter. The synchronization generation counter 1 is supplied with a reference signal f _VCO (for example, 4f _sc ) from a VCO (voltage controlled oscillator) 2. A comparison output of the phase of the signal based on the commercial AC power supply and the phase of the vertical pulse _VPLS is supplied from the sample and hold circuit 3 to the VCO 2 via the low-pass filter 4 and the amplifier 5. The oscillation frequency of VCO2 is controlled according to the phase comparison output. VCO2
A Colpitts-type device having a configuration in which an oscillation frequency is varied by applying a control voltage to a variable capacitance diode can be used. The amplifier 5 is for improving the control gain, and a CMOS configuration is used as the amplifier 5.

Synchronization generating counter 1 counts the reference signal f _VCO from VCO2, together with the horizontal pulses H _PLS and vertical pulse V _PLS, forming a field identification signal S _F. The horizontal pulse _HPLS and the vertical pulse _VPLS are supplied to the clock driver 6.

The clock driver 6 forms a horizontal transfer clock and a vertical transfer clock based on the output of the synchronization generation counter 1.

The horizontal transfer clock and the vertical transfer clock from the clock driver 6 are supplied to a solid-state image sensor 7 such as a CCD image sensor. The solid-state imaging device 7 is driven by the horizontal transfer clock and the vertical transfer clock.

A subject image is captured by the solid-state imaging device 7, and the captured output is supplied to a video signal processing circuit 8. In the video signal processing circuit 8, the synchronization generation circuit 1
A composite sync signal from the
The video signal of the television system is formed. This video signal is taken out from the output terminal 9.

The vertical pulse _VPLS from the synchronization generation counter 1 is supplied to the waveform shaping circuit 10. In the waveform shaping circuit 10, a reset pulse S _R and the sample hold pulse S _H is formed. Reset pulses S _R and the sample hold pulse S _H from the waveform shaping circuit 10 is supplied to the sample hold circuit 3.

A commercial AC power supply 11 having a frequency of 60 Hz is supplied to a power supply circuit 12 and also supplied to a monostable multivibrator 14 (hereinafter abbreviated as a monomulti) via a photocoupler 13. The power supply circuit 12 forms a power supply for each unit.

The time constant of the mono-multi 14 can be set by the lock switching circuit 15 in three ways for each delay amount of 120 degrees. Also,
The time constant of the mono multi 14 can be finely adjusted.

The monomulti 14 forms a pulse signal corresponding to an AC commercial power supply having a frequency of 60 Hz and delayed by a predetermined amount. The output of the mono multi 14 is supplied to the sawtooth wave generation circuit 16.

The sawtooth wave generation circuit 16 forms a sawtooth wave synchronized with the output of the mono multi. The sawtooth wave is supplied to the sample and hold circuit 3.

Sample-and-hold circuit 3, after being reset by the reset pulse S _R obtained by shaping the vertical synchronizing pulses V _PLS, the sample-and-hold pulse S _H, to sample and hold a saw-tooth wave from the sawtooth wave generating circuit 16.
Thereby, the vertical pulse V _PLS from the synchronization generation counter 1 is obtained.
Then, a phase comparison output with the commercial AC power supply 11 via the mono-multi 14 is obtained.

The output of the sample hold circuit 3 is supplied to the VCO 2 via the low pass filter 4 and the amplifier 5. The oscillation frequency of VCO2 is controlled by the output of the sample and hold circuit 3 via the low pass filter 4 and the amplifier 5.

As described above, in one embodiment of the present invention, the phase of the vertical synchronization pulse _VPLS from the synchronization generation counter 1 and the phase of the commercial AC power supply 11 delayed by a predetermined amount by the monomulti 14 are sampled and held by the sample and hold circuit 3. comparison, controls the VCO2 in this comparison output, the phase control loop which forms a horizontal pulse H _PLS and vertical pulse V _PLS synchronously generating counter 1 by using the output f _VCO of VCO2 is configured.

That is, when a commercial AC power supply 11 as shown in FIG. 2A is supplied, a shaped pulse corresponding to the AC commercial power supply is output from the photocoupler 13 as shown in FIG. 2B. The output of this photocoupler 13 is a monomulti 14
, And the mono-multi 14 is triggered by the rising edge of the output of the photocoupler 13. As a result, a pulse as shown in FIG. 2C is output from the mono multi 14. In the sawtooth wave generating circuit 16, as shown in FIG.
A saw-tooth wave is formed in synchronization with the fall of the output of the mono-multi 14.

On the other hand, the synchronization generation counter 1 outputs a vertical pulse V _{PLS as} shown in FIG. _2E . From the waveform shaping circuit 10 at the rising edge of the vertical pulse V _PLS, the reset pulse S _R as shown in FIG. 2 F is output, the falling of the reset pulse S _R, as shown in FIG. 2 G The sample hold pulse _SH is output.

The sample hold circuit 3 samples and holds the sawtooth wave shown in FIG. 2D by the sample hold pulse _SH (FIG. 2G). A phase difference signal is obtained from the output of the sample hold 3, and the phase difference signal is supplied to the VCO 2 via the low pass filter 4 and the amplifier 5.

By such a phase control loop, the vertical pulse _VPLS output from the synchronization generation counter 1 is synchronized with the commercial AC power supply 11 delayed by a predetermined amount by the _monomulti 14. Along with this, even if the commercial AC power source 11 has occurred phase distortion and Fufuku distortion is absorbed distortion by the phase control loop, the horizontal pulses H _PLS and vertical sync pulses V _PLS from the synchronous generator counter 1, the phase No distortion or amplitude distortion occurs.

With such a phase control loop, the horizontal pulse H _PLS and the vertical pulse V _PLS from the synchronization generation counter 1 are stabilized, so that it is not necessary to use a PLL having a PLL configuration as the clock driver 6 and cost reduction can be achieved.

It should be noted that such a phase control loop includes a commercial AC power supply 11 having a frequency of 60 Hz and a reference signal f having a frequency of 4 f _SC (14.32 MHz).
Since the frequency division ratio is compared with the _VCO , the frequency division ratio N becomes very large. Therefore, even if the reference signal f _VCO fluctuates by several tens of kHz, the phase control loop remains locked, but since the frequency division ratio N is large, the jitter on the actual screen can be almost ignored.

Note that, in this example, the amplifier 5 is provided so that the dynamic range can be widened with a low-voltage (for example, 5 V) VCO2.

Further, if the commercial power supply 11 is lost, all operations are stopped, so that a free-run state cannot occur in principle. For this reason, a configuration is possible in which a saw-tooth wave is formed from a signal based on a commercial AC power supply, and the saw-tooth wave is sampled to determine a phase difference. If there is a free-run state, a trapezoidal wave must be used, the configuration becomes complicated, and a large dynamic range cannot be obtained. Further, since the configuration is such that the phase difference is obtained by sampling the sawtooth wave, it is not necessary to use a high-speed element, and the error signal is continuous, so that the configuration of the low-pass filter 4 can be simplified.

As described above, in one embodiment of the present invention, the time constant of the mono-multi 14 is switched between three levels. FIG. 3 shows a case where the delay amount of the mono-multi 14 is increased by 120 degrees. FIG. 4 shows a case where the delay amount of the mono multi 14 is increased by 240 degrees. As shown in FIGS. 2 to 4, when the delay amount of the monomulti 14 is switched, the phase relationship between the commercial AC power supply 11 and the vertical pulse _VPLS can be set in three stages every 120 degrees. As described above, since the phase relationship between the commercial AC power supply 11 and the vertical pulse _VPLS can be set in three stages every 120 degrees, the commercial AC power supply 11 is formed by converting three-phase AC into single-phase AC. Even if the connection at the time of conversion is different for each commercial power supply of each camera, it can be handled.

FIG. 5 is an example of a security system to which the present invention can be applied.

In FIG. 5, 21A, 21B, 21C and 21D are video cameras to which the present invention is applied. These camcorders
21A to 21D are installed in separate rooms, respectively.

Outputs of these video cameras 21A to 21D are supplied to a monitor 23 via a selector 22. The selector 22 selects a necessary video camera among the video cameras 21A to 21D. The imaging screens of the selected video cameras 21A to 21D are displayed on the monitor 23. The outputs of the plurality of video cameras 21A to 21D may be simultaneously displayed on the monitor 23.
While watching the screen displayed on the monitor 23, the state of each room is monitored.

When constructing such a security system, unless the video cameras 21A to 21D are operated synchronously, the selector
When switching a desired video camera from among the plurality of video cameras 21A to 21D in 22, a synchronization disorder occurs.

Power is supplied from the commercial AC power supply 24 to the video cameras 21A to 21D. The frequency of this commercial AC power supply 24 is 60 Hz,
It matches the field frequency of video cameras 1A to 1D. In the video cameras 21A to 21D, as described above, the operating power of each unit is formed from the commercial AC power supply 24, and each video camera 21A is
Synchronization of ~ 21D is achieved.

〔The invention's effect〕

According to the present invention, the sample-hold circuit 3 compares the phase of the vertical synchronizing pulse _VPLS from the synchronizing counter 1 with the phase of the commercial AC power supply 11 delayed by a predetermined amount by the _monomulti 14, and uses this comparison output as the VCO2 And the VCO2 is controlled by the synchronous generation counter 1 and the output f of the VCO2 is controlled by the synchronous generation counter 1.
A phase control loop is formed by the _VCO using the horizontal pulse _HPLS and the vertical pulse _VPLS . When the video camera is operated synchronously using the commercial AC power supply, such a phase control loop absorbs phase distortion and amplitude distortion in the commercial AC power supply 11, and the horizontal pulse _HPLS from the synchronization generation counter 1 and the vertical synchronization Pulse _VPLS stabilizes. For this reason, the number of horizontal lines does not differ for each field due to the phase variation and amplitude variation of the commercial AC power supply, and the number of horizontal lines does not become the same between the even field and the odd field. It is possible to prevent intermittent scanning from being disabled. Further, since the horizontal pulse _HPLS and the vertical synchronizing pulse _VPLS are stable, the clock driver does not need to be configured as a PLL, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIGS. 2 to 4 are waveform diagrams used to explain one embodiment of the present invention, and FIG.
FIG. 1 is a block diagram of an example of a security system to which the present invention can be applied. FIGS. 6 and 7 are block diagrams of an example of a conventional video camera and other examples. Explanation of main symbols in the drawing 1: Synchronous occurrence counter, 2: VCO, 3: Sample and hold circuit, 6:
Clock driver, 7: solid-state image sensor, 11: commercial AC power supply, 1
4: Mono multi.

Continuation of the front page (56) References JP-A-63-16755 (JP, A) JP-A-2-57669 (JP, A) JP-A-58-196769 (JP, A) JP-A-58-200139 (JP, A) , A) Japanese Utility Model Hei 3-69974 (JP, U) Japanese Utility Model Application Sho 53-126426 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/222-5/257

Claims (1)

(57) [Claims] An oscillation frequency is controlled according to a control signal,
Voltage-controlled oscillation means for outputting a reference signal; synchronization generation means for generating a horizontal synchronization pulse and a vertical synchronization pulse in accordance with the reference signal output from the voltage-controlled oscillation means; output from the synchronization generation means A sample and hold pulse generating means for generating a sample and hold pulse based on the vertical synchronization pulse, a sawtooth wave generating means for generating a sawtooth wave synchronized with an AC component of a commercial AC power supply, A sample-and-hold means for performing sample-and-hold by a sample-and-hold pulse generated by the sample-and-hold pulse generation means; and a video camera signal adapted to control the voltage-controlled oscillating means in accordance with an output of the sample and hold means Processing circuit.