JP3049710B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device that stores a plurality of partially different data.

[Conventional technology]

Conventionally, this type of non-volatile semiconductor storage device stores data that is smaller than the storage capacity of the device.

[Problems to be solved by the invention]

Since the conventional nonvolatile semiconductor memory device described above stores data of a storage capacity or less, if the storage capacity is required to be larger, the storage capacity may be increased or a plurality of nonvolatile semiconductor memories may be used. A storage device will be used. In particular, when a plurality of pieces of data that are partially common are stored, there is a disadvantage in that a storage capacity more than necessary is required despite the common data.

An object of the present invention is to provide a nonvolatile semiconductor memory device capable of storing a plurality of data having common data in a part thereof without greatly increasing the storage capacity.

[Means for solving the problem]

According to the nonvolatile semiconductor memory device of the present invention, for the first and second data partially common, a data area for storing a common part and a different area formed in an empty area other than the data area are provided. A ROM section having a sub data area for storing, an address determination circuit for receiving an address signal and determining whether or not the address is in the data area of the ROM section; and an address conversion data signal. Activation / deactivation is controlled, and an output of the address determination circuit is input. When an address of a different portion between the first and second data is input, an address designating the data area and the sub data A first and a second address conversion circuit for replacing an address designating an area; and It is configured to provide access of the serial data area into the sub data area.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a nonvolatile semiconductor memory device showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment employs an input address signal 8
, Two address conversion circuits 2 and 3 for converting the output of the determination circuit 1, and accessed by the conversion circuits 2 and 3,
A ROM section 4 having a data area and a vacant area and having a sub data area in the vacant area, and data read from the ROM section 4 controlled by the data signal 6 of the address determination circuit 1 are determined, and the result is output. And a data determination circuit 5 that outputs the signal 12. Further, the above-described address conversion circuits 2 and 3 provide an address conversion data signal 7
And directly via the inverter 13. Further, 9 and 10 are internal address signals, and 11 is an internal data signal.

FIG. 2 is a conceptual diagram of data stored in a ROM unit in FIG.

As shown in FIG. 2, the ROM section has a data area 14 of a common section, an empty area 15, and a sub data area 16 for storing a different part between data 1 and data 2 stored in the empty area 15. ing.

Next, the circuit operation of the storage device will be described with reference to FIGS.

First, when an input address signal is input, the address determination circuit 1 determines whether or not the address is in the data area 14. If it is in the data area 14, “0” is transferred to the data signal 6 and the internal address signal 9 is transferred.
, The input address is transferred as it is. At the same time, "1" is sent to the address conversion data signal 7 if the data to be accessed is data 1, and "0" is sent to the address conversion data signal 7 if the data 2 is data 2. The first and second address conversion circuits 2 and 3 operate when "1" is sent from the address conversion data signal 7. The address conversion circuit 3 has a function of exchanging the addresses of the data area 14 and the sub-data area 16 when the address of the difference between the data 1 and the data 2 is input.

Next, after the conversion process, the address signal is sent out as the internal address signal 10, so that the ROM unit 4 is accessed. The data in the ROM section 4 is read as an internal data signal 11 and transferred to the data determination circuit 5. The data determination circuit 5 receives the data signal 6 from the address determination circuit 1.
If the signal sent as “0” is “0”, the data sent from the internal data signal 11 is transmitted as the output signal 12 ignoring it.

On the other hand, if the input address is not in the data area 14, “1” is transmitted to the data signal 6 by the address determination circuit 1 and the address “0000” is transmitted to the internal address signal 9. Therefore, the data determination circuit 5
When the signal sent from the data signal 6 is “1”, the data sent from the internal data signal 11 is ignored and the output signal 12 is ignored.
Data "0" is sent.

As described above, it is possible to access the two types of data areas forming the ROM 4.

FIG. 3 is a block diagram of a nonvolatile semiconductor memory device showing a second embodiment of the present invention.

As shown in FIG. 3, this embodiment is an example in which the address determination circuit is provided in the first and second address conversion circuits 2 and 3, and the data determination circuit is omitted. In this case RO
The problem is solved by providing a specific area in the M section 4. That is, in this embodiment, the input address signal 8 is converted by the first address conversion circuit 2 and the second address conversion circuit 3, the internal address signal 10 is created, and the ROM section 4 is accessed and read out. The signal 12 is obtained. The address conversion data signal 7 and the inverter 13 are the same as in the first embodiment.

FIG. 4 is a conceptual diagram of data stored in the ROM unit in FIG.

As shown in FIG. 4, the ROM section 4 comprises a data area 14 for storing data 1 and a vacant area 15, and the vacant area 15 has a sub-data area 16 for storing a different part between data 1 and data 2. Is provided. Further, in the empty area 15, a data “0” section 17 in which data “0” is stored at a specific address, for example, 7F7F, is provided.

In the second embodiment, the first address conversion circuit 2 and the second address conversion circuit 3 have a function of determining an address. Otherwise, a specific address (for example, 7F7F) is output as the internal address signal 10. However, in the ROM section 4, since the data at a specific address (for example, 7F7F) is the data "0" section 17,
Data "0" is sent to the output signal 12.

As described above, in the present embodiment, by providing the specific area 17 different from the sub data area 16 in the empty area 15 of the ROM 4, it is possible to realize the same function as the above-described first embodiment with a simple configuration. There is an advantage that can be.

〔The invention's effect〕

As described above, the nonvolatile semiconductor memory device of the present invention has the ROM portion having the data area and the empty area of the address determination circuit and the address conversion circuit, and has the storage area by providing the sub data area in the empty area. Since a plurality of types of data, some of which are common, can be stored without increasing the storage capacity, the storage capacity can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of a nonvolatile semiconductor memory device showing a first embodiment of the present invention, FIG. 2 is a conceptual diagram of ROM section data in FIG. 1, and FIG. 3 is a second embodiment of the present invention. FIG. 4 is a conceptual diagram of the ROM data in FIG. 3, and FIG. 1 ... address determination circuit, 2,3 ... address conversion circuit,
4 ROM part, 5 data determination circuit, 6 data signal, 7 address conversion data signal, 8 input address signal, 9, 10 internal address signal, 11 internal data signal 12 ... output signal, 13 ... inverter, 14 ... data area, 15 ... empty area, 16 ... sub data area,
17 ... Specific area (data "0" part).

Claims (1)

(57) [Claims] 1. A data area for storing a common part and a sub-area for storing a different part formed in an empty area other than the data area for first and second data partially common. A ROM section having a data area, an address determination circuit for receiving an address signal and determining whether or not the address is in the data area of the ROM section; And an address for specifying the data area and an address for specifying the sub-data area when an output of the address determination circuit is input and an address of a different portion between the first and second data is input. And the first and second address conversion circuits, and the output of the first and second address conversion circuits, the ROM
An access to the data area and the sub data area of a section.