JP3029170B2 - Data transmission method and apparatus, and asynchronous control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of transmitting data between a plurality of central processing units (CPUs) or controllers operating asynchronously, and in particular, to data which guarantees the synchronism of data which is indispensable for a control system and the like. It relates to a transmission system.

[0002]

2. Description of the Related Art As a data transmission system between CPUs in a control system or the like, a packet exchange system in which data is synchronized in CPU units is used. Sending CPU
After the transmission editing process for dividing transmission data into packets of a fixed length is performed, the transmission data writing process to the network is performed when the receiving CPU is in a transmission data waiting state. The receiving CPU performs reading processing and reception editing processing of the received data from the network line, and after that, waits for the next data and notifies the transmitting CPU of the state.

On the other hand, as a method for speeding up data transmission between CPUs, there is a memory transfer method in which transmission data editing and transfer to a network are distributed to reduce the computer load.

[0004]

According to the above-described packet switching system, synchronization of transmission data is guaranteed, but transmission / reception processing takes time, which hinders an increase in transmission speed. For this reason, it is difficult for a CPU of a control system or the like to increase the speed of a control operation, which is an essential task.

On the other hand, according to the memory transfer method, a transmission sub-processor is provided in addition to the CPU of the controller, and the speed of data transmission can be increased by decentralizing the transmission / reception processing. ), The transmission data of the previous timing and the current timing may be read out to the receiving side in a mixed manner, and the synchronization of the data is not guaranteed.

In order to speed up data transmission, a control flag indicating the presence or absence of subsequent data is used to start transfer even when the data length is unknown.
Although a data transfer method described in Japanese Patent Application Laid-Open No. H10-264, for example, is known, there is no guarantee as to data synchronization in an asynchronous case.

FIG. 12 shows an example in which data cannot be synchronized in an asynchronous system. For simplicity, the writing speed and the reading speed will be described as being the same.

FIG. 1A shows an example in which data is synchronized. With data A being written to addresses 1 to N of the memory, reading is performed from t _{0 to} t ₂ , and then writing of data B to addresses 1 to N is delayed from t ₁ to t ₄ after the reading. conducted, it has been made more read until t ₃ ~t _5. In this case, the read data is all data A and the read data is all data B, and the data synchronization is secured.

FIG. 1B shows an example in which data is not synchronized. In a state in which the data A is written to 1~N address of the memory, writing from t ₁ data B, reading is started from t _2. At time t ₃ when the writing of data B has been performed up to n _1, an interrupt enters the sender CPU,
Writing data B n ₁ to N is resumed at time t _5. Read during this period is terminated at time t ₄ runs without interruption. Read data in this case, up to 1 to n ₁ is new data B, up to n ₁ to N is the old data A.

[0010] FIG. (C), although the writing of the data B from the time t ₂ is performed without interruption, reads from the time t ₁ is interrupted by n ₁ address at time t _3, resumed at time t ₄ This is the case. Read data, the old data A to 1 to n _1, to n ₁ to N is the new data B.

FIG. 2D shows that writing of data B from time t ₁ is interrupted at address n ₁ at time t ₂ and resumed at time t ₅ , and reading from time t ₃ is performed at n ₄ at time t ₄ . it is a case that has been resumed at time t ₆ was interrupted by ₂ address. Read data in this case, up to 1 to n ₁ data B, n ₁ ~n to ₂ data A, to n ₂ to N becomes data B.

Thus, the transmitting CPU and the receiving CPU
When data is transmitted and received asynchronously between the transmission and reception CPUs, all data in one transmission editing operation of the transmission CPU may not be obtained by one reception editing process of the reception CPU. In this case, the received data is not the same. I haven't taken the time. As a result, one operation cycle (transmission cycle)
In a plant control system or the like in which the control calculation result at the end of
A malfunction occurs in the next control based on the received data, and in the worst case, the safety of the plant is threatened.

An object of the present invention is to provide a data transmission method for maintaining synchronization of received data in data transfer between a plurality of CPUs operating asynchronously, and to easily realize data synchronization processing only by software processing. To provide a data transmission device.

Another object of the present invention is to provide a transmission control system which enables data transfer by a memory transfer method between a plurality of controllers operating asynchronously.

[0015]

An object of the present invention described above SUMMARY OF THE INVENTION may, among a plurality of processing devices operating asynchronously from one another are connected to the transmission line (CPU), a data transmission method for transmitting and receiving data, transmission send According to one of the transmission processing in the side
An identifier indicating the simultaneity is given before and after the received data and transmitted, and the receiving side adds the identifier before and after the received data .
This is achieved by comparing identifiers and performing reception processing only when synchronization is recognized . Further, the processing device is
Writing the transmission data to the reception data storage device
When reading the received data and the received data,
The reading is performed in the same order as the dress order or in the reverse order.
Sign. Alternatively, the data transmission method of the present invention comprises
Processing devices connected to the
Each unit has its own transmission processor to send and receive data.
When performing, the transmission data by the transmission side processing device (CPU)
When the data editing process is interrupted,
Transmission processing (writing) is performed in units of fixed-length data blocks
Or the data by the receiving transmission processor
Reception-side processing device during reception processing (reading) in block units
When the received data editing process by the (CPU) is interrupted
Invalidates the received data when detecting
I do.

The data transmission device of the present invention is connected to a transmission path.
Data between multiple processing units operating asynchronously with each other.
It sends and receives data, and processes data to be sent and received.
Transmission / reception data temporarily stored in the area determined for each management device
The storage device and the knowledge that indicates synchronization with the synchronized data
The storage area of the self-processing device of the storage device is provided with an identifier.
Transmission synchronization processing means for writing to the storage device and other processing of the storage device
Before being added to data read from the storage area of the device
Having reception synchronization processing means for determining the simultaneity of the identifiers
It is characterized by comprising the processing device. The present invention
Synchronous control systems are connected to transmission lines and are asynchronous with each other.
Transfer data between multiple operating controllers
While controlling, said controller,
Control arithmetic processing means, transmission data processing means, reception data processing
Control data and the controller's transmission data and other
Transfer the received data from the printer and store it in the transfer memory.
A transmission processor, wherein the transmission data processing means
The transmission data for which the
To be transmitted to the transfer memory of another controller.
Features.

[0017]

According to the structure of the present invention, the transmitting CPU inserts, for example, the same number as an identifier at the beginning and end of each data or each data block by one editing process, and then sends the data to the network. I do. By the way,
Even if there is an interruption during the transmission editing process due to an interruption, the same identification number is assigned to the data after the resumption until the transmission editing process ends.

The receiving CPU reads the received data from the network and compares the identification numbers inserted at the beginning and end of the data or data block. If the identification numbers are the same, the receiving CPU determines that the data is synchronized. Perform data editing processing.

The synchronization process for inserting and comparing the identification numbers can be executed easily and efficiently because the length for guaranteeing the synchronization is performed in units of a predetermined data block, and the processing load on the CPU is small. .

According to the conventional asynchronous transmission, transmission on the transmission side is performed.
When the writing of communication data is interrupted, the data block
When reading is performed in units of clocks, or when receiving
When data reading is interrupted, the sending
When the recording is performed, the received data before and after the interruption
Old data is mixed. However, according to the present invention,
If there is no received data, the new and old mixed received data are discarded by simple synchronization processing by the assignment of the identifier. Therefore, the transmitting CPU and the receiving CPU operate asynchronously. Can guarantee the simultaneity of the received data .
It takes the high speed and reliability of data transmission can be both improved.

Further, a data transfer method by memory transfer is provided for a control system including a plurality of asynchronous controllers.
Since it can be adopted , high-speed operation controllability can be achieved while guaranteeing the reliability or safety of the control operation of the system.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows the configuration of a plant control system employing a memory transfer system. Network transmission path 1
Are connected to each other, and each of them operates independently and asynchronously and periodically. The controller 2 inputs process data and outputs process control data to and from the plant via a process input / output device (PI / O) 3.

Each controller 2 includes a CPU 21 for performing control arithmetic processing and transmission / reception data editing processing, a main memory 22 for storing a program used for control arithmetic of the CPU and work data, a data transmission processing and a reception processing via a network. , And these are connected by a system bus 23.

The transmission sub-processor 4 shown in FIG. 3 judges whether or not there is a transfer memory 24 for storing its own transmission data, a modem 25 for performing A / D or D / A conversion of transmission / reception data, and a token (transmission right). And a transmission LSI 26. The sub processor 4 transmits the transmission data written in its own transmission area 241 of its own transfer memory to the other controller 2 while holding the token, and also transmits the transmission data from the other controller 2 to the transfer memory 24. It is taken into the reception data area 242. The data transmission between the controllers is performed cyclically by the token passing method.

All the controllers 2 connected to the network 1 write their own transmission data to their own transmission data area of the transfer memory 24 by the transmission processor 4 and transfer the data to the other controllers 2 at regular intervals via the network 1. The data is also written in a predetermined area of the memory 24.

[0027] Figure 1 is definitive in this embodiment the controller 2
2 shows the configuration of the transmission / reception means of the data transmission device in FIG. The transfer memory 24 of the controller 2 stores received data transferred from another controller via the network 1.

The reception data of the transfer memory 24 sent from another controller is transferred to a transfer reception buffer 211 in the main memory 22 after the reception synchronization processing described later by the reception data synchronization processing means 204, and further, the reception data is edited. The data is edited into the work data area 210 by the processing means 202.

On the other hand, the transmission data of the work data area 210 for storing the calculation result by the control calculation process 201 is as follows:
After being edited by the transmission data editing processing unit 203 and transmitted to the transfer transmission buffer 212, the transmission data synchronization processing unit 205 performs transmission synchronization processing described below and stores the processed data in the transfer memory 24. The transmission data of the transfer memory 24 is transferred to a predetermined area of the transfer memory of each controller at a fixed period by token passing or the like.

FIG. 4 is a flowchart (PAD diagram) for explaining the processing operation of the controller 2. In the figure, the vertical axis indicates time elapse from top to bottom, and the horizontal axis indicates processing contents broken down from left to right.

At the beginning of the operation, the CPU 21 of the controller 2 performs a reception process S10 including a reception synchronization process S101 and a reception data editing process S102. Next, the state of the plant is fetched from the process input / output device 3 and stored in the work data area 210 by the process input process S20. The control calculation process S30 performs a control calculation using the received data and the process input value, and stores the result in the work area 210. The process output process S40 is
A part of the calculation result (control command value, etc.) is output to the plant. Transmission data editing processing S501 and transmission synchronization processing S50
The transmission process S50 consisting of 2 transmits a part of the operation result to the network as transmission data.

FIG. 5 shows a flowchart of the transmission data editing process S501 and the transmission data synchronization process S502. The transmission data editing process S501 transfers each of the predetermined transmission data in the calculation result of the work data area 210 by transferring each time the control calculation process S30 periodically executed as described above ends. The data is transferred to a predetermined address in the buffer 212.

In the transmission data synchronization process S502, when transferring the transmission data in the transfer transmission buffer 212 to the transfer memory 24, one or more of the transmission data is transferred in S5021 in units of data blocks of a preset length. Put together. It should be noted that the editing process for each data block is performed in S
501 may be performed.

Next, in S5022, the ascending order counter is incremented by one.
The data is updated, and the same count value is inserted at the beginning and end of each data block in S5023. When transmission data of the same cycle is composed of a plurality of data blocks, the same count value is assigned to each block. This count value is updated by +1 every period of the transmission process S50. Therefore, if the count values before and after the data block are the same, it can be confirmed that the data is synchronized.

A count value as an identifier is given,
The transmission data in data block units is transferred to the own transmission data area of the transfer memory 24 in S5024, and is sent out to the network when the own controller holds the token.

The CPU 21 performs a transmission synchronization process S50
During the processing of step S2, even if another high-priority interrupt processing enters and the processing is interrupted, after the operation of the transmission data editing processing S501, step S5 is executed.
02, so that the transfer buffer 21
The synchronization of the transmission data in 2 does not collapse.

FIG. 6 is a conceptual diagram illustrating a state in which the self transmission data group edited in the transfer transmission buffer 212 is subjected to the above-described transmission synchronization processing and stored in the self transmission data area of the transfer memory 24. In this example, since data synchronization is required in a plurality of data blocks, a synchronization counter 2001 is inserted at the beginning and end of all data blocks.

However, the identification counter may be added only to the data blocks requiring synchronization. Also,
The own transmission data may consist of a single data block. Note that the maximum length of a data block is determined by hardware restrictions.

FIG. 7 shows a flowchart of the reception data synchronization processing S101. When the received data stored in the transfer memory 24 is transferred to the transfer receiving buffer 211 in the storage order (address order) in S1011, the count values at the beginning and end of the data block are read and compared in S1012. If the result is a mismatch, the data in the data block is not synchronized, and the data is invalidated in S1013. On the other hand, if the count values match, the data in the data block is synchronized, so the validity processing is performed in S1014, that is, the previous and subsequent count values are removed and the original data is restored. Transfer to

FIG. 8 shows the structure of a received data group transferred from the transfer memory 24 to the receiving buffer 211 in the received data synchronization process S101.

As described above, the same identifier is added to the beginning and end of each data block of transmission data, and the receiving side checks whether the two identifiers match or not, thereby determining the simultaneity of the data. it can.

In the above example, the transmission data is edited in units of data blocks of a predetermined length, and identifiers are inserted at the beginning and end of this block. According to this, since the beginning and end of the data are determined, insertion and detection of the identifier for the synchronization processing can be efficiently performed with little overhead.

FIG. 9 shows an example of the case where it is determined that they do not match according to the present embodiment. The old data A written at times t _{1 to} t ₃ is given an identifier 100 at the beginning and end thereof, and the new data B written at times t _{5 to} t ₆ is identifier 1
01 is given. At this time, if the reception process from time t ₂ is interrupted at time t ₄ and restarted at time t ₇ , the first identifier of the received data is 100 and the last identifier is 1
01. That is, until address 0~n ₁ old data A, up to n ₁ ~N is not made of sync with the new data B. Such received data is discarded because the leading and trailing identifiers do not match, so that the adopted received data is always guaranteed to be synchronized.

FIG. 10 shows a special case in which the simultaneity of data cannot be determined even in the above embodiment. That is, the data A to which the identifier 100 is assigned is stored at the time t ₁
Was interrupted by was read to ~t _2, it is to resume reading at time t _5. It was interrupted in the t ₄ time during which the writing of the new data B starts at time t _3, are to resume writing at the time t ₆ again. In this case, the identifier of the received data coincides with 100 at both the head and the end, but since the received data of n _{1 to} n ₂ is B, synchronization is not achieved.

In the following, an embodiment will be described in which even when reading and writing cross a plurality of times, the synchronization can be accurately determined. FIG. 7B shows this reception processing, and is different from the reception processing of FIG. 7A in S1011. That is, the data received from the transfer memory 24 is read in the reverse order of the address at the time of writing.

FIG. 11 is a time chart for explaining the write / read processing operation according to this embodiment. Writing is performed in the order of addresses 0 → N, and reading is performed in the order of addresses N → 0.
Are performed in reverse order.

In this example, as in FIG. 10, the interruption time of each of the writing and reading overlaps, but since there is no reversion of both processes, there is always only one crossing point. Therefore, in the case of reading in the reverse order of the writing shown in FIG. 11, the identifier of the received data is 100 (data A) at the beginning and the identifier is 101 (data B) at the end.
Asynchrony in the received data can be accurately determined. of course,
If there is no cross between the write process and the read process, the identifiers at the beginning and end of the received data always match, so that the synchronization of the received data can be confirmed.

According to the present embodiment, the simultaneity of the received data can be guaranteed in any case where the writing process and the reading process operate asynchronously by a very simple processing method.
That is, in each case where the controller on the transmission side and the controller on the reception side are asynchronous, the transmission sub-processor performing transmission processing with the transmission CPU is asynchronous, and the transmission sub-processor performing reception processing with the reception CPU is asynchronous,
Also, in all cases, including the case where other priority processes interrupting each process overlap each other, the synchronization of the received data is accurately guaranteed. As a result, a safe control operation can be performed, and the transmission load on the main CPU of the controller is reduced, so that a high-speed control operation can be realized.

Further, in this embodiment, since the receiving controller independently executes the synchronization processing of the received data, even if a failure occurs in the transmitting controller or the network, the operation of the receiving side alone can be continued. .

In the above-described embodiment, the communication method using the memory transfer has been described, but the present invention is not limited to this. In other words, even in a communication method using packet switching, the synchronization processing of the present invention can be executed by regarding the above data block as a transmission frame, and therefore, the data transmission is performed while considering the synchronization / asynchronization of the operations of the transmitting CPU and the receiving CPU. Therefore, synchronization of transmission data can be realized by software processing using the above-described identifier.

FIG. 13 shows an example of a control operation logic generally used for the controller, and FIG. 14 is an explanatory diagram of a control system for performing control operation of the logic.

FIG. 13 shows a control calculation logic for establishing / releasing an interlock, which is frequently used in plant control and the like. ＠ signal at input of control logic 301 is OFF
At the time of (0), the signal becomes OFF (0), and the output of the FF circuit which is the output unit of the logic 301 holds the previous state. When ＠ is ON (1), the signal is in accordance with the input signal. If ＯＮ is ON (1), the output of the FF circuit is set (1).
The output of the F circuit is reset (0).

FIG. 14 shows a control operation processing 201a of the transmission controller 2a, in which an operation of the input section of the logic 301 is performed and the operation result is transmitted, and the control operation means 201b of the reception controller 2b converts the received operation result. A configuration for performing an operation of an output unit of the logic 301 is conceptually shown based on the configuration. Although the transfer memory 24 is provided for each controller,
It can also be realized by system sharing. Although the memory 24 is shown in a simplified manner in this figure, in this embodiment, it is provided for each controller as in FIG.

The logic input section 301a is operated by the transmission-side controller 2a. When the signal ＠ is 0, both the signals become 0. The operation result of the signal edited into the transmission data is stored at addresses n to n + 1 of addresses 0 to N of the transfer memory 24 (transmission data area of the controller 2a). On the other hand, the receiving controller 2b
Is output from the transfer memory 2
The data is read out from the addresses n and n + 1 of 4 and both are operated by the FF circuit which inputs 0 data, and the output becomes the same as the previous value. The result is the process output process S40
After that, the operation of the predetermined part of the plant is maintained in the previous state.

Since the controllers 2a and 2b are operating asynchronously, the transmission side writes signal data 0 to the address n of the transfer memory 24, and the address n + 1
There is a possibility that data is read from addresses n and n + 1 on the receiving side before 0 is written to the address. At this time, the address n
If 1 remains as old data at +1, the logic output unit 301b performs a reset operation, so that the output of the FF circuit is reset to 0 where the previous value must be held.

By the way, when the previous value is 1 and the predetermined operation has been interlocked, this is released, and the safety of the plant may be impaired. Moreover, even with such a simple logic, it is not easy to find the cause of the defect in the elapse of an instant repeated several tens to several hundreds of milliseconds. Furthermore, when logic becomes intricate, it becomes almost difficult with human ability.

However, according to the present embodiment, the transmission buffer 2
When transmitting the transmission data from the transfer memory 12a to the transfer memory 24a, the transmission synchronization processing means 205a adds one time to the beginning (address 0) and the end (address N) of a data block of a predetermined length (for example, addresses 1 to N). The same identifier indicating the transmission data editing process (previous 01, current 0
2) is inserted. On the other hand, on the receiving side, the transfer memory 2
4b, the reception synchronization processing means 204b
Thus, the head and tail identifiers are compared for each data block, and only when the identifiers match, the data in the block is validly processed.

Therefore, as described above, addresses n and n
If the data at address +1 is mixed with the old and new data, it becomes invalid. As a result, the controller maintains the control based on the previous data until the data synchronization is confirmed, thereby avoiding the risk of malfunction due to asynchronous data.

In an actual control system, sampling / sampling is performed with respect to the cyclic operation of the controller shown in FIG.
This problem does not occur if the transmission period is sufficiently small (for example, 1/100 or less), but in many cases, the transmission period cannot be so short, and if the transmission / reception operation of the controller is interrupted by an interrupt, This danger is extremely high.

However, even in an asynchronous system, if the data synchronous processing according to the present invention is performed, it is possible to adopt a transmission system with a light processing load such as memory transfer, whereby the control arithmetic processing can be sped up, and In addition, safety of control can be secured.

[0061]

According to the data transmission method of the present invention, even when the transmitting side and the receiving side are operating asynchronously, the received data can be transmitted by assigning identifiers to the beginning and end of the data and transmitting the data. Since synchronization can be ensured, there is an effect that the processing efficiency of data transmission is improved and high-speed transmission becomes possible.

According to the asynchronous control system of the present invention, since the memory transfer method can be used for data transmission between controllers, there is an effect that transmission / reception processing is made more efficient and control operation is performed at higher speed. Moreover, since the data synchronization is ensured, the reliability and safety of the system operation are also guaranteed.

[Brief description of the drawings]

FIG. 1 is a functional configuration diagram of a controller showing an embodiment of a data transmission system of the present invention.

FIG. 2 is a configuration diagram of an asynchronous control system to which the present invention is applied.

FIG. 3 is a configuration diagram of a transmission processor.

FIG. 4 is a flowchart showing a control operation of the controller of FIG. 1;

FIG. 5 is a flowchart illustrating a procedure of a transmission process.

FIG. 6 is an explanatory diagram showing a configuration of a data block in a transmission process.

FIG. 7 is a flowchart showing a procedure of a reception synchronization process;
(A) is the first embodiment, and (b) is the second embodiment.

FIG. 8 is an explanatory diagram showing a configuration of valid processing data in a receiving process.

FIG. 9 is an explanatory diagram in a case where asynchronous data is accurately determined according to the first embodiment of the present invention.

FIG. 10 is an explanatory diagram in a case where asynchronous data is incorrectly determined according to the first embodiment.

FIG. 11 is an explanatory diagram when accurate determination of asynchronous data is performed according to the second embodiment of the present invention.

FIG. 12 is an explanatory diagram illustrating a case where data synchronization cannot be achieved in a conventional asynchronous system.

FIG. 13 is a configuration diagram of one control logic explaining an application example of the present invention.

FIG. 14 is an explanatory diagram of an asynchronous system that performs a control operation of the control logic.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Network, 2 ... Controller, 3 ... Process input / output device, 4 ... Transmission processor, 21 ... CPU, 22 ...
Main memory, 23: System bus, 24: Transfer memory, 2
5: Modem, 201: Control operation processing means, 202: Received data editing processing means, 203: Transmission data editing processing means, 204: Received data synchronization processing means, 205: Transmission data synchronization processing means, 210: Work data area, 21
1: transfer receiving buffer, 212: transfer transmission buffer, 3
01 ... control logic.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Haruya Tobita 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Inside the Hitachi, Ltd. Omika Plant (56) References JP-A-63-276947 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 7/04 H04L 7/00

Claims (5)

(57) [Claims] In a data transmission method for transmitting and receiving data between a plurality of processing devices connected to a transmission path and operating asynchronously with each other, a transmitting side transmits and receives data before and after transmission data by one transmission process.
Transmits data with an identifier indicating timeliness, and the receiving side
Compare the identifiers given before and after the
A data transmission method characterized in that a reception process is performed only when the transmission is recognized . 2. The transmission device according to claim 1, wherein the processing device transmits the transmission data to a transmission / reception data storage device.
When writing data and reading the received data
The read address in the same or reverse order as the write address order.
Data transmission method and performing out. 3. A data transmission method for transmitting and receiving data between a plurality of processing devices connected to a transmission path and operating asynchronously with each other, wherein a transmission data editing process is interrupted by a transmission side processing device. Sometimes
When transmission processing (writing) of a predetermined length data block unit is performed by the transmission-side transmission processor or during reception processing (reading) of the data block unit by the reception-side transmission processor, reception data editing processing by the reception-side processing device is interrupted. A data transmission method for invalidating received data when detecting a case in which data is transmitted. 4. A data transmission apparatus for transmitting and receiving data between a plurality of processing apparatuses connected to a transmission path and operating asynchronously with each other, wherein data to be transmitted and received is temporarily stored in an area defined for each processing apparatus. A transmission / reception data storage device, transmission synchronization processing means for assigning an identifier indicating synchronization to synchronized data and writing the data in a storage area of its own processing device of the storage device, and another processing device of the storage device Memory of
Of the identifier given to the data read from the
A data transmission device comprising the processing device having reception synchronization processing means for determining temporality . 5. An asynchronous control system for controlling a plurality of controllers connected to a transmission line and operating asynchronously with each other while exchanging data, the controller comprising: a control operation processing unit; a transmission data processing unit; Processing means and a transmission processor for transmitting and receiving transmission data of the own controller and reception data from the other controller and storing the transmission data in a transfer memory, wherein the transmission data processing means converts synchronized transmission data into data block units of a predetermined length. Wherein the data is transmitted to the transfer memory of another controller.