JP3022906B2 - Communication method of programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication method of a programmable controller for transmitting a signal to a device to be controlled via an input / output unit.

[0002]

2. Description of the Related Art When an information signal sent from a device to be controlled via an input / output unit is received by a programmable controller, the information signal is usually sent from a central processing unit (CPU) in the programmable controller to the input / output unit. The designated address signal and read (read signal) are transmitted, and the information signal corresponding to the address signal is transmitted as a response to the programmable controller on the input / output unit side. At this time, in order to synchronize the programmable controller side and the input / output device side, the input / output device side sets a ready (READY) signal indicating whether communication is possible, in other words, sets the programmable controller side to a wait state (standby state, stop state). RE for setting to
Send the ADY signal to the programmable controller.

FIG. 3 shows a read (write) sequence and R
The relationship between the EADY signals will be described.

Here, it is assumed that a CPU capable of completing one read (write) cycle in two states T1 and T2 is used. In this figure, only the READY signal is a signal input from the input / output unit to the CPU of the programmable controller. When the CPU starts operation, RE
The ADY signal is sampled. When determining that the READY signal is in the wait state, the CPU inserts a wait state. Further, the READY signal is sampled even in this wait state,
When the CPU determines that the wait state is continued by the ADY signal, the CPU inserts the wait state again. REA
When it is determined that the DY signal is in the ready state, the CPU shifts to the T2 state in FIG. 3 and performs an end sequence.

In a programmable controller,
The parallel bus connecting the I / O units may be several tens of meters long, and the READY signal from the I / O unit may not enter the wait state before the sampling timing for determining whether to enter the wait state due to a delay in the transmission path. . For this reason, in the prior art, a wait state is forcibly created from when the CPU of the programmable controller starts access until the READY signal from the input / output unit enters the wait state, and then the READY signal is connected to the CPU. Was. This state is shown in FIG.

[0006]

Conventionally, in this type of device, the CPU of the programmable controller keeps forcibly waiting until the READY signal of the input / output unit reaches the programmable controller.
Further, since a weight instruction on the input / output unit side is added, the longer the signal transmission path between the programmable controller and the input / output unit, the longer the wait time.
For this reason, there is a problem that the overall processing response of the programmable controller is also delayed.

In view of the above, it is a first object of the present invention to provide a communication method of a programmable controller which improves processing response characteristics of a programmable controller having a long signal transmission path.

Further, some of the input / output units are broken down,
If the READY signal continues to be generated, the programmable controller continues to wait, so that the sequence control for the entire device to be restricted is interrupted, and there is a problem with the conventional device that it is not possible to perform processing such as diagnosis of the cause of a failure. .

Accordingly, a second object of the present invention is to provide a communication method of a programmable controller capable of detecting an abnormality on the input / output unit side by a READY signal and automatically canceling the wait state of the programmable controller. I do.

[0010]

In order to achieve the first object, according to the first aspect of the present invention, an information signal is transferred between a programmable controller and a device to be controlled via an input / output unit. In connection with the transfer of the information signal, the programmable controller side automatically sets a forced wait state on the programmable controller side itself until a wait instruction arrives from the input / output unit to the programmable controller. The programmable controller sets a time limit to the time during which the forced wait state is continued, measures the forced wait state of the programmable controller, and, if the timed result exceeds the time limit, sets the programmable limit. The controller releases the forced wait state. Characterized in that it.

According to a second aspect of the present invention, an information signal is transferred between a programmable controller and a device to be controlled via an input / output unit.
In connection with the transfer of the information signal, a programmable controller communication method for automatically setting a forced wait state on the programmable controller side itself until a wait instruction arrives from the input / output unit to the programmable controller, The programmable controller measures the time during which the weight instruction on the input / output unit side occurs, and is set by the weight instruction on the input / output side when the counted time exceeds a predetermined time. And releasing the programmable controller from the wait state.

[0012]

According to the first aspect of the present invention, the forced wait time is limited and the wait state of the programmable controller is released.

According to the second aspect of the present invention, the wait instruction time to the programmable controller on the input / output unit side is limited, and the wait state of the programmable controller is released.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Prior to the description of the present invention, an example of a system configuration of a programmable controller will be described with reference to FIG.

In FIG. 2, a programmable controller main body 6 (hereinafter referred to as a CPU unit) is connected to input / output units 7 and 8 by a parallel bus 9. The input / output unit 7 is an input / output unit connected when the system is installed, and is hereinafter referred to as a basic unit. The input / output unit 8 is an input / output unit added when the system is expanded, and is referred to as an additional unit.

As the basic unit 7 and the extension unit 8, the same equipment as in the prior art can be used. That is, a plurality of input / output (I / O) modules connected to the parallel bus 9 are connected to each component in the device to be controlled, and perform level conversion of signals transmitted and received between the component and the CPU unit 6. .
REA indicating whether communication is possible on the I / O module 5 side
Generate the DY signal.

In the CPU unit 6, the CPU 1, the RO,
An M (read only memory) 2, a RAM (random access memory) 3, and a wait arbitration circuit 4 according to the present invention are connected to an internal bus.

The CPU 1 controls the entire system according to a system program stored in the ROM 2.
The RAM 3 temporarily stores data used for the operation of the CPU 1. The wait arbitration circuit 4 counts the elapsed time of the wait state of the CPU 1 and releases the wait state of the CPU 1 when a predetermined time has elapsed.

FIG. 1 shows an example of the circuit configuration of the weight arbitration circuit 4. In FIG. 1, a register 50 stores a forced wait (until a READY signal arrives from the input / output side).
CPU1 must be forced to wait state)
Is stored.

The value stored in the register 50 can be updated from the CPU 1 via the data bus, that is, variably set.

The timer 52 generates a READY signal for forced wait for the time indicated by the value stored in the register 50 from the start of access by the CPU 1. The wait state termination timer 53 monitors the READY signal transmitted from the basic unit 7, and when the READY signal indicates that communication is not possible for a certain period of time (a wait instruction to the CPU 1), a wait period after a certain period has elapsed. A READY signal indicating release is generated. The above-mentioned fixed time counted by the state termination timer 53 is written into the latch 51 by the CPU 1.

The gate 54 includes the basic unit 7, the timer 5,
READY signal for instructing wait state 2 and READ for instructing wait release of timer 53 for terminating wait state
The Y signal is transferred to the CPU 1 according to a predetermined priority order.

The above-described timer circuits 60 are provided for the basic unit 7 and the extension unit 8, respectively, and are connected to the selector 55.

When one of the basic unit 7 and the extension unit 8 is selected by the CPU 1, the selector 55 transfers a READY signal from the unit or the corresponding timer circuit to the CPU 1.

The wait operation in such a circuit will be described with reference to FIGS.

(1) Initial Processing When the system is started, the CPU 1 writes a wait time value for the basic unit 7 into the register 50 and a wait time value for the extension unit 8 into the latch 51.

(2) System Operation The CPU 1 of the CPU unit 6 addresses each of the I / O modules 5 of the basic unit 7 and the expansion unit 8 and generates a read signal for reading a control signal (FIG. 3). (Corresponding to T1 in (B)). When this address signal is detected by a decode circuit or the like (not shown) in the wait arbitration circuit 4, a timer circuit corresponding to the input / output module indicated by the address signal is selected, and the read signal * R of the CPU 1 is selected.
In response to the occurrence of D, the timer 52 of FIG. 1 generates a READY signal (level off) for a forced wait instruction for a predetermined time. This signal is transferred to the CPU 1 via the gate 54.

When the CPU 1 receives this READY signal, it sets a wait state. When the level-off READY signal indicating the wait state instruction on the input / output module 5 side is generated before the timer 52 counts the predetermined time, the gate circuit 54 outputs the level-off output of the timer 52 and the level on the input / output module 5 side. The exclusive OR (exclusive OR) operation result (level off) of the OFF output is transferred to the CPU 1.

If a wait instruction READY signal is generated on the input / output module 5 side even after a certain period of time, the READY signal on the input / output module 5 side is output to the gate 5.
4, the data is transferred to the CPU 1, so that the CPU 1 continues the wait state. On the other hand, if a wait instruction READY signal is not generated on the input / output module 5 side after a certain time due to a failure on the input / output module 5 side, the timer 52 generates a READY signal for forced wait at the end of the predetermined time. Since the suspension is stopped, the forced wait state of the CPU 1 is released, and the CPU 1 starts the operation again (corresponding to the first aspect of the present invention).

On the other hand, the timer 53 for terminating the wait state also starts counting simultaneously with the activation of the timer 52. After that, if the wait instruction READY signal generated on the basic unit 7 side keeps the wait instruction (level off) state for some reason, if a certain time longer than the timer time of the timer 52 is measured, the wait state The termination timer 53 generates a level-off wait release signal and transfers it to the CPU 1. Therefore, the CPU 1 is released from the wait state, and can resume the operation (corresponding to the second aspect of the present invention).

The same applies to the case where the CPU 1 reads data from the input / output module 5 on the extension unit 8 side. However, it goes without saying that the forced wait time of the CPU 1 is different from that of the basic unit 7.

The following example can be implemented in addition to this embodiment.

1) In this embodiment, the example of the read processing is described as an example of the access of the CPU 1 to the input / output unit. However, the same wait control processing can be executed for the write processing. In this case, the activation condition of the timer 52 and the wait state termination timer 53 is when the write signal * WR is generated instead of the read signal.

2) In this embodiment, the time measured by the timer 52 and the timer 53 for terminating the wait state is set to C when the system is started.
Although the setting is made by the system program of the PU1, the set time can be changed during the system operation. In this case, a set time value is input to the CPU unit 6 from a programming device (not shown) for inputting a sequence program, and the input set time value is written into the latch 51 or the register 50 by the CPU 1 of the CPU unit.

[0036]

As described above, according to the present invention, the wait state of the programmable controller is released after a fixed time without continuing as in the prior art. Even if the error occurs, the sequence control of the programmable controller can be restarted. Also, since the forced wait time is shortened,
The processing response characteristics of the programmable controller are also improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration of a weight arbitration circuit in FIG. 2;

FIG. 2 is a block diagram showing a system configuration of a programmable controller to which the present invention is applied.

FIG. 3 is a timing chart showing operation timing of a conventional programmable controller.

FIG. 4 is a timing chart showing operation timing of a conventional programmable controller.

[Explanation of symbols]

 1 CPU 2 ROM 3 RAM 4 Wait arbitration circuit 5 I / O module 6 CPU module 7 Basic unit 8 Extension unit

Claims (2)

(57) [Claims] An information signal is transferred between a programmable controller and a device to be controlled via an input / output unit, and the input / output unit waits for the programmable controller with respect to the transfer of the information signal. The programmable controller communication method of automatically setting a forced wait state on the programmable controller side itself until the instruction arrives, wherein the programmable controller sets a time limit to a time for which the forced wait state is continued, A method for communicating with a programmable controller, comprising: counting a forced wait state of a programmable controller; and, when a result of the counting exceeds the time limit, the programmable controller cancels the forced wait state. 2. An information signal is transferred between a programmable controller and a device to be controlled via an input / output unit, and the input / output unit waits for the programmable controller in connection with the transfer of the information signal. In the programmable controller communication method of automatically setting a forced wait state on the programmable controller side itself until the instruction arrives, the programmable controller measures the time during which the input / output unit side wait instruction is generated. If the measured time exceeds a predetermined time, the wait state of the programmable controller set by the instruction of the wait on the input / output side is released.