JP3005396B2 - Bit interleaved transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit interleave transmission system, and more particularly to a bit interleave transmission system used for digital radio communication.

[0002]

2. Description of the Related Art In recent years, in digital radio communication,
A multi-level modulation scheme has been introduced for the purpose of effective use of frequency and increase of transmission capacity. However, since interference from the outside increases along with this, countermeasures are required. In particular, interference due to spurious radar waves is a serious problem because a so-called burst error occurs in which errors continue during the radar pulse width. In order to reduce this burst error, it has been conventionally known to use a bit interleave system together with an error correction system (for example, Japanese Patent Laid-Open No. 58-181348).
And JP-A-63-180222.

FIG. 4 is a block diagram showing an example of a conventional bit interleave transmission system in which a bit interleave system is used in combination with the above error correction system, wherein (A) shows a transmission unit and (B) shows a reception unit. In FIG. 1A, a digital data string of a main signal is inputted to a terminal 1 from the outside, and a digital data string of an auxiliary signal is inputted to a terminal 2.

The auxiliary signal is used, for example, for a meeting line between relay stations, for transmitting an alarm to its own station, and for transmitting a route identification code. Of these, the meeting line is randomized, but the others are transmitted as a fixed pattern.

[0005] The above two digital data strings are respectively input to the transmission rate converter 3 and multiplexed, and after being rate-converted, input to the error correction encoder 4 where the error correction syndrome is output. Bits are appended. In this ratio, s bits of syndrome are added to m bits of main signal data and n bits of auxiliary signal data. That is, one frame for error correction is K (= m +
(n + s) bits, the output data rate (clock frequency) of the transmission rate converter 3 is (m + n +
s) / (m + n) times.

In the error correction encoder 4, the data of the frame format to which the error correction syndrome s bits are calculated and added for each (m + n) bits of the output data sequence of the transmission rate converter 3 are transmitted to an interleave controller. 5, J bits are continuously written into the memory 6. This J is equal to (D × K) and is called the interleave depth.

The data written in the memory 6 is firstly read out from the first bit to the {K × (D−1) +1} bit every K bits, and then read from the second bit to the {K × th}
(D-1) +2｝ bits are read out every K bits, and the same operation is repeated to rearrange the data.
That is, interleaving is performed.

FIG. 5 schematically shows an interleaving method by writing and reading of the memory 6 described above.
In the figure, numerals indicate the input order of each bit data of the input data string of the memory 6, and here, K = 1
0, D = 10, J = 100, m = 5, n = 2, and s = 3 are shown.

At the time of writing, input data is written in numerical order from the left end to the right end of the figure and from the upper stage to the lower stage, that is, 1, 2, 3,. . , 99, 100 in that order. Here, the bits with black circles are the bits that are written first in each frame. on the other hand,
At the time of reading, data is read from left to right in the vertical direction of FIG. Therefore, reading is 1,11,2
1,. . . , 91, 2, 12,. . . , 92,
3,. . . , 99, 10, 20,. . . , 90,100
Are read out in this order.

Returning to FIG. 4A, the interleaved data string S1 is read from the memory 6 as described above. The data sequence S1 is input to the modulator 7 and modulated by a predetermined modulation method, then output from the output terminal 8 to a transmitter (not shown), and further transmitted as a radio wave via a transmission antenna (not shown). Transmitted wirelessly.

Next, the operation on the receiving side will be described. On the receiving side, a modulated wave is inputted to an input terminal 11 shown in FIG. 4B via a receiving antenna and a receiver (both not shown), and further inputted to a demodulator 12 to form a digital data stream. S2 is demodulated. This digital data string S2 is written to the memory 14 via the deinterleave controller 13.

The digital data sequence S 2 written in the memory 14 is rearranged (deinterleaved) by the deinterleave controller 13 in the original data order. FIG. 6 schematically shows a deinterleaving method by writing and reading of the memory 14. In the figure, at the time of writing, data is written from left to right in the vertical direction. That is, the interleaved digital data string S2 is written every 10 addresses in the vertical direction in FIG.

As a result, the data written in the memory 14 is in a state where the data is written in the same order as when the data is written in the memory 6 on the transmission side. Therefore, when reading the memory 14, the data is read from the left side to the right side in the horizontal direction of FIG. 6 and from the upper stage to the lower stage. The black circles in FIG. 6 are the bit data read at the beginning of each frame, and the data is returned to the original order before being interleaved again by this reading.

The digital data string deinterleaved and read from the memory 14 is supplied to an error correction decoder 15 via a deinterleave controller 13 shown in FIG. After the error is corrected, it is supplied to the reception speed converter 16. The receiving rate converter 16 separates the input data into main signal data bits and auxiliary signal bits, and converts the data rate to (m + n) / (m + n + s) times the input data. 17 and the auxiliary signal bit is output to terminal 18.

When interleaving is performed, for example, when three consecutive burst errors occur in the read data 1, 11, 21 shown in FIG. 5 due to radar interference, these data are converted into one frame by deinterleaving on the receiving side. Therefore, even if the error correction method is the simplest single correction method, it can be corrected and transmitted without error. If interleaving is not performed, three consecutive burst errors cannot be corrected by the single error correction method, and are output as errors.

As described above, in the conventional system, by using the interleave system together with the error correction system, a burst error generated by radar interference or the like can be converted into a random error and error corrected.

[0017]

However, in the above-mentioned conventional bit interleave transmission method, an auxiliary signal input from outside may or may not be used depending on the situation, and if the value is constant. Therefore, normal demodulation may be difficult. That is, when the auxiliary signal is not used or the value is constant, the auxiliary signal data string is all "0" or "1".

In this case, when the data is rearranged by the interleaving, the time slots of the auxiliary signal are transmitted continuously, and the randomness of the pattern is lost, and abnormalities appear in the modulated wave. For example, as shown in FIG. 5, when the sixth bit and the seventh bit in one frame are allocated as auxiliary signal time slots, if the value of the auxiliary signal remains “0”, 6 bits are generated by interleaving. , 16,. . . , 96,7,1
7,. . . , 97 and 20 bits “0” are continuously transmitted.

For this reason, in the above case, in the conventional method, 10
A strong pattern correlation in which 20 bits of 0 bits are continuous "0" occurs, and the modulated wave output from the output terminal 8 should originally have the spectrum shown in FIG.
As shown in FIG. 3B, an abnormal spectrum having a line spectrum is generated, and normal demodulation becomes difficult.

The present invention has been made in view of the above points, and performs an interleave such that an auxiliary signal is not continuously transmitted, so that the auxiliary signal is continuous at a fixed value.
It is an object of the present invention to provide a bit interleave transmission method capable of preventing occurrence of an abnormal spectrum of a modulated wave occurring in a signal .

[0021]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a main signal data sequence relating to main information to be transmitted on a transmitting side and whether or not the main signal data sequence is used depending on the situation.
Or when not used or when the data value is constant
A bit sequence of a data sequence forming a frame is rearranged by multiplexing at least a sequence of "0" or "1" with an auxiliary signal data sequence, and then modulated and transmitted by a modulator and received by a receiving side. The bit data position of the data sequence obtained by demodulating the modulated wave with the demodulator is rearranged in the order of the original data by an operation reverse to that on the transmission side, and then separated into the main signal data sequence and the auxiliary signal data sequence. A first memory in which writing and reading of a first data string in which at least the main signal data string and the auxiliary signal data string are multiplexed are performed;
And a first writing means for sequentially writing bit data positions of the data string of the auxiliary signal in each frame in each frame and writing the bit data positions in the first memory, and a first writing means written in the first memory. First transmitting means for sequentially reading out a data sequence in the depth direction, extracting an interleaved second data sequence and outputting the interleaved second data sequence to the modulator, provided on the transmission side, wherein the second data extracted from the demodulator is provided. A second memory in which a column is written and read, second writing means for sequentially writing the second data sequence in a depth direction of the second memory, and a second memory written in the second memory. And a second reading means for reading out the second data string in the same addressing order as the first writing means on the receiving side.

[0022]

According to the present invention, the first data string is written to the first memory with the bit data positions of the data stream of the auxiliary signal sequentially shifted, and the first read means reads data from the first memory. Since the data is converted into an interleaved second data sequence by being sequentially read in the depth direction and transmitted, the number of time slots (the number of bits) in which the auxiliary signal data sequence continues in the second data sequence is conventionally reduced. It can be significantly shortened.

[0023]

1 is a block diagram of an embodiment of the present invention. FIG. 1 (A) shows the configuration on the transmitting side, and FIG. 1 (B) shows the configuration on the wave receiving side. In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals. In FIG. 1 (A), the main signal data sequence input to terminal 1 and relating to the main information to be transmitted, and the fixed pattern or random pattern auxiliary signal data sequence input to terminal 2 are transmitted to transmission rate converter 3 respectively. It is multiplexed at a rate of m bits of the main signal data string per frame and n bits of the auxiliary signal data string, and a s bit error correction syndrome bit time slot per frame is added.

The output data sequence of the transmission rate converter 3 is input to an error correction encoder 4, where s is calculated by using a predetermined generator polynomial from m bits of the main signal data sequence and n bits of the auxiliary signal data sequence. Error syndrome bits for error correction are generated and multiplexed with m bits of the main signal data string and n bits of the auxiliary signal data string. The above operation is the same as the conventional operation.

The present embodiment is characterized in that an interleaver 20 interleaves the output data sequence (the first data sequence) of the transmission rate converter 3 with the interleaver 20. That is, the interleaver 20 includes a transmission-side write controller 21, a first memory 22, and a transmission-side read controller 23, and the transmission-side write controller 21 transmits the first data string to the memory 22. Each bit data position of the data sequence of the auxiliary signal in the frame is sequentially shifted and written, and the transmission-side readout controller 23 sequentially reads out the first data sequence from the memory 22 in the depth direction and writes the interleaved second data sequence. Take out.

The write / read control of the memory 22 by the interleaver 20 will be described in more detail with reference to FIG. In FIG. 2, K = 1 as in FIGS.
0, D = 10, J = 100, m = 5, n = 2, s = 3, in which auxiliary signal data is multiplexed on the sixth and seventh bits of each frame And A black circle indicates the first data bit in each frame.

The write controller 21 determines the write address start position of each frame of the first data string in the memory 22 by
The first data string is written into the memory 22 by shifting one bit at a time for each frame. That is, as shown schematically from the left to the right at the top of FIG.
Write the input data as it is.

In the second frame, as schematically shown in the second row of FIG. 2, the first data bit "11" of the frame is set to a value one bit larger than the conventional write start address. 2 is written in the second address position from the left in the second row, and then each data is sequentially written. The last data bit "20" of that frame is the conventional write start address of the second frame. 2 is written to the leftmost address position of the second stage.

As schematically shown in the third row of FIG. 2, the third frame is a value in which the write start address is one bit larger than the write address at that time by the write controller 21 (the conventional write start address). Therefore, the first data bit "21" of the frame is written to the third address from the left, and the data of the three frames are written.

Thereafter, the input data string is 1 in the same manner as described above.
By shifting the write start address to the right by one bit per frame, each data is written to the memory 22 as schematically shown in FIG. Therefore, in the depth direction which is the vertical direction in FIG.
The auxiliary signal data string is not aligned by 3 bits or more as in the related art.

Next, at the time of reading data from the memory 22, the read controller 23 operates in the vertical direction (depth direction) of FIG.
The data stored in the memory is sequentially read from the left to the right to form a second data string in which the data array is rearranged. That is, the first data string input in the ascending order of the numerical values in FIG. 2 is 1,20,29,38,47,
56, 65, 74, 83, 92, 2, 11,. . . , 1
00, 10, 19, 28, 37, 46, 55, 64, 7
The second data string is rearranged in the order of 3, 82, 91.

As a result, the auxiliary signal data in the second data string is continuous at a maximum of only 3 bits (ie, 87, 96, 6). The second data string S3 is supplied to the modulator 7 of FIG. 1A via the read controller 23, where it is modulated by a predetermined modulation method such as phase modulation or multilevel quadrature amplitude modulation. The signal is transmitted as a modulated wave via a transmitter and a transmission antenna (both not shown).

On the other hand, on the receiving side, a signal received via a receiving antenna and a receiver (both not shown) is
The signal is supplied to the demodulator 12 from the terminal 11 (B) and demodulated, and is converted into a data sequence S4 corresponding to the second data sequence S3. This demodulated data sequence S4 is input to the deinterleaver 30.

The deinterleaver 30 includes a receiving-side write controller 31, a second memory 32, and a receiving-side read controller 3.
The data string S4 is written into the memory 32 by the method schematically shown in FIG. 3, and then read out to obtain a data string rearranged in the original order.
In FIG. 3, black circles indicate data bits to be read first in each frame.

That is, the data string S4 is sequentially written in the memory 32 by the receiving-side write controller 31 in the vertical direction (depth direction) of FIG. Next, the reception-side read controller 33 controls the read start address to be shifted to the right by one bit each time the read address of the memory 32 is read by one frame in the same manner as the transmission-side write controller 21. The data stored in the memory 32 is read out.

In this manner, the first
The third data sequence rearranged in the same order as the data sequence of (i) is read. This third data string is supplied to the error correction decoder 15 of FIG. 1B via the read controller 33, where the error is corrected using the error correction syndrome, and then the data is transmitted to the reception-side speed converter 16. The input signals are separated into a main signal digital data sequence and an auxiliary signal digital data sequence, and are output to terminals 17 and 18.

Therefore, according to this embodiment, even when the auxiliary signal data is not used or has a fixed value,
Since the fixed value has a maximum of only three consecutive bits, no abnormality occurs in the modulation spectrum, so that the receiving side can demodulate normally.

Also in this embodiment, the burst error correction capability can maintain the same capability as the conventional system. For example, in the transmitted / received second data string, 1, 20,
When a burst error occurs in 29 consecutive 3-bit data, the data is distributed to one error in one frame by a deinterleave operation, so that even the simplest single error correction method can be corrected.

[0039]

As described above, according to the present invention,
Since the number of time slots (the number of bits) in which the auxiliary signal data sequence continues in the interleaved second data sequence to be transmitted and received is made much shorter than in the past, the auxiliary signal is not a random pattern but fixed or “0”. Even if the pattern is "1" or "1", an abnormal spectrum can be prevented from being generated in the modulated wave.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram schematically illustrating a transmitting side interleaving method of the present invention.

FIG. 3 is a diagram schematically illustrating a receiving-side deinterleaving method of the present invention.

FIG. 4 is a block diagram of an example of the related art.

FIG. 5 is a diagram schematically illustrating a conventional transmission-side interleaving method.

FIG. 6 is a diagram schematically illustrating a conventional receiving-side deinterleaving method.

FIG. 7 is a modulation spectrum diagram for explaining a conventional problem.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main signal data input terminal 2 Auxiliary signal data input terminal 4 Error correction encoder 7 Modulator 11 Modulation wave input terminal 12 Demodulator 15 Error correction decoder 20 Interleaver 21 Transmitter write controller 22 First memory 23 Transmitter Read controller 30 Deinterleaver 31 Receiver write controller 32 Second memory 33 Receiver read controller

Continuation of the front page (56) References JP-A-63-181538 (JP, A) JP-A-4-320123 (JP, A) JP-A-1-159874 (JP, A) US Patent 4559625 (US, A) The Institute of Electronics, Information and Communication Engineers, Information Network Handbook, Ohmsha, PP316-319 (58) Fields surveyed (Int. Cl. ⁷ , DB name) H03M 13/00 H04L 1/00

Claims (3)

(57) [Claims] 1. A main signal data sequence relating to main information to be transmitted on a transmitting side, and whether or not the main signal data sequence is used depending on a situation.
Or when not used or when the data value is constant
A bit sequence of a data sequence forming a frame is rearranged by multiplexing at least a sequence of "0" or "1" with an auxiliary signal data sequence, and then modulated and transmitted by a modulator and received by a receiving side. The bit data position of the data sequence obtained by demodulating the modulated wave with the demodulator is rearranged in the order of the original data by an operation reverse to that on the transmission side, and then separated into the main signal data sequence and the auxiliary signal data sequence. In the bit interleaved transmission method, a first memory in which writing and reading of a first data string in which at least the main signal data string and the auxiliary signal data string are multiplexed is performed, and the first data string is input. First writing means for sequentially shifting each bit data position of the data sequence of the auxiliary signal in each frame to write to the first memory; and a first writing means for writing to the first memory. 1 data sequence is sequentially read in the depth direction, an interleaved second data sequence is taken out, and the first data sequence is output to the modulator.
A second memory in which the second data string extracted from the demodulator is written and read, and a second data string in a depth direction of the second memory. Second writing means for sequentially writing,
A bit interleave transmission system comprising, on a receiving side, a second reading means for reading a second data string written in the second memory in the same addressing order as the first writing means. 2. Each frame of the first and second data strings includes an error correction syndrome bit generated from the main signal data string and the auxiliary signal data string in the main signal data string and the auxiliary signal data string. The main signal data sequence and the auxiliary signal data sequence of the third data sequence read from the second memory by the second reading means on the receiving side by the multiplexing configuration. 2. The bit interleave transmission method according to claim 1, further comprising an error correction decoder that corrects using bits. 3. The method according to claim 1, wherein the first writing means shifts a write address start position of each frame of the first data string in the first memory by a constant value for each frame, and shifts the first data by a predetermined value. 3. A bit interleave transmission according to claim 1, wherein said second read means reads data from said second memory in the same address order as said first write means. method.