JP2989642B2 - Video display device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a moving image display device. More specifically,
The present invention displays an object of a large size in an animated manner on a raster scan monitor by combining one or more character units each composed of a plurality of dots in a horizontal direction and a vertical direction, for example, a video game machine or a personal computer. A moving image display device.

(Prior art)

An example of this type of moving image display device is disclosed in, for example, Japanese Patent Application Laid-Open No. 62-24296, which was published on February 2, 1987. In Japanese Patent Application Laid-Open No. 62-24296, data of horizontal display size and vertical display size is stored in an attribute memory (Obje
There is an advantage that the object size can be arbitrarily changed for each object by storing it in the ct Attribute Memory (OAM).

[Problems to be solved by the invention]

However, in the technology disclosed in Japanese Patent Application Laid-Open No. 62-24296, since the number of bits of the size designation data is large, a memory having a large storage capacity must be used as the OAM or the program memory. For example, if six types of sizes are selected in the horizontal and vertical directions, the size designation data requires three bits in each of the horizontal and vertical directions, so that one object has six bits. If 128 objects can be displayed on one screen, the size specification data will be 76 per screen.
It becomes 8 bits (= 6 bits × 128). Therefore, OAM for temporarily storing one screen of object data
Storage capacity of only 76
8 bits are required. In addition, since the size specification data is written from the CPU, the amount of data of the storage system size specification data also needs to be “the number of objects × 6 bits” in advance in the program. Will be needed. If the program memory capacity is the same, the number of objects that can be displayed naturally decreases.

Therefore, a main object of the present invention is to provide a moving image display device capable of displaying objects of various sizes using a memory having a small storage capacity.

Another object of the present invention is to provide a moving image display device capable of increasing the number of displayable objects using a memory having a small storage capacity.

[Means for solving the problem]

The present invention relates to a moving image display device for displaying a large-sized object on a raster scan monitor by combining one or more characters each consisting of a plurality of dots in a horizontal direction and a vertical direction. First storage means for storing data in an associated address area in advance for each object, an object for generating object designation data for designating one or more objects to be displayed in a next vertical period of a raster scan monitor Designated data generating means, position data generating means for generating position data indicating the position on the monitor where the specified object should be displayed, size selection data generating means for selecting the object size for each object, size specification for each screen Decide the mode Designation mode data generation means for generating designation mode data to be executed, second storage means for temporarily storing object designation data and position data, position data read from the second storage means, and size from the size selection data generation means. In-range determining means for determining whether or not the object should be displayed in the next horizontal scanning period based on the selected data and a combination of the specified mode data from the specified mode data generating means, and an in-range state in the in-range determining means A moving image display device comprising: a read address creating unit that creates a read address of a first storage unit for an object determined to be located in the first storage unit and gives the read address to the first storage unit.

[Action]

One character is formed of, for example, 8 dots (pixels) in the horizontal direction and 8 dots (pixels) in the vertical direction. One object is constituted by a set or combination of one or more such characters. For example, the first storage means such as a video data memory includes:
For example, graphic data (dot data) of a character constituting each of the 128 objects is stored in advance for each object. Therefore, the object is displayed on the raster scan monitor by reading the graphic data from the first storage means.

The microprocessor (CPU), for example, in the initial state or during the vertical blanking period of the raster scan monitor,
For example, object data is set in a second storage means such as an OAM (object attribute memory). The object data includes object designation data (name data), vertical position data, horizontal position data, and object size selection data (large or small size) in addition to color palette data, horizontal and vertical flip data, priority display data, and the like. .

For example, “8 × 8”, “16 ×
Two types are specified from the object size of "16", "32x32" or "64x64". This size designation data is temporarily held in, for example, a size register. The size selection data described above is, for example, “0” or “1”,
One of the above two types of object sizes is selected by the size selection data.

The in-range determination means determines whether or not the object is in the in-range state based on the object size determined by the size designation data and the size selection data and the position data of the object on the monitor, that is, the next horizontal line. It is determined whether or not it should be displayed.

The graphic data of the object determined to be in the in-range state in both the horizontal direction and the vertical direction by the in-range determining means is read from the first storage means. That is, the read address creating means reads out the read address such that the graphic data of the in-range determined object is read from the first storage means based on, for example, the object designation data, the position data, the size designation data, and the size selection data. create.

〔The invention's effect〕

According to the present invention, a plurality of sizes are designated in the size designation data, and the size is selected by the size selection data. Can be reduced. Therefore, not only can the storage capacity of the OAM be significantly reduced, but also the storage capacity of the program memory can be reduced. For example, when a maximum of 128 objects can be displayed on one screen and there are six types of sizes that can be displayed, it is only necessary to provide 3-bit size designation data for one screen and 1-bit size selection data for each object. . Therefore, in this case, 131 bits (= 128 × 1 +
The data of 3) may be used, and the data amount may be about 1/5 (= 131/768) as compared with the technology disclosed in the above-mentioned JP-A-62-24296.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

〔Example〕

1. Overall Configuration Referring to FIG. 1, a microprocessor 10 controls the overall operation of a moving image display device such as a video processor 12 according to program data from a program data memory 14 included in a detachable memory cassette, for example. . As the microprocessor 10, for example, a 16-bit microprocessor such as an integrated circuit "RF5A22" manufactured by Ricoh Co., Ltd. is used. The video processor 12 reads the graphic data from the video data memory 16 according to the instruction from the microprocessor 10 and
Give to 18. This video data memory 16 is, for example, 64K
It is composed of a byte SRAM (Static Random Access Memory) and includes a background pattern storage area 16a and a character data storage area 16b. Thus, the background pattern storage area 1
The reason why the SRAM 6a and the character data storage area 16b are composed of one SRAM is that the operation speed is high and the size of the storage area can be arbitrarily set by a character (object) and a background pattern. Also sound circuit
20 digitally generates necessary music and sound effect data in accordance with an instruction of the microprocessor 10 and supplies the digitally generated data to the TV interface 18. The TV interface 18 converts the graphic data from the video processor 12 into RGB signals and supplies the RGB signals to the video circuit of the RGB monitor 22, and converts the sound data from the sound circuit 20 into sound signals and converts the sound data into the sound circuit of the RGB monitor 22. give. As the sound circuit 20, for example, an integrated circuit “CXD1222Q” manufactured by Sony Corporation can be used. In this manner, on the screen of the RGB monitor 22, an object such as a video game and a background pattern which change according to the progress of the program preset in the program data memory 14 are displayed.

In the embodiment of FIG. 1, the TV interface 18 converts graphic data into RGB signals. However, a TV interface for converting graphic data into a television video signal may be used. In this case, a general household TV receiver can be used as the monitor.

FIG. 2 shows the video processor 12 of the FIG. 1 embodiment in more detail. The video processor 12 is a microprocessor
This CPU includes a CPU interface 24 that includes a data latch and address decoder that latch data from
The interface 24 includes a background image CPU interface 24a and a moving image (object) CPU interface 24b. The background CPU interface 24a is connected to the background (Backgroun
d) For image, microprocessor 10 and video processor 1
The moving image CPU interface 24b transmits and receives data between the microprocessor 10 and the video processor 12 with respect to the object.

According to the program data given from the microprocessor 10 through the background image CPU interface 24a, the background image data generation circuit 26 reads out the pattern data (character code) of the background image from the background pattern storage area 16a of the video data memory 16, Based on the pattern data, the graphic data of the background image is read from the character data storage area 16b of the video data memory 16 and provided to the synthesizing circuit 28. On the other hand, the moving image data generating circuit 30 to which the present invention is directed will be described in further detail later. The graphic data of the object is read and provided to the synthesizing circuit 28.

As will be described later, when the object and the background pattern overlap, the combining circuit 28 determines a priority order indicating which of the object and the background pattern is displayed with priority. Therefore, when the priority is given to the object, the object is displayed on the screen, and the background pattern overlapping the object is not displayed.
If a priority is given to the background pattern, the background pattern is displayed on the screen, and objects overlapping the background pattern are not displayed. Thus, the graphic data synthesized by the synthesizing circuit 28 is supplied to the image signal generating circuit 32. The image signal generation circuit 32 includes a color encoder that creates an RGB signal according to a color code for each dot (pixel) output from the synthesis circuit 28. This RGB signal is provided to the monitor 22 as described above.

The timing signal generating circuit 34 receives the basic clock of 21.47727 MHz shown in FIGS. 4A and 4B, and processes this basic clock with, for example, a counter, a decoder, a logic circuit, etc. A large number of timing signals shown in FIG. 4B are generated and applied to the CPU interface 24, the background image data generation circuit 26, the synthesis circuit 28, the moving image data generation circuit 30, the image signal generation circuit 32, and the like.

More specifically, when the basic clock is divided by two, the timing signal 10 shown in FIGS. 4A and 4B is used.
M or / 10M (however, the symbol "/" means inversion in this specification) is obtained, and further dividing the frequency by 1/2 results in a timing signal 5M or / 5M.

On the screen of the RGB monitor 22 (FIG. 1), a display period of one dot (pixel) corresponds to one cycle of the signal 5M.
Therefore, the time when the count value of the signal 5M is "0-341" is the horizontal period. Count value of signal 5M in horizontal period “0”
The time of -268 "corresponds to one horizontal display period, and the time of the count value" 269-341 "corresponds to a horizontal blanking period.One horizontal period, that is, the count value of the signal 5M is" 0-34 ".
A vertical signal V (FIG. 3) is obtained for each 1 ", and this signal V is counted and becomes a vertical position during scanning, that is, a line number. One field during interlaced scanning is the fifth field.
Assuming that there are 262 horizontal lines as shown in FIG.
The timing signal FIELD is obtained during the count value "0-262" of the clock signal. The period in which the signal FIELD is at the high level corresponds to one vertical period, the count value "0-239" corresponds to the vertical display period, and The value “240-262” corresponds to the vertical blanking period.

The timing signal VBH is output as the vertical signal count value "240" as shown in FIG. 5, which indicates the start of the vertical blanking period. The timing signal VB goes high during the vertical blanking period, and the timing signal / VB goes high during the vertical display period.

The timing signal HC0 shown in FIGS. 4A and 4B is obtained by dividing the above signal 5M by 1/2, and the timing signal / HC0 is obtained as its inversion. Timing signal / HC1 is signal / H
This is a signal obtained by dividing C0 by 1/2. The timing signal IN is
As shown in FIGS. A and 4B, this is a signal indicating the in-range determination operation that is at a high level during the horizontal display period, that is, the count value “0-255” of the signal 5M.
/ IN is obtained as its inverse. Timing signal / HI is 1
The signal is output as the count value “0” of one signal 5M every horizontal period. The timing signal HBH is output as the count value "269-270" of the signal 5M as shown in FIG. 4B, which indicates the start of the horizontal blanking period. Timing signal / HBH is signal HB
It is obtained as an inversion of H, so that the signal / HBH is at a high level between the count values “271-268” of the signal 5M. Note that the timing signal / HB is at a low level during the horizontal blanking period. 4A and 4B
As shown in the figure, the signal is output as a high level during the count value “341-268” of the signal 5M, and the timing signal OAE
As shown in FIG. 4 and FIG. 4B, the count value “0−
271 ". The timing signal LBR is output as a high level during the count value" 17-272 "of the signal 5M as shown in FIGS. 4A and 4B, and the timing signal LBW is output. It is output as a high level during the count value “276−3” of the signal 5M.
/ CRES is output as a low level during the count value "3-17" of the signal 5M as shown in FIGS. 4A and 4B.

As shown in FIG. 6A, the moving image CPU interface 24b receives data from the data bus of the microprocessor 10 and includes an 8-bit OAM address register 36. This OAM
The address register 36 is provided from the microprocessor 10 to the OAM (Object Attribute Memory) included in the moving image data generation circuit 30.
y) When writing data to 38, an address is received from the microprocessor 10 and an initial address of the OAM 38 is set. This OAM 38 has a storage capacity of, for example, 34 bits × 128 and 12
The object data of each of the eight objects can be stored. Each object data is
As shown in FIG. 7, it consists of a total of 34 bits, 3-bit color palette data, 1-bit horizontal and vertical flip data, 2-bit priority display data, etc., and 9-bit object designation data (name data). , 8-bit vertical position data, 9-bit horizontal position data, and 1-bit object size selection data.

Address decoder 40 receives read / write signal R / W from microprocessor 10 and an address from the address bus, and outputs signals OAW, / ODW, PAW, SZW and ITW.
The signal OAW is given as a write signal to the OAM address register 36, and the OAM address register 36 is loaded with the initial address from the microprocessor 10 in response to the signal OAW.

OAM address circuit 42 included in video data generation circuit 30
Includes an address counter and is enabled by the signal OAW. The OAM address circuit 42 receives the initial address from the OAM address register 36, increments it at the timing of the signal / ODW, and outputs address data for sequentially specifying the address of the OAM 38 to the address selection circuit 44 (6B
Figure). This address selection circuit 44 has a vector RA
Address data from M46 is also provided. Vector ram46
Stores the address of the object determined to be in the in-range state by the in-range determination circuit 56 described later. And the address selection circuit 44 is the OAM address circuit 4
The address data from 2 or the address data from the vector RAM 46 is selected and given to the OAM 38.

The signal / ODW from the address decoder 40 or given as an enable signal of the OAM control circuit 48,
Outputs the write signal WE and data when writing the data received from the microprocessor 10 to the OAM 38,
Give to M38.

The size register 50 is a 3-bit register, and loads any one of the size data “000-101” shown in the following Table I represented by three bits of data D5-D7 from the microprocessor 10. That is, when an address, data and a write signal designating the size register 50 are given from the microprocessor 10, the signal SZW is output from the address decoder 40. In response to the signal SZW, size data is loaded into the size register 50. The size data from the size register 50 is used as a moving image data generation circuit.
It is provided to a size decoder 52 included in 30. The size decoder 52 decodes the size data and outputs signals S8, S16, S32 or S64 indicating different object sizes.
Is output.

The 2-bit interlace register 54 displays 1-bit interlace data indicating interlace or non-interlace from the microprocessor 10, and displays one dot per line or one dot per two lines during interlace. Data OBJ V SEL indicating whether to perform the operation. That is, when an address, data and a write signal designating the interlace register 54 are provided from the microprocessor 10, the signal ITW is output from the address decoder 40. In response to this signal ITW, interlace data and data OBJ V SEL are loaded into interlace register 54.

In this embodiment, up to 32 objects can be displayed on one line, so it is necessary to specify which of the 128 objects that can be displayed on one screen should be displayed on the next line. The in-range determination circuit 56 shown in FIG.
And the aforementioned vector RAM 46 is used. Therefore, the vector RAM 46 has a storage capacity of 7 bits × 32 indicating the object number.

The vector RAM address circuit 58 mainly includes a counter, and increments the address of the vector RAM 46 for each signal / INRANGE from the in-range determination circuit 56. When there is no in-range object in the horizontal line from the vector RAM address circuit 58,
A signal / NONOBJ indicating this is supplied to a buffer RAM control circuit 92 (FIG. 6C) described later. As described above, since a maximum of 32 objects can be displayed on one line, when the number of objects in the in-range state reaches "32", the signal INRANGE FULL is output from the vector RAM address circuit 58.
Is output to the in-range determination circuit 56. Accordingly, the in-range determination circuit 56 stops the subsequent in-range determination output.

When displaying an object, the size counter 60 shown in FIG. 6B outputs data SC indicating the number of the leftmost character to be displayed among a plurality of characters constituting the object. The size counter 60 receives the initial value data from the size counter control circuit 62 and increments the initial value in response to the signal / HC0 from the timing signal generation circuit 34. The result is the above data
The data SC is output as SC, and this data SC is used for calculating an address in a horizontal (H) position calculation circuit 64 described later.

The size counter control circuit 62 outputs a signal L indicating the timing at which the horizontal position data of the new object should be loaded to the H position calculation circuit 64. That is, this signal L is a timing signal for executing processing for the next object, and is given to the above-described vector RAM address circuit 58. The vector RAM address circuit 58 decrements the vector RAM address in response to the signal L. Therefore, the address of the vector RAM 46 is changed for each signal L, and unless the signal L is output, the vector
Updating of the address in the RAM address circuit 58 is stopped. In other words, in the case of a large object, OAM38
Since the address of the OAM 38 must be the same, the address of the OAM 38 is not changed by the signal L until the processing of all the characters constituting one object is completed. The signal L is obtained by delaying the signal C by one stage D-FF.

As described above, the OAM38 has horizontal (H) position data,
Vertical (V) position data, attribute data, and name data are temporarily stored. These data read from the OAM 38 are stored in the register control circuit 74.
Under the control of the 9-bit H position register 6
It is loaded into a 6, 8-bit V position register 68, an 8-bit attribute register 70, and a 9-bit name register 72. The register control circuit 74 controls the load timing of each of the registers 66, 68, 70, and 72 in response to the signal L and the signal C from the size counter control circuit 62 described above.

The H position data HP is supplied from the H position register 66 to the H position operation circuit 64. The data HP is also supplied to the size counter control circuit 62. The H-position calculation circuit 64 calculates the absolute value data HA of the horizontal (H) position of the object and supplies the calculated value to the in-range determination circuit 56 and to a buffer RAM address circuit 90 described later to be used as an address of the buffer RAM 84. You. The H position calculation circuit 64 also adds the H position and the data SC from the size counter, and supplies the result data to the size counter control circuit 62.

The V position calculation circuit 76 receives the vertical (V) position data VP from the V position register 68 and the vertical period signal V, and subtracts the V position of the object from the currently scanned horizontal line position. This subtraction result data is data indicating whether or not the object should be displayed on the next horizontal line.
The subtraction result data is supplied to the address adder control circuit 78 together with the in-range determination circuit 56.

As will be described later in detail, the in-range determination circuit 56 determines whether the object is in the next horizontal line based on the H position data and V position data thus provided, the size data SR, the interlace data IR, and the attribute data AR. Whether it should be indicated by
It is determined whether or not the vehicle is in the in-range state. The in-range determination circuit 56 performs the in-range determination 128 times in one horizontal scanning period. As described above, when the number of objects in the in-range state reaches 32, the signal INRANGE is output from the vector RAM address circuit 58. FULL is given. Therefore, after receiving signal INRANGE FULL, inrange determination circuit 56 does not output signal / INRANGE.

The address adder control circuit 78 processes the data before the addition in the address adder 80. That is, the address adder control circuit 78 outputs the data SR,
It receives the H position data and the V position data from the H position operation circuit 64 and the V position operation circuit 76 together with the data IR from the interlace register 54 and the data AR from the attribute register 70, and receives an H flip (H inversion) or V
At the time of flip (inversion), the value to be added is changed. The address adder 80 outputs the output data from the address adder control circuit 78 and the object code data from the name register 72 (the upper left character name of the character data storage area 16a of the video data memory 16 shown in FIG. 1).
That is, the address of the character data storage area 16a is created. This address is output to video data memory address circuit 82.

The buffer RAM 84 shown in FIG. 6C has a storage capacity of 9 bits × 256 and temporarily stores color pallet data, priority data, and the like. The H inversion circuit 86 connected to the data bus of the video data memory 16 receives the color data of each dot (pixel) read out from the character data storage area 16b, and receives the data AR from the attribute register 72 based on the inversion instruction. The horizontal (H) direction is reversed in dot units. Then, the color data from the H inversion circuit 86 is supplied to a color data extraction circuit 88. The color data extraction circuit 88 collects the color data input for each of the four color cells to obtain 4-bit color data per dot.
Give to. On the other hand, the color pallet data (3 bits) and the priority data (2 bits) from the attribute register 72 are also given to the buffer RAM 84.
Eventually, the buffer RAM 84 has 9 per dot as described above.
Stores bit data.

The buffer RAM address circuit 90 stores the absolute value data HA of the H address from the H position operation circuit 64 and the H position register 66
From the H position data HP. And during the display period,
The buffer RAM address circuit 90 increments the address of the buffer RAM 84 to "0-255" and supplies this address to the buffer RAM 84. Therefore, color data and the like are read from the buffer RAM 84 in dot order.
When writing data to the buffer RAM 84, the buffer RAM address circuit 90 creates a write address for the buffer RAM 84 based on the absolute value data HA. However, reading or writing of the buffer RAM 84 is controlled by the buffer RAM control circuit 92. That is, the buffer RAM control circuit 92 receives the signal / NONOBJ from the vector RAM address circuit 58 (FIG. 6B), prohibits the writing of data to the buffer RAM 84 in response to the signal / NONOBJ, When "transparent" is indicated, similarly, writing of data to the buffer RAM 84 is prohibited.

Here, each of the above-described circuits will be described in more detail with reference to FIGS.

Detailed Circuit OAM Address Circuit 42 The OAM address circuit 42 shown in FIG. 8 includes an 8-bit address counter (Hi) 94 and a 2-bit address counter (Lo) 96. Address input A2 of address counter 94
-A8 and A9 are supplied from the address latch (Lo) 36a and the address latch (Hi) 36b of the OAM address register 36, and the address input A1 of the address counter 96 is supplied from the address latch 36a. The address A1 is an address for specifying one of two words of an object, and the addresses A2-A8 are for specifying any of the 128 objects.
The data output D7 from the address latch 36b is output from the timing signal generator 34 along with the inversion of the signals / HI and / VB.
ND gate 98. Therefore, data output D7
It is applied to the reset input R of the address counter 94 via the NAND gate 98. Therefore, when the data D7 is at the low level, the address counter 94 is reset, and the address counter 94 always starts counting from "0" and is incremented. As a result, when the in-range is determined, the object that is first determined to be in the in-range state is processed as the object with the highest priority. When the data D7 is "1", the address counter 94 is not reset, and the data last inputted from the microprocessor 10 (FIG. 1) is set as it is as initial value data, and specified by the initial value data. Objects are processed with the highest priority.

The data selector 100 receiving the signal / HC0 from the timing signal generation circuit 34 uses a clock of a different frequency between the vertical blanking period and the other period for the address counter.
Give 94 selectively. That is, the output of the D-FF 102 to which the signal IN from the timing signal generation circuit 34 is input as a data input and the signal HC0 from the timing signal generation circuit 34 is input as a clock is given to the input of the AND gate 104,
The signal / VB from the timing signal generation circuit 34 is AND gate 10
4, the AND gate 104 outputs a low level during the vertical blanking period. This low level signal causes the data selector 100 to
Clock from the timing signal generation circuit 34
The clock synchronized with C0 or the access timing from the microprocessor 10, that is, the address decoder 40 (6th A
Switch between the clocks synchronized with the signal OAW from the figure). Therefore, the microprocessor 10 stores the address counter 94 in the vertical blanking period.
A clock synchronizing with the timing of accessing is provided, and in other periods, a clock synchronizing with the internal timing is applied.

The output of the above-described AND gate 104 is provided as an enable input T of the address counter 94 through the OR gate 108 together with the carry signal C from the address counter 96.

The signal VBH from the timing signal generation circuit 34 is provided as the data input of the D-FF 110, and the signal HC0 from the timing signal generation circuit 34 is provided as the clock input. The signal VBH is also output to the AND gate 1 together with the output of the D-FF110.
Given to 12. Therefore, the output of the AND gate 112 goes high at the timing of the signal HC0, and together with the signals OAW1 and OAW2 from the address decoder 40, the NOR gate 1
14 is applied to the data inputs of D-FFs 116 and 118. A signal / 10M from the timing signal generation circuit 34 is supplied as a clock of the D-FF 116, and a signal 10M from the timing signal generation circuit 34 is supplied as a clock of the D-FF 118. The output of these D-FFs 116 and 118 is NOR
Along with the output of gate 114, it is provided to the input of NOR gate 120. Therefore, when the microprocessor 10 sets the address of the OAM 38 from the NOR gate 120, a numerical value corresponding to the address is output to the data bus, and the timing signal / LD for loading this numerical data into the address counter 94 is used as an address. It is provided to a counter 94.

Address selection circuit 44, OAM control circuit 48 and OAM 38 The address selection circuit 44 shown in FIG.
Or select address A2-A8 from vector RAM 46 and
Give to AM38 Lord OAM124. That is, the signals / VB and / IN from the timing signal generation circuit 34 are supplied to the data selector 122 via the NOR gate 126, and therefore, the data selector 122 supplies the address A2− from the OAM address circuit 42 during the vertical blanking period. Give A8 to main OAM124. Similarly, the data selector 128 responds to the signal / VB from the timing signal generation circuit 34 by using the address counter (Hi) 94 and the address counter (Lo) of the OAM address circuit 42.
Addresses A0-A4 from 96 or addresses A0-A4 from vector RAM 46 are selected and provided to auxiliary OAM 130 of OAM 38.
The data selector 132 selects the address A1 from the address counter 96 of the OAM address circuit 42 or the output of the AND gate 134 in response to the signal / VB from the timing signal generation circuit 34. Signals HC0 and / IN from the timing signal generation circuit 34 are supplied to two inputs of the AND gate 134. Therefore, during the vertical blanking period, the microprocessor
Write to OAM38 using the data output from 10,
In other periods, the upper and lower object data DOH and DOL are transferred by the internal clock to the main OAM124,
Read from OAM38 and output.

The OAM 38 is divided into the main OAM 124 and the auxiliary OAM 130 because the data bus of the microprocessor 10 is 8 bits, while the object data stored in the OAM 38 is 34 bits as described above. That is, as shown in FIG. 7, the 8-bit data is stored in the main OAM 124 four times, and the remaining two bits (= 34−32) are combined into four 8-bit data, which are then stored in the auxiliary OAM 130. Remember. Therefore, the auxiliary OAM 130 stores the most significant bit of the 9-bit H position data and the 1-bit size selection data.

The OAM control circuit 48 has an 8-bit data latch 136 each.
And 138, which are used for writing object data from the microprocessor 10 to the OAM 38. That is, data D0 to D7 of the data bus are provided as inputs of the data latch 136, and an output of the data latch 136 is provided as an input of the data latch 138. As latch signals for data latches 136 and 138, signal / PAW output from address decoder 40 (FIG. 6A) and the output of NAND gate 140 are provided. NAND
Gate 140 receives address A0 from OAM address circuit 42 and signal / ODW from address decoder 40. address
A0 is inverted by an inverter 144 and provided as an input to a NAND gate 142, which further receives the signal / ODW described above. Therefore, in response to the signal / ODW, data is latched in the data latch 138 when the address A0 is at a low level, and NA is output when the address A0 is at a high level.
A write signal is applied from ND gate 142 to main OAM 124, and upper and lower object data DIH and DIL latched in data latches 136 and 138 are written to main OAM 124.

Further, since the auxiliary OAM 130 is not 16 bits, the data writing is completed by one operation. Therefore, signal / ODW is supplied as a write signal of auxiliary OAM 130, and data latch 13
The object data latched in 8 is written.

The OAM control circuit 48 has two NOR gates 146 and 148
The NOR gate 146 receives the address A9 from the OAM address circuit 42 after being inverted by the inverter 150, and outputs a signal / VB from the timing signal generation circuit 34.
Is given. The NOR gate 148 has the above address.
A9 and signal / VB are provided as is. Therefore,
During the vertical blanking period, when the address A9 is at the high level, the enable signal is assisted by the NOR gate 148.
The signal is supplied to the OAM 130, and when the signal is at a low level, the enable signal is supplied from the NOR gate 146 to the main OAM 124. And the lord
Upper object data DOH read from OAM124
Is loaded into the V position register 68, the attribute register 70, and the name register 72, and the lower-order object data DOL is loaded into the H position register 66 and the name register 72.

Also, as described above, the specific data of the object data is stored in the auxiliary OAM 130 in a group of four objects. H position register 66 at the same timing
And the attribute register 70 is loaded.

Vector RAM Address Circuit 58 and Vector RAM 46 The vector RAM address circuit 58 shown in FIG. 10 includes a 5-bit reversible counter or U / D counter 154.
The count data of the counter 154 is provided to addresses A0 to A4 of the vector RAM 46. The signal IN from the timing signal generation circuit 34 is applied to the data input of the D-FF156,
The output of -FF156 is provided to the data input of D-FF158.
The signals HC0 and 5M from the timing signal generation circuit 34 are supplied as clock inputs to the D-FFs 156 and 158.
The output of the D-FF 158 is provided together with the signal HC0 as an input of a NAND gate 160, and the output of the NAND gate 160 is provided together with the output of the NAND gate 162 as two inputs of a NOR gate 164. The signals / LB and / HC0 from the timing signal generating circuit 34 are supplied to two inputs of the NAND gate 162. Then, the output of the NOR gate 164 is the U / D counter 1 described above.
Provided as 54 count inputs or clocks.
Therefore, the clock of U / D counter 154 is determined by signal HC0 from timing signal generation circuit.

Further, a signal / LB from the timing signal generating circuit 34 is provided as an input U / D for switching up / down counting of the U / D counter 154 through the inverter 166. Therefore, when signal / LB is at a high level, U / D counter 154 serves as an up counter and signal / L
When B is at the low level, the U / D counters 154 are each configured as a down counter.

Further, the signals 5M and HC0 from the timing signal generation circuit 34 are supplied to the input of the NAND gate 168, and the output of the NAND gate 168 is the signal / INRA from the in-range determination circuit 56.
Provided to NAND gate 170 along with NGE. This signal / INR
ANGE is given to the data input of D-FF172, and the NAND
The output of the gate 168 is given as the clock of the D-FF 172. The output of the D-FF 172 is provided as one input of the data selector 174, and the signal / LB is provided as a switching input of the data selector 174. The output of NAND gate 170
It is given as the set input / S of the RS-FF176, and the reset input / R is the signal / HI from the timing signal generation circuit 34.
Is applied. The output of the RS-FF 176 becomes the input of the AND gate 178. The other input of the AND gate 178 is the signal / HB from the timing signal generation circuit 34 via the OR gate 180.
The output of H or L and D-FF182 is provided.

Therefore, during the period during which in-range detection is required, the signal / L
When B goes high, the U / D counter 154 switches to an up-count operation. Then, every time the signal / INRANGE indicating the in-range state becomes low level, the enable signal is given from the D-FF172, so that the U / D counter 154
The clock from the NOR gate 164 is counted up. U /
The count value of the D counter 154 is provided to the vector RAM 46 as a write address. When the U / D counter 154 counts up and the in-range detected object reaches “32” which can be displayed in one line, the AND gate 18
The signal INRANGE FULL is generated by 6 and D-FF188. In response to the signal INRANGE FULL, the in-range determination circuit 56 is deactivated. On the other hand, when the signal / LB becomes low level, the U / D counter 154 is switched to the down-count operation, and the down-count operation is performed every time the signal L from the size counter control circuit 62 is supplied. U / D counter 154
In order to read out an object whose count value of the in-range is detected, the vector RAM 46 is used as a read address.
Given to. Then, when all objects are read, the count value of the U / D counter 154 becomes “0”,
Since the carry signal is given to D-FF182, the U / D counter
154 is deactivated.

When the in-range determination operation is started by the in-range determination circuit 56, the signal / HI from the timing signal generation circuit 34 is given to the reset input of the U / D counter 154, and this signal / HI is used as the reset input of the RS-FF 176. Is also given. Then, if no object in the in-range state is detected thereafter, the output of the RS-FF176 remains at the low level, and this signal indicates that the D-FF190 object 1
The signal / NONOBJ is output in response to the signal HC0 from the timing signal generation circuit 34 via 92. This signal / NONOBJ is supplied to the buffer RAM control circuit 92 (FIG. 6C).

Register control circuit 74, H position calculation circuit 74, H position register 6
6, V position register 68, attribute register 70, name register 72 and H position operation circuit 76 The register control circuit 74 shown in FIG. 11 includes a NOR gate 194 and NAND gates 196 and 198. The signal C from the size counter control circuit 62 (FIG. 6B) and the signals VB and IN from the timing signal generation circuit 34 are supplied to the inputs of the NOR gate 194. The input of the NAND gate 196, together with the output of the NOR gate 194, the signal from the timing signal generation circuit 34/5
M and HC0 are supplied, and the input of the NAND gate 198 is supplied with the signal L from the size counter control circuit 62 (FIG. 6B) and the signals 5M and HC0 from the timing signal generation circuit 34.

The H position operation circuit 64 includes an 8-bit full adder 200, while the inputs A0-A7 have exclusive OR gates.
The output of 202 is provided, while the AND gate is provided as input B3-B5
The output of 204 is given. The ground potential, that is, “0” is given as the other input. H position data D0-D7 from the first H position register 66a of the H position register 66
Is provided to the input of the exclusive OR gate 202 together with the carry signal input CIN from the AND gate 206. Therefore, when carry signal input CIN is high level, data D
0-D7 is inverted by the exclusive OR gate 202 and provided as the above-mentioned one-side input A0-A7 of the full adder 200.

Note that the AND gate 206 includes the H position register 66
Data D8 from 2H position register 66a and the output of OR gate 208 are provided. When the data D8 is "1", the horizontal (H) position of the object is in the negative (minus) area as shown in FIG. 12, and when the data D8 is "0", the H position of the object is shown in FIG. As in the positive (plus) area.
That is, the actual display screen of the monitor 22 (FIG. 1)
This is the right half of the drawing from the origin (0,0) shown in FIG. 12. In this display screen, the horizontal position is "0-255", that is, "000H-0FFH". However, in this embodiment,
Even if the left edge of the object is off the display screen, it is shown in the left half of FIG. 12 even outside the display screen so that the portion of the object within the display screen appears on the screen smoothly from the left edge of the screen Such a virtual screen is assumed, and the horizontal position can be set within the range. Outside the display range, the horizontal position is represented as "256-511", that is, "100H-1FFH".
Then, during the in-range determination period, the H position data
If D8 is "0", data D0-D7 are directly
At this time, the inputs B3-B5 are fixed to a low level by a signal IN from the timing signal generation circuit 34 indicating that the in-range determination period is being performed. Therefore, the output of full adder 200 is "D0-D7 + 0"
And the data D0-D7 are output as they are. Also, H
If the position data D8 is "1", the data D0-D7 are inverted by the exclusive OR gate 202 to generate the full adder 200.
The inputs B3-B5 are fixed to a low level by the signal IN described above. Therefore, the output of the full adder 200 is "1 + / (D0-D7)".

In other cases, when the signal HC0 from the timing signal generation circuit 34 provided through the OR gate 208 is at a high level, the full adder 200 outputs “0” or “1” depending on “0” or “1” of the H position data D8. D0-D7 + 0 "or" D0-D7 +
1 "is loaded as the initial value of the size counter 60 (FIG. 6B). When the signal HC0 is at a low level, the H position data D0
−D7 is directly supplied to the inputs A0 to A7 of the full adder 200, and the data SC0 to SC2 from the size counter 60 are supplied as the inputs B3 to B5 of the full adder 200. .

The reason why the H position data is converted into its absolute value in the H position calculation circuit 64 in this manner is that the object is monitored on the monitor except for the portion protruding from the display screen of the monitor like the object shown in FIG. This is for displaying from the left end of the screen.

Note that the V position calculation circuit 76 has an 8-bit full adder 210.
On the other hand, the input A0-A7 is provided with the V position data D8-D15 from the V position register 68 reflected by the inverter 212, while the input B0-B7 is supplied with the signal VD0-V from the timing signal generation circuit 34. VD7 is applied. Then, the addition result of the full adder 210 is provided to the AND gate adder control circuit 78 and the in-range determination circuit 56 (FIG. 6B) as vertical (V) position data of the object.

Size register 50, interlace register 54, size decoder 52, and in-range determination circuit 56
(FIG. 6A) receives the signal SZW as a load signal.
1, including second and third size registers 50a, 50b and 50c, and the first, second and third size registers 50a, 50b
And 50c via the data bus to the microprocessor 10
Data D0-D7 from FIG. 1 are provided. Interlace register 54 includes first and first interlace registers 54a and 54b that receive signal IZW from address decoder 40 (FIG. 6A) as a load signal, and include first and second interlace registers 54a and 54b. Data from the microprocessor 10 (Figure 1) via the data bus
D0-D7 are provided. The first size register 50a loads the address data BASE of the object memory area, the second size register 50b loads the data SEL, and the third size register 50c loads the size data SIZE. The first interlace register 54a loads interlace data for setting whether to perform different display or the same display in an odd field and an even field, and the second interlace register 54b loads data OBJ V SEL.

The data BASE and SEL loaded into the first and second size registers 50a and 50b are, as described above, one SRA.
The address of the video data memory 16 for arbitrarily setting the background pattern storage area 16a and the character data storage area 16b of the M video data memory 16 (FIG. 1) is designated. That is, as shown in FIGS. 14 and 15, the video data memory 16 has a storage capacity of 64 Kbytes (words), and a specific 4 Kbyte area 16 A stores the data D.
Specified by the data BASE represented by 0-D2. Also, separate areas 16B1, 16B each of which is 4K bytes
2,16B3 or 16B4 is specified by data SEL represented by data D3 and D4. By appropriately combining the data BASE and SEL, the type of the object can be changed only by changing the two bits of the data SEL. That is, character data of an object required in a certain scene of the game is stored in the specific area 16A and another area 16B1-16B4.
If character data of an object required in another scene is stored in another one of the areas 16B1 to 16B4, when the object is required, two bits of the data SEL are stored. To 16B1-16B4
By simply specifying the other one, the type of object can be easily changed for each scene of the game.

Also, the 3-bit size data D5-D7 from the third size register 50c is input to the size decoder 52. The size decoder 52 decodes the size data D5-D7 together with the 1-bit size selection data SIZESEL from the first attribute register 70a (FIG. 11) included in the attribute register 70, and NOR gates 52a, 52b, 52c or 52d. Outputs a size designation signal S8, S16, S32 or S64. That is, when the size designation signal S8 is output from the NOR gate 52a, an object of horizontal × vertical = 8 × 8 dots (consisting of one unit character) is selected, and when the size designation signal S16 is output from the NOR gate 52b. Horizontal x vertical = 16 x 16 dot object (consisting of 4 unit characters) is selected, and size specification signal S32 is NOR
When output from the gate 52c, an object of horizontal x vertical = 32 x 32 dots (consisting of 16 unit characters) is selected, and when the size designation signal S64 is output from the NOR gate 52d, horizontal x vertical = 64 x 64 dots Objects (consisting of 64 unit characters) are selected.

These size designation signals S8, S16, S32 or S64 are transmitted to the size counter control circuit 62 and the address adder control circuit 78.
Are provided as signals / OBJ8, / OBJ16, / OBJ32 or / OBJ64. The size specifying signals S8 and S16 are provided to a data selector 214 included in the in-range determination circuit 56, and the size specifying signals S32 and S64 are
Given to. As one input of the data selector 218, a size designation signal S64 is further provided, and the other input of the data selector 218 is fixed at "1". To these data selectors 214, 216 and 218, the interlace data from the second interlace register 54b included in the interlace register 54 is given as a selection signal. The object size changes between interlace and non-interlace. For example, if the dot density is increased at the time of interlacing, the object size becomes smaller. Therefore, it is necessary to change the reference size for in-range determination based on the size designation signal from the size decoder 52 accordingly. In order to perform the in-range determination operation according to such a difference in size, the data selector 214
-218 is used.

The output of data selector 214 is inverted by inverter 220 and applied to one input of AND gate 224 through OR gate 222. As the other input of the OR gate 224, the output of the AND gate 226 is provided. As two inputs of the AND gate 226, an interlace designation signal from the interlace register 54 and a size designation signal S8 from the NOR gate 52a via the inverter 228 are given. And AND gate 2
The other input of 24 is the V position data from the V position calculation circuit 76
D3 is given.

The outputs of the data selectors 216 and 218 are provided as two inputs of an AND gate 230, and the remaining input of the AND gate 230 is provided with V position data D4 from the V position calculation circuit 76.
The output of the data selector 218 is supplied to the AND gate 232 together with the V position data D5 from the V position operation circuit 76.
The output of the AND gate 226 is supplied to the AND gate 234 together with the V position data D2 from the V position calculation circuit 76. The outputs of these AND gates 224, 230, 232 and 234 are
The signal is inverted together with the V position data D6 and D7 from the V position calculation circuit 76, and supplied as an input to the NAND gate 236.

The input of the NAND gate 236 is further provided with the output of the NOR gate 238. The input of the NOR gate 238 receives the inverted H position data D8 from the H position register 66 and the output of the NAND gate 240. NAND gate 240 receives as its inputs the outputs of NAND gates 241, 242 and 244, as well as the inversion of H position data D6 and D7 from H position register 66. Two inputs of the NAND gate 241 are the output of the inverter 228 receiving the size designation signal S8 and the H position data D3 from the H position register 66. The three inputs of the NAND 242 are the H position data D4 from the H position register 66 and the size designation signal. S16 and S32, and the two inputs of NAND 244 are H position data D5 from H position register 66 and size designation signal S64.

The output of the NOR gate 238 is a signal indicating whether the output is in the in-range state in the horizontal (H) direction. Further, the AND gates 224, 230, 232, and 234 are signals indicating whether or not the data D5 and D7 from the V position operation circuit 76 are in the in-range state in the vertical (V) direction.

The input of the above-described NAND gate 236 includes the above-described NOR.
In addition to the output of the gate 238 and the AND gates 224, 230, 232 and 234, the output of the D-FF 246 which receives the signal IN from the timing signal generation circuit 34 at its data input and receives the signal HC0 as its clock, and the vector RAM address circuit 58 Signal INRANGE FULL. Therefore, from the NAND gate 236, the signal IN and the signal I
When there is no NRANGE FULL, when the object to be determined is in the in-range state in both the horizontal and vertical directions, a signal / INRANGE indicating this is output.

Size counter control circuit 62 and size counter 60 The size counter control circuit 62 shown in FIG.
Object size signal / OBJ8, / from 2b, 52c or 52d
Includes a data latch 248 that receives OBJ16, / OBJ32 or / OBJ64.

The H position data D8 from the H position register 66 is ANDed.
Gates 250, 252 and 254 are applied to one input of each of the AND gates 250, 252 and 254.
D3, D4 and D5 of the absolute value data HA from the position calculation circuit 64
Are given. Outputs of the AND gates 250, 252 and 254 are provided as initial values of the size counter 60. H
When the H position data of the position register 66 is positive (plus),
The start position of the target object is the monitor 22 (Fig. 1)
, "0" is always input as the H position data D8. Therefore, AND gate 250-25
Both outputs of 4 become low level and size counter 60
Is "0". On the other hand, when the H position data of the H position register 66 is negative (minus), H
"1" is always input as the position data D8. For example, when the H position data is “−8”, its absolute value HA is “8” and is represented as binary data “1000”. Therefore, D3 of the absolute value HA becomes high level and AN3
The output from the D gate 250 also becomes high level, and "1" is set as an initial value in the size counter 60. Then, the larger the deviation in the negative direction, the larger the absolute value HA, that is, the initial value set in the size counter 60.

The signal / HC0 from the timing signal generation circuit 34 is given as a clock of the size counter 60, and therefore, the size counter 60 increments the initial value set as described above for each signal / HC0. Since the signal / IN from the timing signal generation circuit 34 is given as the reset input of the size counter 60, the size counter 60 does not count during the in-range determination period in the in-range determination circuit 56.

Then, the output data SC of the size counter 60 is given to the address adder control circuit 78 as described above,
Provided as one input of AND gates 256, 258 and 260. The other inputs of AND gates 256, 258 and 260 have signals / OBJ16, / OBJ32 and
/ OBJ64 is given. And AND gates 256,258 and
The output of 260 is the signal latched in data latch 248
Provided to NOR gate 262 along with / OBJ8. The outputs of the D-FFs 264 and 266 are further provided to the input of the NOR gate 262, the output of the AND gate 268 is provided to the input of the D-FF 264, and the timing signal generation circuit 34 is provided to the input of the D-FF 266.
, Respectively. AND gate 268
Are the data D3-D7 from the H position operation circuit 64 and the H from the H position register 66 inverted by the inverter 270.
Receives position data D8. As the clocks of the D-FFs 264 and 266, the same signal / HC0 from the timing signal generation circuit 34 as the latch signal of the data selector 248 is applied.
The output of the OR gate 262 is provided as a data input of the D-FF 272 and is also provided as a signal C to the register control circuit 74. The signal HC0 from the timing signal generation circuit 34 is supplied to the clock of the D-FF 272.

Address adder control circuit 78 The address adder control circuit 78 shown in FIG.
Object size signal / OBJ8, / from 2b, 52c or 52d
Includes D-FFs 274 that receive OBJ16 and / OBJ32. D-FFs
The signal HC0 from the timing signal generation circuit 34 is supplied to the clock 274. The signal / OBJ8 from D-FFs274 is AND
Gates 276, 278, 280, 282, 284 and 286 are provided to each input. The signal / OBJ16 from D-FFs274 is AND gate 278,28
0, 284 and 286. The signal / OBJ32 from the D-FFs 274 is provided to each input of AND gates 280 and 286. The remaining inputs of the AND gates 276, 278 and 280 include the data H-FLIP from the attribute register 70.
And the remaining inputs of the AND gates 282, 284 and 286 are the data V-
FLIP is given. Then, the attribute register 70
Is further provided as one input of each of exclusive OR gates 288, 290 and 292.
The outputs of the AND gates 276, 278, and 280 described above, together with each of the data SC0-SC2 from the size counter 60, are output by the exclusive OR gates 294, 296, and 298, respectively.
Is given to the input. The outputs of the AND gates 282, 284 and 286 are the exclusive OR gates 300, 302 and 3 respectively.
04 is given to one input. Exclusive OR gate
The other inputs of 288, 290, 292, 300, 302 and 304 receive the output of the 6-bit data selector 306.

The data selector 306 includes a timing signal generation circuit 3
4 and the data indicating the difference between the V position from the V position calculation circuit 76 and the scanning line number.
The output of D-FF308 receiving D0-D5 is provided. D-FF3
The signal / HC0 from the timing signal generation circuit 34 is given as the clock of 08, and the data D0-D4
Is supplied to one input of the data selector 306, and the D-FF 308
Are supplied to the other input of the data selector 306. The data selector 306 selectively outputs both inputs according to the data OBJ V SEL from the interlace register 54, and as described above, the exclusive OR gates 288, 29
0,292,300,302 and 304.

The address adder control circuit 78 mainly changes the address when performing the H inversion and / or the V inversion shown in FIGS. 18A to 18D. In the case of FIG. 18A,
The data H-FLIP and V-FLIP are both "0",
Inversion and V inversion are not performed. In the case shown in FIG. 18B, the data H-FLIP is "1" and the data V-FLIP is "0", so that H inversion is performed about the vertical axis 310, but V inversion is performed in a row. I can't. In the case shown in FIG. 18C, the data H-FLIP is “0” and the data V-FLIP
Is “1”, so that H inversion is not performed, but V inversion is performed about the horizontal axis 312. In the case shown in FIG. 18D, the data H-FLIP and V-FLIP are both "1", and the H inversion and the V inversion centering on the vertical axis 310 and the horizontal axis 312 are executed.

Referring back to FIG. 17, since the inversion distance changes depending on the object size, the input of the AND gates 276-286 is, as described above, the output signal / OBJ of the size decoder 52 as described above.
8, / OBJ16 and / OBJ32. When the object size is 8 × 8, the output of the AND gates 276 to 286 is low because the signal / OBJ8 is low. Therefore, in this case, the exclusive OR gate
294-298 are size data SC0-S from the size counter 60
Since C2 is output as it is as addition addresses AA4, AA5 and AA6, the address is not inverted. If the object size is 16 × 16, the signal / OBJ16 goes low and the
Only D-gates 276 and 282 are activated, and the outputs of the remaining AND gates 278, 280, 284 and 286 go low. In this case, if the data H-FLIP is "1", the size data SC0 from the size counter 60 is inverted by the exclusive OR gate 294 and output as the addition address AA4.
If the object size is 32 × 32, the signal / OBJ32 goes low, the AND gates 276, 278, 282 and 284 are activated and the outputs of the remaining AND gates 280 and 286 go low. In this case, if the data H-FLIP is “1”, the size data SC0 and SC1 from the size counter 60
Are inverted by exclusive OR gates 294 and 296 and output as addition addresses AA4 and AA5. If the object size is 64x64, the signals / OBJ8, / OBJ16 and / O
BJ32 goes high, and all AND gates 276-286 are activated. In this case, if the data H-FLIP is "1", the size data SC0-SC2 from the size counter 60 are inverted by the exclusive OR gates 294-298 and output as added addresses AA4-AA6.

In the case of V inversion, the video data memory address circuit
Inversion of the lower 3 bits of the address to 82 means inversion for each horizontal line, and inversion of the upper 3 bits means inversion for each character. Since these lower 3 bits are not related to the object size, the exclusive OR gates 288, 290 and 292 invert or do not invert the data from the data selector 306 depending on "1" or "0" of the data V-FLIP. , And outputs the lower three bits A0, A1 and A2 of the address to the video data memory address circuit 82. For the upper three bits, a condition for each size is set by the AND gates 282 to 286 in the same manner as in the case of the above-described H inversion. The output data of the data selector 306 is inverted or not inverted by the exclusive OR gates 300, 32, and 304 depending on "", and is output to the address adder 80 as upper three bits AA8, AA9, and AA10.

The AND gates 314 and 316 included in the address adder control circuit 78 output addition addresses AA12 and AA13.
It is used as data for specifying any one of the areas 16B1 to 16B4 described above with reference to FIG.

Address adder 80, video data memory address circuit 82
The address adder 80 shown in FIG. 19 includes three 4-bit full adders 80a, 80b and 80c, and the outputs of the full adders 80a-80c are supplied to the video data memory address circuit 82 as addresses A4-A15. Given. The addresses A0-A2 of the video data memory address circuit 82 are supplied with the addresses A0-A2 from the address adder control circuit 78, and the address A3 is supplied with the signal HCO from the timing signal generation circuit 34. Note that which input bit is fixed to the ground potential in each of the full adders 80a to 80c is determined by the first size register 50a (the thirteenth size register) of the size register 50.
It depends on the data BASE in the figure). Then, the addresses A0 to A15 of the video data memory 16 are designated by the video data memory address circuit 82.
Are output to the H inverting circuit 86.

H Inverting Circuit 86 and Color Data Extracting Circuit 88 The H inverting circuit 86 shown in FIG. 20 includes a data selector 318 that receives output data D0-D15 from the video data memory 16. The data selector 318 has 16 data selectors each of which selects one of the 2-bit inputs and outputs it with 1 bit. The output of the D-FF 320 is provided as a selection signal of the data selector 318. Data H-FLIP is applied to the data input of the D-FF 320, and the signal / HC0 from the timing signal generating circuit 34 is applied as a clock. The data selector 318 responds to the selection signal according to the following Table I.
Output data according to I.

In this way, the H inversion circuit 86 inverts the graphic data output from the video data memory 16 in 8-bit units according to the presence or absence of the horizontal (H) direction inversion command H-FLIP. The graphic data output from the H inversion circuit 86 is supplied to a color data extraction circuit 88.

The color data extraction circuit 88 has four first data selectors.
322, a second data selector 324, a third data selector 326, and a fourth data selector 328. Each of the data selectors 322 to 328 selects and outputs only one of the 8-bit inputs. The first data selector 322, the second data selector 324, the third data selector 326, and the fourth data selector 328 respectively receive signals HPO, 5M and HCO from the timing signal generation circuit 34 as selection signals.
Is given. The graphic data from the above-described H inversion circuit 86 is supplied to 16-bit D-FFs 330 and 332, respectively, and the output of D-FFs 332 is further supplied to D-FFs 334. The signal / HC0 from the timing signal generation circuit 34 is applied as a clock for the D-FFs 330 and 334,
The signal HC0 from the timing signal generation circuit 34 is supplied to the clock of FFs332. The signal LBR from the timing signal generation circuit 34 is further applied to the data input of D-FF336,
A signal 5M from the timing signal generation circuit 34 is given as a clock of the D-FF 336. The output of D-FF 336 is provided as the reset input of D-FFs 330 and 334 described above.

The first 16 bits of the graphic data from the H inversion circuit 86 are held in the D-FFs 332 in response to the signal HC0,
Six bits are held in the D-FFs 330 in response to the signal / HC0. At this time, the first D-FFs332
Sixteen bits are moved to D-FFs 334 in response to signal / HC0. Therefore, graphic data of a total of 32 bits becomes input data of the first data selector 322, the second data selector 324, the third data selector 326, and the fourth data selector 328 in units of 8 bits. These data selectors 322
−328 each select one bit according to Table III below:
A total of 4 bits of color cell data are output. In this way, four color cells are designated by the color data extraction circuit 88, respectively.

Buffer RAM 84 Each of the buffer RAMs 84 shown in FIG.
A first buffer RAM 84a and a second buffer RAM 84b having the same storage capacity. The buffer RAM 84 may be originally one buffer RAM, but in this embodiment, it is divided into two, and the odd dots are stored in the first buffer RAM 84a, and the even dots are stored in the second buffer RAM 84b. ing. That is, in response to the signal HPO from the timing signal generation circuit 34, data 0D0-0D3 indicating an odd dot and data 1D0 indicating an even dot are selectively output from the data selectors 322-328 of the color data extraction circuit 88. -1D3 is output, and the data 0D0-0D3 and 1D0-1D3 are provided as data inputs to the first buffer RAM 84a and the second buffer RAM 84b, respectively.

When data is read from the buffer RAM 84, the data is read at once from the first output latch 338a and the second output latch 338b, and the data is read out from the combining circuit 28 (FIG. 2).
Give to.

Buffer RAM address circuit 90 and buffer RAM control circuit
The buffer RAM address circuit 90 shown in FIG. 22 includes an 8-bit counter 340.
Given to. As the reset input of the counter 340, a signal / CRES output from the timing signal generation circuit 34 immediately before the display period is given. As the clock of the counter 340, the output of the data selector 342 is provided. A timing signal generating circuit 34 is connected to two inputs of the data selector.
, And a signal LBR from the timing signal generation circuit 34 is provided as a selection signal. Therefore, the clock of counter 340 changes between the case of writing data to buffer RAM 84 and the case of reading data. That is, at the time of writing, the counter 340 is incremented in response to the signal / 10M, and at the time of reading,
The counter 340 is incremented in response to the signal HC0. Therefore, at the time of reading, the counter 34 is set every two dots.
0 will be incremented by "1".

The signal L from the size counter 60 is supplied to the data input of the D-FF 346, and the signal HC0 from the timing signal generation circuit 34 is supplied as the clock of the D-FF 346. The output of D-FF 346 is supplied to D-FF 348 which receives signal HC0 from the same timing signal generation circuit 34 as a clock. Also, the signal from the timing signal generation circuit 34
HC0 is supplied to the input of the D-FF 350, the signal 5M from the timing signal generation circuit 34 is supplied to the clock of the D-FF 350, and also supplied as the input of the D-FF 352. D
The timing signal generator circuit 34
Is provided. D-FF348,350 and 352
Are output together with the signal LBR from the timing signal generation circuit 34 inverted by the inverter 354.
The output of the NAND gate 344 is provided as the load signal input / LD of the counter 340. Therefore, the load timing of the counter 340 depends on the signal L, that is, the object size.

The initial value of the counter 340 is a 9-bit D-FFs35 which receives the absolute value data D0 to D7 from the H position operation circuit 64 and the output of the exclusive OR gate 360 as D8.
6, ie, the output of D-FF358. As inputs to the exclusive OR gate 360, the absolute value data D8 from the H position register 66 and the carry signal H-CARRY from the H position calculation circuit 64 are given. Therefore, as the data input D8 of the D-FFs 356, the inverse of the data D8 of the H position register 66 is given when there is a carry signal. This D-
As the clock of FFs 356 and 358, NAND gate 36 receiving signal / 5M and HC0 from timing signal generation circuit 34
Two outputs are given.

The outputs D0 and D8 of the D-FFs358 are D
-FF 364 and 366 are provided as data inputs, and the clocks of these D-FFs 364 and 366 include signals / HC0, / 10M and HC0 from timing signal generation circuit 34.
The output of the ND gate 368 is provided. The output of the D-FF 364 is supplied to the color data extraction circuit 88 described above as a signal HPO,
ND gate 370. The output of the D-FF 366 passes through an inverter 372 included in the buffer RAM control circuit 92.
Provided to AND gate 372.

The buffer RAM control circuit 92 has a 7-bit full adder 376
, And data D1-D7 from the counter 340 included in the buffer RAMAND gate circuit 90 described above are provided as inputs A0-A6 of the full adder 374. The other input B of the full adder 376 is supplied with the ground potential, that is, “0”, and the carry input is supplied with the output of the AND gate 370 described above. The full adder 376 outputs the addresses OA0 to OA6 of the first and second buffer RAMs 84a and 84b of the buffer RAM 84. For example, if the initial H-first of the object is an even-numbered dot, the address OA0-OA6 is set to the counter 340.
In the case of an odd-numbered dot, the data of the counter 340 is incremented by "+1" by the full adder 376, and the data is output as addresses OA0 to OA6.

First buffer RAM 84a object 84b of buffer RAM 84
The write signals / WE0 and / WE1 in FIG. 20 are obtained from NOR gates 378 and 380.

The input of NOR gate 378 has two NAND gates 382 and 3
The output of 84 is provided, and NAND gate 382 receives the output of each of AND gate 386, inverter 388 and NAND gate 390, and signal 10M from timing signal generation circuit 34. The timing signal generator 3 is connected to the input of the NAND gate 384.
Signal 5M from 4 and the output of AND gate 392 are provided. As inputs of the AND gate 386, the signal LBW from the timing signal generation circuit 34, the signal / NONOBJ from the vector RAM address circuit 58, and the output of the NOR gate 394 are provided. NAND gate 390 receives respective inversions of outputs 1D0-1D3 from color data extraction circuit 88. The NOR gate 394 receives the output of the above-described AND gate 374 and the output of the AND gate 396. It is. OR gate 398 receives the inversion of outputs D1 and D2 of counter 340.

The input of NOR gate 380 has two NAND gates 400 and 4
02 output, the NAND gate 400 includes the AND gate 386, the exclusive NOR gate 404, and the NAND gate described above.
406 each output and timing signal generation circuit 3
Receive signal 10M from 4. Exclusive NOR Gate 4
The carry input signal of the above-mentioned full adder 376 and the output D8 of the counter 340 are given to two inputs of 04. As inputs to the NAND gate 406, respective inversions of the outputs 0D0 to 0D3 from the color data extraction circuit 88 are given. A signal 5 from the timing signal generation circuit 34 is input to the input of the NAND gate 402.
The outputs of M and AND gate 392 are provided. AND gate 39
As the input of 2, the signal / HC0 from the timing signal generation circuit 34 and the output of the D-FF408 are provided. This D-F
Signals LBR and 5M from timing signal generation circuit 34 are applied to the data input and clock of F408, respectively.

Thus, in response to the output signals / WE1 and / WE0 from the two NOR gates 378 and 380, the first buffer RA
Data is written to M84b and M84a, respectively.

Entire operation Initial state or vertical blanking period From microprocessor 10 to OAM address register 36 (6th
Set the 9-bit OAM address in (Figure A). in this case,
Address data and a write signal designating the OAM address register 36 are provided from the microprocessor 10, and as a result, the above-described signal OAW is output from the address decoder 40. At the same time, the data indicating the initial address is output from the microprocessor 10, so that the OAM
An initial address is set in the address register 36. Also, the initial address value from the OAM address register 36 and the signal OAW from the address decoder 40 are used for the OAM address circuit.
Given to 42. Since the signal OAW is used as a load signal of an internal counter (described later) after being delayed in the OAM address circuit 42, the initial address value for the OAM 38 from the microprocessor 10 is slightly delayed from the OAM address register 36. It is also set in the OAM address circuit 42.

Subsequently, the object data is written from the microprocessor 10 to the OAM 38. In this case, first, the microprocessor 10 outputs an address, data, and a write signal. Since the address selection circuit 44 (FIG. 6B) receives the aforementioned signal VB from the timing signal generation circuit 34, the address output terminal of the OAM address circuit 42 and the address input terminal of the OAM 38 are connected during the vertical blanking period. doing. In response to the address and write signals from microprocessor 10, signal / ODW is output from address decoder 40.
In response to this signal / ODW, the OAM control circuit 48 latches the data from the microprocessor 10, and this latched data is supplied to the data input DI of the OAM 38, and the write / enable signal WE / CE is supplied to the OAM 38. Given. Therefore, the OAM 38 has a microprocessor 10 that has passed through the OAM control circuit 48 to the address specified by the OAM address circuit 42.
Is written. Then OA
Since the M address circuit 42 sequentially increments the address as described above, the object data is written to the sequential address of the OAM 38.

In addition, the size register 50
Load the size data into (Fig. 6A). In this case, address data and a write signal designating the size register 50 are provided from the microprocessor 10, and as a result, the above-described signal SZW is output from the address decoder 40. At the same time, since the size data as previously shown in Table I is output from the microprocessor 10, the size data is set in the size register 50 in response to the signal SZW.

Then, 2-bit interlace data is loaded from the microprocessor 10 into the interlace register 54 (FIG. 6A). In this case, address data and a write signal designating interlace register 54 are supplied from microprocessor 10, and as a result, signal IZW described above is output from address decoder 40. At the same time, since the interlace data and OBJ V SELECT are output from the microprocessor 10, the interlace register 54 is output in response to the signal IZW.
These data are set.

Horizontal Scan Period I In this horizontal scan period I, the in-range determination circuit 56
, The OAM address of the object in the in-range state is written to the vector RAM 46.

That is, the vector RAM address circuit 5 responds to the signal HI from the timing signal generation circuit 34 immediately before the start of horizontal scanning.
8 (FIG. 6B) is reset and the vector RAM address is set to "0". Immediately before the start of horizontal scanning, the object order data loaded in the OAM address register 36 is used to reset the counter reset NAND of the OAM address circuit 42.
Gate 96 (FIG. 7). When the object rank data is "0", the address counter 94 (FIG. 8) of the OAM address circuit 42 is reset, and therefore, the OA
The M address is set to “0”. When the object rank data is “1”, the address counter of the OAM address circuit 42 is not reset, and the last loaded data is held as the initial value of the address counter 94. When performing the in-range determination, the monitor 22 (FIG. 1) preferentially prioritizes an object determined to be in the in-range state later than an object determined to be in the in-range state.
Therefore, the initial value of the OAM address at the time of the in-range determination operation is changed by such a method, whereby the priority of the object can be changed.

More specifically, the address selection circuit 44 (6B
In the figure, the address output terminal of the OAM address circuit 42 and the address input terminal of the OAM 38 are connected by the signal IN from the timing signal generation circuit 34 during the in-range detection in the in-range determination circuit 56. OAM control circuit 4
8 always supplies an enable signal to the OAM 38 except during the vertical blanking period. Therefore, the OAM data is read from the OAM 38 according to the address data from the OAM address circuit 42 and the enable signal from the OAM control circuit 48. this
Of the output data from the OAM 38, the H position data is in the H position register 66, the V position data is in the V position register 68, the attribute data is in the attribute register 70, and the name data (object designation code) is the name register.
72 are respectively loaded by a load signal from the register control circuit 74.

The H position data from the H position register 66 is output to the H position calculation circuit 64. As described above with reference to FIG. 12, when the most significant bit of the H position data is "0", Is "0-255", the raw data is supplied to the in-range determination circuit 56. Conversely, when the most significant bit of the H position data is "1", that is, when the H position is "-256"
If the value is "-1", "2's complement" (absolute value) at the H position is calculated in the H position calculation circuit 64, and the result data HA is supplied to the in-range determination circuit 56.

The V position calculation circuit 76 receives the signal V from the timing signal generation circuit 34, subtracts the V position data VP from the V position register 68 from the vertical position data of the line indicated by the signal V, and in-ranges the resulting data. This is given to the judgment circuit 56.

The in-range determination circuit 56 includes H position data corrected as needed from the H position calculation circuit 64, subtraction result data from the V position calculation circuit 76, size selection data from the attribute register 70, and data from the size register 50. Size data and data OBJ V SE from interlace register 54
Based on L, it is determined whether the object to be determined at that time is in the in-range state. And if the object is in the in-range state, the signal
/ INRANGE is output to the vector RAM address circuit 58.

The vector RAM address circuit 58 includes an in-range determination circuit 5
In response to the signal / INRANGE from 6, a write signal is given to the vector RAM 46. The vector RAM 46 receives the write signal and the address data from the vector RAM address circuit 58 and the data (OAM address) from the address selection circuit 44 and stores the data DI. Then, after outputting the write signal to the vector RAM 46, the vector RAM address circuit 58 increments the address of the vector RAM 46.

In response to the signal HC0 from the timing signal generation circuit 34, the OAM address value of the OAM address circuit 42 is incremented by "+1".
In 46, the in-range judgment of the next object is performed.
The object data of the in-range object
The address of the OAM 38 is stored in the vector RAM 46.

As described above, the OAM address circuit 42 is reset by the object order data of the OAM address register 36, but when the OAM address circuit 42 is reset,
If the AM address changes from "0" to "127" and the OAM address circuit 42 is not reset, the OAM address is incremented by "+1" from the "last set address", and "127" is followed by "1". 0 ", and changes to" last set address -1 ".

The above-described in-range determination operation is performed 128 times during scanning of one line on the monitor 22 (FIG. 1). The number of determined objects is "3
When the signal reaches 2 ", the signal INRANGE FILL is output from the vector RAM address circuit 58 to the in-range determination circuit 56, and the output of the signal / INRANGE from the in-range determination circuit 56 is accordingly inhibited.

Horizontal Blanking Period During the horizontal blanking period, the graphic data of the object in the in-range state is stored in the buffer RAM 84.

In the H blanking period, a signal HB is supplied from the timing signal generation circuit 34 to the vector RAM address circuit 58, and the U / D counter 154 (FIG. 10) in the vector RAM address circuit 58 is counted up by the signal HB. Mode is switched to the down count mode. further,
In response to the signal HBH from the timing signal generation circuit 34,
The address of the vector RAM address circuit 58 is decremented, and the vector RAM address storing the OAM address of the object data set last is the vector R
Given to AM46.

Upon receiving the address from the vector RAM address circuit 58, the vector RAM 46 outputs the OAM address. The address selection circuit 44 supplies the address from the vector RAM 46 to the address input terminal of the OAM 38 in response to the signals IN and VB from the timing signal generation circuit 34.

Of the object data output from the OAM 38, the H position data to the H position register 66, the V position data to the V position register 68, the attribute data to the attribute register 70, the name data to the name register 72, and the register control. Loaded in response to a load signal from circuit 74.

The H position data latched in the H position register 66 is applied to the H position operation circuit 64. If the most significant bit of the H position is “0”, the H position calculation circuit 64 sets the size counter 60 to “0”.
If the most significant bit at the H position is "1", D3-D5 of the complement (absolute value) data of "2" at the H position is applied to the size counter 60. Thus, the size counter 60
Indicates the number of character units from the left in the horizontal direction of the object (1 character unit is 8 bits) to be displayed on the screen of the monitor 22. If the H position of the object is, for example, "504" (1F8H = -8), the complement of "2" is "8", and therefore D3-D5 of the two's complement data is "1". This means that the object is displayed on the screen of the monitor 22 from the first character unit constituting the object. However, since the object starts from the 0th character,
The first character is the second character from the left.

Immediately after the start of the horizontal blanking period, the size counter control circuit 62 receives the signal HBH from the timing signal generation circuit 34 and supplies the load signal / LD to the size counter 60.

In response to the load signal / LD from the size counter control circuit 62, the size counter 60 is preset with “0” when the H position of the object is within the range of “0-255”, and the H position is set to “0”. When it is within the range of 256-511 ", the data from the H position calculation circuit 64 is preset.

The data of the size counter 60 is output to the H position calculation circuit 64. The H position calculation circuit 64 is a timing signal generation circuit 34
Is changed from the mode for calculating the complement of "2" to the adder mode in response to the signals HCO and IN from. In the adder mode, the H position data and the data from the size counter 60 are added. The addition result data is H position data in consideration of the object size in the horizontal direction.
This is corrected H position data when dot character data is written to the buffer RAM 84 the number of times corresponding to the number of characters in the horizontal direction. This addition result data is provided to the buffer RAM address circuit 90 as address data. At the same time, the data from the size counter 60 is provided to the address adder control circuit 78 and used to calculate the address of the object to be displayed, that is, the character.

The V position calculation circuit 76 subtracts the V position data of the object latched in the V position register 68 from the data of the line number indicated by the signal V from the timing signal generation circuit 34, and outputs the result data to the address adder control circuit.
Give to 78.

The address adder control circuit 78 includes an interlace register
The subtraction result data D0-D5 or D0-D4 from the V position operation circuit 76 according to "1" or "0" of the 54 data OBJ V SEL.
+ Select one of the signals FIELD from the timing signal generation circuit 34.

If the latter is selected in the address adder control circuit 78, a graphic of one dot in the vertical direction is displayed on one line on the display of the monitor 22 at the time of interlace, and if the former is selected, the graphic of two dots is displayed in the vertical direction Displays a one-dot graphic.

The size data loaded in the size register 50 is decoded by the size decoder 52, and as a result, the signal / O
BJ8, / OBJ16, / OBJ32 or / OBJ64 are obtained.

The data selected in the address adder control circuit 78 as described above is the data V-FLIP in the attribute register 70 and the signal / OBJ8, By / OBJ16, / OBJ32 or / OBJ64, only the necessary bits in consideration of the object size are inverted or not inverted, so that A0-A2, AA4-AA6, AA8-AA10 and AA12 and AA13 (FIG. 17) ) Is output to the address adder 80. At the same time, the address adder control circuit 78 receives the data from the size counter 60, and outputs the object by the data H-FLIP in the attribute register 70 and the signal / OBJ8, / OBJ16, / OBJ32 or / OBJ64 from the in-range determination circuit 56. Only the necessary bits in consideration of the size are inverted or not inverted, and the result is given to the address adder 80. Further, the address adder control circuit 78 receives the most significant bit of the name register 72 and the object name bank data in the size register 50, performs address conversion, and provides the conversion result to the address adder 80.

The address adder 80 adds the lower bits of the H operation data and V operation data after the H inversion and / or V inversion from the address adder control circuit 78 and the name data from the name register 72, and simultaneously performs the H operation. The upper bits of the data and the V operation data are added to the object base data BASE from the size register 50, and the result of each addition is given to the video data memory address circuit 82 as an address.

The video data memory address circuit 80 receives a signal OAE for permitting address output to the video data memory 16 from the timing signal generation circuit 34, and outputs an address from the address adder 80 to the video data memory 16.

The video data memory 16 receives the address from the video data memory address circuit 82 and outputs graphic data to the H inversion circuit 86.

The H inverting circuit 86 inverts the 8-dot graphic data according to “0” or “1” of the data H-FLIP in the attribute register 70 or supplies it to the color data extracting circuit 88 without inverting.

On the other hand, in the buffer RAM address circuit 90, the address from the H position calculation circuit 64 is preset in the internal counter 340 (FIG. 22), and the data from the counter 340 is supplied to the buffer RAM 84. The most significant bit of the H position data in the H position register 66 and the carry signal from the H position calculation circuit 64 (carry when calculating the buffer RAM address) are exclusive in the buffer RAM control circuit 92. O
The processing is performed by the R gate 404 (FIG. 22), and the result is simultaneously preset in the counter 340. When the carry signal is "0" and the H position is in the range of "0-255", and when the carry signal is "1" and the H position is in the range of "256-511", The output of the exclusive OR gate 404 is "0". This data is used to create a write signal to the buffer RAM 84 in the buffer RAM control circuit 92.

In the buffer RAM control circuit 92, the exclusive O
When the output of the R gate 404 is received and the color of the dot indicated by the color data extraction circuit 88 is not a code indicating transparency, a write signal / WE0 or / WE1 is supplied to the buffer RAM.

When the object starts with an odd dot,
The full adder 396 (FIG. 22) in the buffer RAM control circuit 92 increments the buffer RAM address by "+1" and gives the result to the buffer RAM 84.

The buffer RAM 84 receives the address from the buffer RAM address circuit 90, the color data from the color data extraction circuit 88, the color data and priority data from the attribute register 70, and the write signal and address from the buffer RAM control circuit 92. , And 9-bit color and priority data.

In the above embodiment, two 128 × 9 bit RAMs are used as the buffer RAM 84. One is used to store data for odd dots, and the other is used to store data for even dots. Therefore, in this embodiment, two types of addresses are necessary, but if the response speed of the first and second buffer RAMs 84a and 84b (FIG. 21) is increased, only one type of address may be used. In this case, the address from the buffer RAM control circuit 92 becomes unnecessary.

When the object size is 8 × 8 or more, that is, when the object is composed of two or more characters, after the size counter 60 is up-counted, the above-described operation is performed by the number of times corresponding to the number of characters. Will repeat.

The size counter control circuit 62 uses the signals / OBJ8, / OBJ16, / OBJ32 or / OBJ64 from the in-range determination circuit 56 and the count value from the size counter 60 to transfer each object data to the buffer RAM 84. Determine the end timing. Until all of a plurality of character data constituting one object are written in the buffer RAM 84, the count down (decrement) of the address in the vector RAM address circuit 58 is prohibited. Then, at the timing when all the character data is written, the address of the vector RAM address circuit 58 is decremented by "-1". In this way, the vector RAM address circuit 58 gives the address of the vector RAM in which the OAM address of the next object is stored to the vector RAM 46. Data from vector RAM46 is OAM38
The H position data from the OAM 38 is supplied to the H position calculation circuit 64 via the H position register 66. The horizontal display start position data of the next object is supplied again from the H position calculation circuit 64 to the size counter 60, a load signal is supplied from the size counter control circuit 62 to the size counter 60, and the size counter 60 is preset.

Thereafter, similarly, the object data of the subsequent objects are sequentially stored in the buffer RAM 84.

Horizontal scanning period II During this period, the data in the buffer RAM 84 is converted into an image signal and output to the RGB monitor 22 (FIG. 1).

At the end of the horizontal blanking period, the buffer RAM address circuit 90 outputs the signal / CRE from the timing signal generation circuit 34.
Upon receiving S, the internal counter 340 is reset.

When the horizontal scanning period starts, the buffer RAM 84 becomes the buffer RAM.
Upon receiving the address from the address circuit 90, it outputs graphic data to the synthesis circuit. The graphic data of the object combined with the background pattern by the combining circuit 28 is converted into an image signal by the image signal generating circuit 30. Therefore, on the monitor 22, a composite image of the object and the background pattern is displayed.

Then, in the buffer RAM address circuit 90, the counter 340 is counted up by the signal HC0 from the timing signal generation circuit 34, and the address is sequentially incremented. The buffer RAM 84 is a buffer RAM address circuit 90.
, And sequentially outputs graphic data to the synthesis circuit 28.

At the same time that the data of the line currently being scanned is output from the buffer RAM 84, the operation described in [Horizontal scanning period I] is executed again to create the data of the next line.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing the video processor of the embodiment shown in FIG. FIG. 3 is a block diagram showing a timing signal generation circuit. FIGS. 4A and 4B are timing diagrams showing timing signals in the horizontal direction. FIG. 5 is a timing chart showing timing signals in the vertical direction. 6A, 6B and 6C are block diagrams showing the moving picture data generation circuit shown in FIG. FIG. 7 is an illustrative view showing one example of object data; FIG. 8 is a block diagram showing the OAM address circuit in detail. FIG. 9 is a block diagram showing the address selection circuit, OAM control circuit and OAM in detail. FIG. 10 is a block diagram showing the vector RAM address circuit and the vector RAM in detail. FIG. 11 is a block diagram showing in detail a register control circuit, an H position register, a V position register, an attribute register, a name register, an H position operation circuit, and a V position operation circuit. FIG. 12 is an illustrative view showing a horizontal (H) position and a vertical (V) position related to the monitor screen. FIG. 13 is a block diagram showing in detail a size register, an interlace register, a size decoder, and an in-range determination circuit. FIG. 14 and FIG. 15 are illustrative views showing an example of a memory format of a video decoder memory. FIG. 16 is a block diagram showing the size counter control circuit in detail. FIG. 17 is a block diagram showing the address adder control circuit in detail. 18A to 18D are illustrative views showing states of an H flip and a V flip. FIG. 19 is a block diagram showing the address adder, the video data memory address circuit and the video data memory in detail. FIG. 20 is a block diagram showing the H inversion circuit and the color data extraction circuit in detail. FIG. 21 is a block diagram showing the buffer RAM in detail. FIG. 22 is a block diagram showing a buffer RAM address circuit and a buffer RAM control circuit in detail. In the figure, 10 is a microprocessor, 12 is a video processor, 14 is a program memory, 16 is a video data memory,
16b is a character data storage area, 24b is a video CPU interface, 28 is a synthesis circuit, 30 is a video data generation circuit,
34 is a timing signal generation circuit, 36 is an OAM address register, 38 is an OAM, 42 is an OAM address circuit, 44 is an address selection circuit, 46 is a vector RAM, 48 is an OAM control circuit, 50 is a size register, 52 is a size decoder, 54 is an interlace register, 56 is an in-range determination circuit, 58 is a vector RAM address circuit, 60 is a size counter, 62 is a size counter control circuit, 64 is an H position operation circuit, 66 is an H position register, 68
Is a V position register, 70 is an attribute register, 72 is a name register, 74 is a register control circuit, 76 is a V position operation circuit, 78 is an address adder control circuit, 80 is an address adder, 82 is a bit data memory address circuit, 84 is a buffer RAM, 86 is an H inversion circuit, 88 is a color data extraction circuit, 90 is a buffer RAM address circuit, and 92 is a buffer RAM control circuit.

Continuing on the front page (72) Inventor Masahiro Otake, Nintendo Co., Ltd., 60, Fukuinakami-Takamatsucho, Higashiyama-ku, Kyoto, Kyoto, Japan ) References JP-A-63-113784 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G09G 5/36-5/38 G09G 5/08

Claims (2)

(57) [Claims] 1. A moving image display device for displaying a large-sized object on a raster scan monitor by combining one or more characters each consisting of a plurality of dots in the horizontal and vertical directions, the moving image display device comprising: First storage means for storing graphic data for each object in an associated address area in advance; generating object designation data for designating one or more objects to be displayed in a next vertical period of the raster scan monitor; Object specifying data generating means for generating, position data generating means for generating position data representing a position on the monitor at which a specified object is to be displayed, size selecting data generating means for selecting an object size for each object, and for each screen To size finger Designation mode data generation means for generating designation mode data for determining a mode; second storage means for temporarily storing the object designation data and the position data; position data and the size read from the second storage means In-range determining means for determining whether or not to display the object in the next horizontal scanning period based on the size selection data from the selection data generating means and the combination of the specified mode data from the specified mode data generating means; and A moving image display device, comprising: a read address creation unit that creates a read address of the first storage unit for an object determined to be in an in-range state by the inrange determination unit and provides the read address to the first storage unit. 2. The moving image display device according to claim 1, further comprising means for temporarily storing said selection mode data.