JP2978706B2 - Control storage caching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control storage caching, and more particularly, to a control storage caching method for controlling reading of a microprogram.

[0002]

2. Description of the Related Art Conventionally, a microprogram for controlling an arithmetic processing unit has a small capacity of an RO built in an LSI.
M or RAM, etc.
It is stored in an external ROM or RAM, or stored in a main storage device or the like.

In order to store a large-capacity microprogram in a ROM or RAM outside the LSI, LSI input / output pins for interfacing with the ROM or RAM are required, and the number of LSI input / output pins becomes insufficient. For this reason, the shortage of the LSI input / output pins is often solved by storing the microprogram on the main storage device and reading the microprogram using a normal main storage device access mechanism.

However, the read time of the microprogram directly affects the performance of the arithmetic processing unit. Therefore, when the microprogram is stored in the main storage device, the microprogram and the main processor must be connected to each other to compensate for the delay in the read time. A cache memory is required between the storage devices. In this case, the conventional control storage caching method determines the compartment to be evicted in the event of a cache miss, based on the last access time,
It has an LRU memory.

[0005]

In the above-described conventional control storage caching method, in a multiprocessor system having a relatively large number of arithmetic processing units, the hit rate of the cache memory is reduced. As a result, there has been a problem in that the reading time of the microprogram becomes longer and the system performance is reduced.

[0006]

According to the method of the present invention, there is provided a set associative cache memory comprising a plurality of compartments between an arithmetic processing unit and a main storage device, and stored in the main storage device. and the control store caching scheme microprograms for controlling the arithmetic processing apparatus in the information processing apparatus which operates caching in the cache memory, said cache
Only to specific cache memory addresses in
Microprograms are stored so that microprograms can be stored.
The address in main memory where the RAM is stored is a specific address
Limited to the range, the micro-program a flag corresponding to the block of a particular cache memory address range of the cache memory indicating whether read into the cache memory, the flag when the swap event block has occurred Indicates that a microprogram is stored, a block in another compartment is swept out without sweeping out that block.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1 showing a first embodiment of the present invention, the present embodiment includes an arithmetic processing unit 1, a main storage unit 2, a cache memory 3, an address register 31, address arrays 320 to 32n, data Arrays 330 to 33n, valid flag memories 340 to 34n, address comparison circuit 350
To 35n, microprogram storage flags 360 to 36
n, LRU memory 37, compartment selection circuit 38
It is composed of

When the arithmetic processing unit 1 issues a microprogram read request, the request address is stored in the address register 31. A part of the bit group of the address register 31 corresponds to the address arrays 320 to 3.
2n addresses are indexed. As an example, a case of a 4-compartment cache memory 3 having a storage space of 32 bits addressing (4 gigabytes), a block size of 64 bytes, and a cache memory capacity of 4 megabytes will be described. Each compartment of the address arrays 320 to 323 is composed of 16 kilowords × 12 bits, and stores the upper 12 bits of the 32 bits of the address. The middle 14 bits of the 32 bits of the address indicate the storage address of the address array, and the lower 6 bits indicate 1 byte of the block size of 64 bytes.

The address information read from the address arrays 320 to 32n is applied to address comparison circuits 350 to 35n.
Is compared with the upper bit group of the address register 31,
The result matches, and the corresponding valid flag memory 3
If the values of 40 to 34n are valid, a cache hit is determined and the microprogram is read from the corresponding data array 330 to 33n. According to the example above,
The upper 12 bits of the address stored in the address arrays 320 to 323 and the corresponding 12 bits of the address register 31 are converted into four address comparison circuits 350 to 35.
3, the comparison results are identical, and the compartments in which the validity flag memories 340 to 343 indicate the validity of the block are determined to be cache hits.

If a cache hit is not determined, a microprogram read request is issued to the main storage device 2. The microprogram read from the main storage device 2 is stored in one compartment of the data arrays 330 to 33n selected by the compartment selection circuit 38. At the same time, address array 3
A part of the microprogram is stored in 20 to 32n, the corresponding bits of the valid flags 340 to 34n are made valid, and the corresponding bits of the microprogram storage flags 360 to 36n are also set.

When the arithmetic processing unit 1 issues a request other than the microprogram read request, the request address is stored in the address register 31. A part of the bit group of the address register 31 becomes an address of the address arrays 320 to 32n and is indexed.
The address information read from the address arrays 320 to 32n is compared with a part of the bit group of the address register 31 by the address comparing circuits 350 to 35n, and as a result,
If the values of the corresponding valid flag memories 340 to 34n are valid, it is determined that a cache hit has occurred, and data is read from or written to the corresponding data arrays 330 to 33n.

If no cache hit is determined, a request is issued to the main storage device 2. The data read from the main storage device 2 is stored in the cache memory. In this case, the data already stored in the cache memory 3 is stored in the cache memory 3.
You have to get rid of it from above. The compartment selection circuit 38 selects the compartment whose last access time indicated by the LRU memory 37 is the oldest. At this time,
A compartment in which the microprogram storage flags 360 to 36n are not set is preferentially selected.
Therefore, the block in which the microprogram is stored is not evicted unless the microprogram is stored in all compartments of the same cache memory. Is almost never done.

FIG. 2 shows a second embodiment of the present invention. FIG.
Referring to FIG. 1, in the present embodiment, the arithmetic processing device 1, the main storage device 2, the cache memory 3, the address register 31, the address arrays 320 to 32n, and the data arrays 330 to 3
3n, valid flag memories 340 to 34n, address comparison circuits 350 to 35n, microprogram storage flag 3
60, LRU memory 37, compartment selection circuit 3
8.

The difference from the first embodiment shown in FIG.
The microprogram is stored only in a specific compartment, for example, compartment # 0. Therefore, microprogram storage flag 360 is provided not for blocks but for addresses of address arrays 320 to 32n.

When the data stored in the cache memory 3 is evicted from the cache memory 3, if the microprogram storage blog 360 is set,
When the selection is made by the compartment selection circuit 38, the compartment # 0 is excluded. Therefore, in the case where the addresses of the address arrays 320 to 32n are 16 kilowords and the block size is 64 bytes, when the microprogram capacity is up to 1 megabyte, no mishit occurs once the data is read into the cache memory 3.

FIG. 3 shows a third embodiment of the present invention. FIG.
Referring to FIG. 1, in the present embodiment, the arithmetic processing device 1, the main storage device 2, the cache memory 3, the address register 31, the address arrays 320 to 32n, and the data arrays 330 to 3
3n, valid flag memories 340 to 34n, address comparison circuits 350 to 35n, microprogram storage flag 3
60 to 36n, an LRU memory 37, and a compartment selection circuit 38.

The difference from the first embodiment shown in FIG.
The point is that the microprogram is mapped on the main memory so as to be read only at a specific address of the address arrays 320 to 32n.

For example, the storage space is 32-bit addressing (4 gigabytes), the block size is 64 bytes,
When the cache memory will be described for the case of the cache memory of 4 compartments 4 megabyte when the capacity of 64 kilobytes microprogram address on the main memory is 00000000 address _16, 00100
000 ₁₆ address, 00200000 ₁₆ address, and 003
00000 address _16, and maps each 16 kilobyte region starting. Then, the micro-program 0000 ₁₆ address on the cache memory 3 to 0100
_{The data} is read into 256 entries (1024 blocks) at address ₁₆ .

In this case, the microprogram storage flag may have 256 entries × 4 compartments = 1024 bits. In the present embodiment, similarly to the first embodiment, when data stored in the cache memory 3 is evicted from the cache memory 3, the compartments in which the microprogram storage flags 360 to 36n are not set have priority. Selected.

FIG. 4 is a diagram showing a fourth embodiment of the present invention. Referring to FIG. 4, the present embodiment includes an arithmetic processing device 1,
Main storage device 2, cache memory 3, address register 31, address arrays 320 to 32n, data array 3
30 to 33n, valid flag memories 340 to 34n, address comparison circuits 350 to 35n, a micro program selection flag 360, an LRU memory 37, and a compartment selection circuit 38.

The difference from the third embodiment shown in FIG.
The microprogram is stored only in a specific compartment, for example, compartment # 0. Therefore, microprogram storage flag 360 is provided not for blocks but for addresses of address arrays 320 to 32n.

For example, the storage space is 32-bit addressing (4 gigabytes), the block size is 64 bytes,
The case of a four-compartment cache memory 3 having a cache memory capacity of 4 megabytes will be described. In a volume of 64 kilobyte microprogram, a mapping to a region where the address on the main memory begins 00000000 address _16. Then, the micro-program 0000 ₁₆ of the compartment # 0 of the cache memory 3 to
It will be loaded into the 0400 ₁₆ address of the 1024 entry (1024 block). In this case, the microprogram storage flag should have 1024 entries × 1 compartment = 1024 bits.

In this embodiment, as in the second embodiment, when data stored in the cache memory 3 is evicted from the cache memory 3, if the microprogram storage flag 360 is set, the compartment selection is performed. In making the selection in circuit 38, compartment # 0 is omitted. This embodiment is excellent in that the number of bits of the microprogram storage flag 360 can be reduced when the capacity of the microprogram is smaller than the capacity of one compartment of the cache memory 3.

[0024]

As described above, according to the present invention,
When a microprogram is stored on the main storage device, the cache memory hit ratio directly affects the performance of the processing unit, but once the microprogram is read into the cache memory, it is controlled so as not to be evicted from the cache memory. By doing so, it is possible to increase the cache memory hit rate of the microprogram. Therefore, in spite of the fact that the microprogram is stored in the main memory, the performance is equivalent to the case where the microprogram is resident in the cache memory. Performance degradation due to hits can be minimized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a third embodiment of the present invention.

FIG. 4 is a diagram showing a fourth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 arithmetic processing unit 2 main storage device 3 cache memory 31 address register 320-32n address array 330-33n data array 340-34n valid flag memory 350-35n address comparison circuit 360-36n microprogram storage flag 37 LRU memory 38 compartment selection circuit

Claims (2)

(57) [Claims] 1. A set associative cache memory comprising a plurality of compartments between an arithmetic processing device and a main storage device, for controlling the arithmetic processing device stored in the main storage device. In a control storage caching method in an information processing apparatus that operates by caching a microprogram in the cache memory, a specific cache memory of the cache memory is used.
Micro program is stored only in memory address
As shown, the address in the main memory where the microprogram is stored
Address is limited to a specific address range, and a specific cache memory address of the cache memory indicating whether the microprogram is read in the cache memory.
Scan range flag corresponding to the block of the provided, if the flag when the swap event block has occurred indicates storage of microprogram sweeping blocks other compartments without the sweep in the block A control storage caching method, characterized in that: 2. An address on a main memory where a microprogram is stored is limited to a specific address range so that the microprogram is stored only at a specific cache memory address of the cache memory. Of the plurality of compartments, the compartment in which the microprogram is stored is limited to a particular compartment, and a specific cache memory address of the cache memory indicating whether the microprogram is read in the cache memory and a block of the particular compartment are provided. A corresponding flag is provided, and when a block swap event occurs, if the flag indicates storage of a microprogram, the block in the specific compartment is not flushed and the specific command is not executed. 2. The control storage caching method according to claim 1, wherein a block of a compartment other than the compartment is swept out.