JP3078303B2 - Cache memory control circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control method for ensuring the consistency of contents between a built-in cache memory and an external cache memory in a microprocessor having a built-in cache memory. is there.

[Prior Art] In the field of microprocessors, the difference in operation speed between a processor and a main storage device has become a problem as its operation speed has been improved. As the operation speed of the processing unit increases, the amount of instruction codes and data consumed by it also increases.Therefore, the processing capacity of the entire system must be used for the main storage unit unless a high-speed one that matches the operation speed of the processing unit is used. Can not be raised. However, if the entire main storage device having a large capacity is constituted by high-speed storage elements, the device becomes very expensive.

Therefore, as shown in FIG. 2A, a cache memory 22 is provided between the main storage device 23 and the processing device 21 so that the speed of the main storage device 23 is relatively slow as compared with the processing device 21. Do things faster. The cache memory 22 is a small-capacity but high-speed storage device, and holds a copy of the content of the part recently referred to by the processing device 21 in the main storage device 23. When referring to the processing device 23, first, the cache memory 22 is searched, and if the target data or instruction code exists there, it is used, and the main storage device 23 is not referenced. If the target object does not exist in the cache memory 22, it is taken out from the main storage device 23 and used, and at the same time, a copy thereof is stored in the cache memory 22.

Inside the cache memory 22, data is managed in units called blocks. The blocks existing inside the cache memory 22 are all in the main memory as described above.
Here is a copy of the block inside 23. All blocks in the cache memory 22 are called data indicating where the original of the block is stored in the main storage device 23 and data called a valid bit indicating that the block is valid. Comes with flags. A block, a tag, and a valid bit are collectively called an entry.

Searching the cache memory 22 means searching for a block having a tag equal to the address of the data requested to be referenced from all valid blocks existing in the cache memory 22. A case where such a block exists in the cache memory 12 is called a hit, and a case where it does not exist is called a mishit.

The configuration method of the cache memory 22 can be classified into several types according to the number of comparators used for comparing an address with a tag. Here, the set associative method which is closely related to the present invention will be described. In a set associative cache memory, the configuration is expressed by two parameters, the number of ways and the number of sets. The number of ways is a number indicating the number of comparators used for comparing an address and a tag at the time of retrieval, and the number of sets is a number indicating the number of blocks per comparator.

As an example of the configuration of the set associative cache memory, FIG. 3 shows the configuration when the number of ways is two (two-way set associative system). In FIG. 3, reference numeral 301 denotes a set index generation circuit, which generates a set index 302 from an address 300 of data for which a reference request has been made, based on an appropriate algorithm.

303 is the way $ 0 array, which is the way $ 0
Is a storage device for storing the entries belonging to the group, and stores the number of entries equal to the number of sets. Way $ 0
The array 303 is used for a cache memory search operation.
One entry is selected from the internal entries according to the set index 302, and its contents are output. Further, at the time of the block replacement operation, the block operates in accordance with the way # 0 selection signal 306 output from the way selection signal generation circuit 305, replaces the tag of the entry selected according to the set index 302 with the address 300, and replaces the block. Replace with the input data from the data input 308, and set the valid bit to logic "1" to indicate that the block included in the entry is valid.

The way # 1 array 304 performs the same operation as the way # 0 array 303. That is, at the time of a cache memory search operation, one entry is selected from the internal entries according to the set index 302 and the content is output. In addition, during the block replacement operation, the way selection signal generation circuit 305
Operates in accordance with the way # 1 selection signal 307 output from.

When updating an entry, the way selection signal generating circuit 305 generates a signal for designating a way in which an entry to be updated exists. If a miss occurs as a result of reference, block replacement is performed. In this case, a set selected according to the set index 302 (a set of entries having the same set index, including the number of ways equal to the number of ways) is included. It is necessary to determine which way of the two entries belongs to which is to be updated. Algorithms to do this include LRU algorithms that update the longest time since they were last referenced, or algorithms that have the longest time since they were read into cache memory. There is a FIFO algorithm or the like for which is updated. Although not shown in FIG. 3, the way selection signal generating circuit 305 has a signal line for inputting information required by the algorithm implemented therein.

The tag selected in accordance with the set index 302 during the search operation of the cache memory and included in the entry output from the way # 0 array 303 is input to the match detection circuit 309, where it is compared with the address 300. The result of the comparison is ANDed with the valid bit of the entry in the AND gate 311. If the result is logic one,
Output gate 313 is opened and the block of the selected entry is output to data output 315. That is, in each entry selected in each way according to the set index 302, its tag is equal to the address 300,
The block whose valid bit is logic 1 is output to the data output 315.

The OR gate 316 is for generating a signal indicating a hit or a mishit. That is, if there is an entry having a tag equal to the address 300 in either the way # 0 array 303 or the way # array 304 and the valid bit is logic 1, the output of the OR gate 316 becomes logic 1, This indicates that it is not necessary to refer to the main storage device because the target data has been output from the cache memory. Here, the operation of the set associative cache memory of the number of ways W and the number of sets S is summarized as follows.

The set index is calculated from the address of the data to be obtained by an appropriate algorithm.

One of the S sets is selected using the obtained set index.

Since the selected set contains W entries, the tag and address contained in each entry are
Are compared at once by the number of comparators. If there is an entry that includes a tag that matches the address requested to be referenced and whose valid bit is logical 1 (contains valid data), the contents of the block are sent to the processing device as a hit as a hit. If there is no such entry, the entry replacement processing is performed assuming that there is a miss hit.

If the currently selected set has room,
The data requested to be referenced is fetched from the main storage device and stored there, and a tag and a valid bit are added. If there is no room in the set, the replacement priority of each of the W entries is evaluated in accordance with an appropriate algorithm, the entry with the highest replacement priority is invalidated, and the data retrieved from the main storage device is deleted. And a tag and a valid bit are assigned. The data retrieved from the main storage device is also sent to the processing device.

By the way, the cache memory is provided to make a relatively slow main storage device seem faster. When viewed from the processing device side, the main storage device and the cache memory must not appear to be separate, but must appear to have one high-speed main storage device. Therefore, as shown in FIG. 2 (b), when considering a configuration such as a multiprocessor system that performs processing while sharing the main storage device 23 among a plurality of processing devices 211, 212,. , 222,... And the main storage device 23, it is necessary to ensure content consistency. For example, in FIG. 2B, it is assumed that the content of a certain block has been rewritten by an instruction from a certain processing device 211. At this time, it is necessary to match the contents between all the cache memories 221, 222,... And the main storage device 23. As a method that is often performed as a method of matching, the cache memory 221 added to the main storage device 23 and the processing device 211 that has instructed the rewrite is rewritten so as to have the same contents, and the other cache memories 222,. As for the method, there is a method of invalidating all the blocks on the cache memory corresponding to the rewritten blocks.

When such a method is used, a bus monitoring circuit for detecting a write operation to the main storage device is required. The bus monitoring circuit is a circuit for monitoring the data transfer status on the bus line 25 in FIG. 2 (b) and detecting that writing to the main storage device 23 has been performed.

The following document introduces a method of matching contents between a main storage device and a cache memory built in a microprocessor by hardware according to this method.

Reference: Integrated MMU, cache raise system-level is
sues "COMPUTER DESIGN" May 15, 1987 The microprocessor introduced in the literature has a 2-way set associative data-only cache memory and a direct mapping method (equivalent to a set associative method with one way). ) Instruction-specific cache memory. In each of the internal cache memories, a function of resetting the valid bit of the entry selected by the set index given from the outside to logical 0 to each way and invalidating a block included in the entry is added. Means for realizing the above method.

Since the cache memory built in the microprocessor generally has a small capacity, an external cache memory is further added outside the chip.
In this case, the contents of both the internal cache memory and the external cache memory must be consistent with the contents of the main storage device. In the example introduced in the above document, a direct map type external cache memory is further provided outside the microprocessor. In such a case, if the condition that the block existing in the internal cache memory always exists in the external cache memory is satisfied, the bus monitoring circuit is shared between the internal cache memory and the external cache memory. It is stated that by doing so, the amount of hardware can be reduced. In order to satisfy the condition, when an entry is updated in the external cache memory, all entries in the internal cache memory corresponding to the entry updated in the external cache memory are invalidated. Has been introduced.

[Problem to be Solved by the Invention] A problem that occurs when an external cache memory is added to a microprocessor having a built-in cache memory based on the prior art and hardware ensures consistency of contents with a main storage device. For the sake of explanation, assume a system as described below.

(1) The built-in cache memory has the following features.

This is a set associative system with the number of ways Wi and the number of sets Si.

By specifying a set index from outside the chip, the contents can be invalidated in a set unit.

(2) An external cache memory having the following features is added to a microprocessor having a built-in cache memory having the above features.

It is a set associative system with the number of ways We and the number of sets Se (however, We ≧ Wi, Se ≧ Si).

When a bus monitoring circuit is provided and a write operation to the main storage device is detected, (a) it is checked whether or not a copy of the rewritten block in the main storage device exists in itself; (B) Generates a set index of the internal cache memory corresponding to the address where the write operation was performed, and rewrites it on the main storage device using the set index. The following operations are performed to invalidate the copy of the specified block existing in the internal cache memory.

In such a system, if the condition that the same block always exists in the external cache memory is satisfied, the internal cache memory and the internal cache memory are used as described in the description of the related art. As described in the reference in the preceding section, the amount of hardware can be reduced by sharing the bus monitoring mechanism with the external cache memory.

However, in general, the external cache memory is searched only when the internal cache memory has a mishit.Therefore, when focusing on a specific block, the external cache memory is viewed from the internal cache memory side and from the external cache memory side. And the frequency of reference may be different.
At this time, if there is a reference request that causes a miss in both the internal cache memory and the external cache memory, the block replaced in the internal cache memory and the block replaced in the external cache memory may not be the same. FIG. 4 shows how such a case occurs when both the internal cache memory and the external cache memory use the 2-way set associative method and the LRU method as a replacement algorithm.

In FIG. 4, reference numeral 41 denotes the contents of a certain set in the internal cache memory. The left column shows the block of the entry belonging to way # 0, and the right column shows the way # 1.
Represents a block of entries belonging to. Now, it is assumed that block A exists in way # 0 of this set and block B exists in way # 1. An asterisk (*) on the right side of B indicates that if the next miss occurs, B, which is the content of way # 1, is replaced. 42 indicates the contents of the set corresponding to 41 in the external cache memory.
The notation is the same as in the case of 41.

FIG. 4A shows a state where the contents of the internal cache memory and the contents of the external cache memory match.

Here, it is assumed that the processing device refers to B. At this time, since the built-in cache memory is hit, the external cache memory is not referred. As a result of the hit, in the built-in cache memory, the state of the block to be replaced in the case of the next miss hit is as shown by 43 instead of B to A. However, at this time, since the external cache memory has not been referred to, the contents remain unchanged as shown at 44 (FIG. 4 (b)).

In this state, it is assumed that a block C which is neither A nor B is referred to next. At this time, both the internal cache memory and the external cache memory cause a miss hit. As a result, block replacement occurs in both cache memories. In the internal cache memory, A is replaced and the state as shown at 45 is obtained. However, in the external cache memory, B is replaced and the state as shown at 46 is obtained. (FIG. 4 (c)).

In the state shown in FIG. 4C, the condition for sharing the bus monitoring circuit between the internal cache memory and the external cache memory described in the reference is not satisfied.

If the bus monitoring circuit is independently provided in both cache memories, there is no problem in function, but the number of components in the whole system increases, so this is not a very desirable solution.

In an example in the literature, in order to avoid such a phenomenon, when an entry is updated in the external cache memory, all entries corresponding to the entry updated in the external cache memory are stored in the internal cache memory. A new block is being read after invalidation. FIG. 5 shows this state in the same notation as FIG.

In FIG. 5, steps 51 to 54 (FIGS. 5A and 5B) are the same as those in FIG. Assume that block C is referred to in this state. The operation of the external cache memory is exactly the same as that described with reference to FIG. On the other hand, in the built-in cache memory, the block C is read after the contents of the set are once invalidated as shown in FIG. 55 as a result of the mishit, and the state shown in 57 is obtained (FIG. 5 (c)). ).

Paying attention to 56 and 57 in FIG. 5 (c), the condition that the block existing in the internal cache memory always exists in the external cache memory is satisfied. Can be shared.

However, when this method is used, even the block A which should not be invalidated in the built-in cache memory is invalidated. As a general characteristic of the set associative cache memory, if the capacity is the same, increasing the number of ways tends to increase the probability of hitting, so the number of ways is as large as possible even when an external cache memory is provided. The performance of the system can be enhanced by providing the above. However, in a situation in which useless invalidation is likely to occur as described here, the performance is not improved as expected because the damage caused by useless invalidation increases as the number of ways increases.

An object of the present invention is to provide a cache memory control method capable of reducing useless invalidation operations in a built-in cache memory which occur when an entry in an external cache memory is updated.

[Means for Solving the Problems] In the cache memory control method of the present invention, an external cache memory is provided outside a microprocessor having a built-in cache memory, and blocks on the cache memory corresponding to each block of the main storage device are provided. In a cache memory control system employing a set associative system in which a plurality of sets are provided, a bus monitoring unit for detecting writing to a main storage device in an external cache memory is provided. A control signal is supplied from the memory to the internal cache memory, and the way in which the entry to be replaced in the internal cache memory is stored is designated from the outside so as to match the external cache memory.

[Operation] If a block that is neither in the internal cache memory nor in the external cache memory is referred to and a miss occurs, the entry is replaced with the mishit. At this time, the way in the internal cache memory to be replaced is replaced. Selection is not restricted from the inside, which is restricted by the replacement method such as LRU algorithm and FIFO algorithm.
An external instruction is issued from the external cache memory so as not to be restricted by such a method.

Instructing from the external cache memory makes it possible to select a way to be replaced based on an instruction based on the external cache memory. That is, the external cache memory does not know all states of the internal cache memory, but at least,
It has the main storage device write information by the bus monitoring means, and it is possible to instruct the replacement result of the internal cache memory to match the replacement result of the external cache memory based on this information.

Therefore, a replacement made based on such an external instruction does not invalidate blocks that do not need to be invalidated, and the same blocks always exist in the internal cache memory as those in the external cache memory. Since the bus monitoring mechanism sharing condition that the bus monitoring mechanism exists also holds, the bus monitoring means only needs to be provided in the external cache memory, and the bus monitoring means can be shared.

Embodiment FIG. 6 shows the configuration of a two-way set associative cache memory according to an embodiment of the present invention. The components from 600 to 616 are the same as those from 200 to 216 in FIG. However, the way # 0 array 603 and the way array 604 have, in addition to the basic functions described in FIG. 3, invalidation of a set unit necessary when ensuring consistency of contents with the main storage device by hardware. There is an input to perform. These are connected to the invalidation set index input 620. This embodiment is characterized by the components 621
624 was added. Reference numeral 621 denotes a selector which is controlled by an external selection signal enable signal 624, and switches between outputs 606 and 607 of a built-in way selection signal generation circuit 605 and external way # 0 selection signals 622 and way # 1 selection signals 623, It is used to output a way # 0 selection signal 626 and a way # 1 selection signal 627.

When the external cache memory is not added, the entry is updated in accordance with the instruction of the built-in way selection signal generation circuit 605, but when the external cache memory is added, the entry is updated according to the instruction of the way selection signal generation circuit of the external cache memory. Therefore, the entry is updated. An external selection signal enable signal 624 is provided to perform the control.

FIG. 1 shows an example in which a two-way set associative external cache memory is added to a microprocessor having a built-in cache memory having the configuration shown in FIG. A portion 11 surrounded by a broken line in the drawing is a microprocessor. The microprocessor 11 includes a built-in cache memory 13 on the same chip in addition to the processing device 12. The built-in cache memory 13 has a configuration as shown in FIG.

The external cache memory 15 has a function of generating a way select signal for the built-in cache memory 13 necessary for implementing the present invention, in addition to the function described in (2) of the description of the problems of the prior art. When the external cache memory function as described in (2) is simplified and repeated, the external cache memory function is set associative and has a bus monitoring circuit 19 to be shared, and this bus monitoring circuit 19 If it exists, it is matched, and if it does not exist, the copy existing in the internal cache memory is invalidated.

External cache memory 15 to internal cache memory 13
The signal line 18 supplied to the bus is a collective expression of the internal cache memory control signal, and a signal line 620 for specifying a set index when performing invalidation and for specifying a way when performing replacement. It consists of signal lines 622-624. Signals on the signal lines 622 to 624 for specifying a way when performing this replacement are sent out based on the monitoring result of the bus monitoring circuit 19.

The main storage device 67 is the same as that shown in FIGS. 2 (a) and 2 (b).

FIG. 7 shows the states of the corresponding entries in the built-in cache memory and the external cache memory in this embodiment according to the same notation as in FIGS. 4 and 5. In FIG. 7, reference numerals 71 and 72 (FIG. 7A) show the initial state.

Next, when B is referred to, a hit occurs in the internal cache memory, and the state shown in 73 and 74 is reached (FIG. 7 (b)).

 Up to this point, the operation is the same as in FIGS. 4 and 5.

Further, when C is referenced, both the built-in cache memory and the external cache memory cause a miss hit, so the entry is updated. At this time, in the case of FIG. 4, both cache memories have updated their entries based on their own judgment, so that the condition for sharing the bus monitoring circuit has not been satisfied. Further, in the case of FIG. 5, the condition A is invalidated up to A which is not necessary to be invalidated. In FIG. 5, the contents of all the ways are once invalidated. However, in this embodiment, B is replaced according to an external way selection signal without invalidation (No. 7).
Figure (c).

That is, at the time of a block replacement operation, the external cache memory 15 is stored in the internal cache memory based on the monitoring result of the bus monitoring circuit 19 provided in the external cache memory 15.
The internal cache memory control signal 18 is output to 13. The way selection signals 626 and 627 output from the selector 621 by the external selection signal enable 624 are switched from the inside to the outside way selection signals 622 and 623. At this time, the external way # 0 selection signal 622 takes a non-selected value, and the way # 1
The selection signal 623 has a selection value. For this reason, in the built-in cache memory, the way # 1 array 604 operates according to the external way # 1 selection signal 627 output from the selector 621, and the block to be replaced when the next miss occurs belongs to the way # 0. Despite being A, block B of the entry belonging to way # 1 is updated and replaced with block C. In the external cache memory, the block B to be replaced in the case of the next miss hit is replaced with the block C. As a result, the contents of the internal cache memory are adjusted to the contents of the external cache memory, and the state shown at 75 and 76 in FIG. 7 (c) is obtained. In this way,
According to this embodiment, since the internal cache memory is matched with the external cache memory, the bus monitoring circuit 19 only needs to be in the external cache memory.

Similarly, FIG. 8 shows the operation when the internal cache memory has two ways and the external cache memory uses the four-way set associative method.

81 and 82 (FIG. 8 (a)) show the initial states of the internal cache memory and the external cache memory, respectively.
81 is the same as 71. Since the number of ways of the external cache memory is four this time, there are four entries in the external cache memory set corresponding to the set of the internal cache memory shown at 81.
Blocks such as B, C, and D are stored. 82
In the following, it is assumed that D is to be replaced when the next miss occurs in the external cache memory.

Here, it is assumed that the processing device refers to B. At this time,
Since the built-in cache memory is hit and the external cache memory is not referred to, the state shown in 83 and 84 is obtained (FIG. 8 (b)).

Next, it is assumed that the processing device refers to the block E which is not included in the internal cache memory. At this time, the block D existing in the way # 3 is replaced in the external cache. However, the built-in cache memory is of the two-way set associative type and has only the way # 1.
Therefore, the even way of the external cache memory is made to correspond to the way # 0 of the internal cache memory, and the odd way of the external cache memory is changed to the way # 1 of the internal cache memory.
Let's make it correspond. In this way, block D existing in way # 3 on the external cache memory is replaced, and B present in way # 1 in the internal cache memory is replaced by an instruction from the external cache memory. The state is as shown in FIG. 86 (FIG. 8 (c)).

This state satisfies the condition for sharing the bus monitoring circuit. When the number of sets of a general built-in cache memory is n and the number of ways of an external cache memory is m (m ≧ n), the many-to-one correspondence from m to n is appropriately determined to achieve the present invention. Implementation is possible.

As described above, according to the present embodiment, a shared bus monitoring circuit is provided in the external cache memory, and the way selection signal is switched from the inside to the external way selection signal in accordance with the detection result of the bus monitoring circuit. When replacing an entry due to a mishit in the set-associative built-in cache memory built in the microprocessor, the way to be replaced is selected according to an instruction from outside the chip based on the external cache memory. Therefore, the internal cache memory can be easily matched with the external cache memory outside the chip. Therefore, it is not necessary to provide the bus monitoring circuit independently in both cache memories, and it is not necessary to invalidate the block in the first place. There is no need to invalidate it.

In the above embodiment, the case where the mapping method between the main memory and the cache memory is the set associative method is described. However, the set associative method includes a direct mapping method which is a special example thereof.

[Effects of the Invention] According to the present invention, it is possible to reduce a useless invalidation operation of a built-in cache memory which occurs when a microprocessor having a built-in cache memory and an external cache memory are used in combination. At the same time, the bus monitoring means can be shared.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a cache memory control system according to this embodiment, FIG. 2 is a block diagram showing a conventional cache memory control system, and FIG. 3 is a block diagram showing a set associative cache memory according to a conventional example. 4 is an entry state diagram of a general internal cache memory and an external cache memory, FIG. 5 is an entry state diagram of a conventional internal cache memory and an external cache memory according to a conventional example, and FIG. 6 is a set associative method according to the present embodiment. 7 is a block diagram showing the cache memory of FIG. 7, FIG. 7 is an entry state diagram of a 2-way set associative built-in cache memory and an external cache memory according to the present embodiment, and FIG. 8 is a 4-way set associative built-in cache according to the present embodiment. Entries between memory and external cache memory It is a state diagram. 11 is a microprocessor, 12 is a processing device, 13 is a built-in cache memory, 15 is an external cache memory, 17 is a main storage device, 18 is an internal cache memory control signal, and 19 is a bus monitoring circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-199251 (JP, A) JP-A-64-13650 (JP, A) JP-A-61-156346 (JP, A) JP-A-1 279342 (JP, A) JP-A-62-84350 (JP, A) JP-A-2-188847 (JP, A) JP-A-3-230238 (JP, A) JP-A-60-237554 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12 / 08,12 / 12

Claims (1)

(57) [Claims] 1. A main storage device for storing a plurality of data, an internal cache memory for storing first and second data corresponding to a part of the plurality of data, and a processing device for outputting reference data A cache memory control circuit comprising: a microprocessor provided with a microprocessor; and an external cache memory provided outside the microprocessor and storing at least third and fourth data respectively corresponding to the first and second data. A bus monitoring means provided in the external cache memory so as to be shared with the external cache memory and detecting a write operation of the processing device to the main storage device; and wherein the reference data is the first to fourth data. If the data does not match, the internal cache memory is determined based on the detection result of the bus monitoring means. A control signal selecting means for switching the control to the control from the external cache memory about the outside by the control from the cache memory, when replacing said third data to the reference data of the first
The cache memory control circuit, further comprising: data replacement means for replacing data with the reference data and replacing the second data with the reference data when replacing the fourth data with the reference data. .