JP2973873B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronizing circuit, and more particularly to a demultiplexing circuit which needs to perform frame or packet synchronization and byte synchronization in high-speed data communication or the like.

[0002]

2. Description of the Related Art As a conventional frame synchronization circuit of this type, for example, Japanese Patent Application Laid-Open No. 4-365239 discloses a frame synchronization circuit as shown in FIG. In addition,
FIG. 6 shows a case where 1-byte data is composed of 3 bits for explanation.

In FIG. 6, reference numeral 21 denotes a transmission signal input terminal to which a transmission signal is input, and reference numeral 22 denotes a serial / parallel converter for rearranging serial data into a parallel structure, which is constituted by a shift register or the like. Reference numeral 23 denotes a delay unit, which is configured by a D-type flip-flop (abbreviated as “DF / F”).

Reference numeral 24 denotes a synchronization pattern detection circuit, which is composed of n sets of logic gates corresponding to the synchronization pattern.

[0005] Reference numeral 25 denotes a phase selection unit, which comprises an exclusive control unit 25a for instructing phase selection and a logic gate 25b for phase selection. Reference numeral 12 denotes a synchronization protection circuit required for frame synchronization, which is composed of a contention counter and the like.

Reference numeral 26 denotes a buffer for establishing byte synchronization between a plurality of byte synchronization circuits for a byte parallel multiplexing apparatus, and reference numeral 8 denotes a byte synchronization signal serving as a clock for reading out the buffer. Numeral 11 denotes a byte-synchronized byte parallel output.

Next, the operation of the frame synchronization circuit shown in FIG. 6 will be described.

The serial-structured received signal input from the transmission signal input terminal 21 is parallelized in the serial-parallel converter 22. The parallelized signal is sent to the delay unit 23 with a byte length n.
, And a parallel signal having n kinds of phases is generated.

A synchronous pattern detection circuit 24 inputs parallel signals of n types of phases, simultaneously detects a pattern of a synchronization byte, selects a phase that has been successfully detected first by a phase selection unit 25, and inputs it to a buffer 26. I do.

When bit synchronization is achieved in the byte paralleling multiplexing device, the byte synchronization signal 8 is used as a clock for reading out the buffer 26 because n types of phases can be considered for the parallel signal input to the buffer 26. .

In the case of packet synchronization, the delay unit 2
The received signal is stored in a buffer in order to prevent data loss due to delay at 3 or the like.

[0012]

However, in the above conventional example, in order to realize a frame synchronization circuit using a low-speed logic circuit, the number of bits constituting a byte (n) is required.
Logic circuits for detecting the synchronization patterns.

In addition, since the synchronization process takes a long time, synchronization protection takes a long time for a frame in which a byte for synchronization appears at a fixed period, such as frame synchronization, and a packet in which a packet appears intermittently. A buffer was needed.

When a desired byte synchronization signal is recorded, a buffer for synchronization is further required.

Accordingly, it is an object of the present invention to provide a frame synchronization circuit which solves the above problems and realizes a high-speed operation of a byte synchronization circuit in a byte parallel multiplexing apparatus with a simple configuration.

[0016]

In order to achieve the above object, according to the present invention, a predetermined number of bits (= n) is set to 1 byte.
Byte-based frames or packets
In the frame synchronizer that synchronizes,
(2n-1) or more flip-flops
And the flip-flops are connected in a cascade configuration.
And a set of n consecutive flip-flops
And n sets of parallel signals shifted by one time slot
And a first shift register for outputting the n sets of parallel signals.
A selector for selecting one of the signals,
The parallel output of successive n flip-flops of the
Input synchronization frame of input frame or packet
A synchronous pattern detection circuit for detecting a cut pattern;
According to the timing of the output of the synchronous pattern detection circuit, n
Synchronizes with the byte synchronization signal of the specified phase of the set of parallel signals
To control the selected parallel signal by the selector
Driven by a selector control circuit and the byte synchronization signal
n flip-flops connected in cascade
Of the parallel signal selected by the selector.
A second slot for synchronizing the system slot with the byte synchronization signal.
Further comprising a shift register, a to provide a frame synchronization circuit according to claim.

In the present invention, preferably, the first sheet
Shift register is the (2n-1) flip-flops
In addition to the predetermined
Flip flows equal to the number of delays of the im slot
And outputting a predetermined signal rather than outputting the parallel signal.
Parallel to the synchronous pattern detection circuit earlier by the time slot
It is characterized by outputting a signal .

In the present invention, preferably, the synchronization
Between the pattern detection circuit and one input terminal of the selector;
The period of the detection signal output from the synchronous pattern detection circuit
A synchronization protection circuit for checking the characteristics is inserted .

According to the present invention, the predetermined number of bits is 1 byte.
Of a frame or packet composed of bytes
For byte synchronization, the frame or packet
From each other from the parallel signal obtained by parallelizing
Generating a plurality of parallel outputs having different slots;
Synchronized with the byte synchronization signal of the predetermined phase of the parallel output
Select and output time slot parallel output
I can .

Further , the present invention provides n bits (where n is a predetermined number)
Is a byte, and is composed of bytes.
When synchronizing the byte of a frame or packet,
The frame or packet is parallelized byte by byte
N tie shifted by one time slot from parallel signal
And generates a parallel output for the
Out of the parallel output of the predetermined phase
Parallel output of time slot synchronized with byte synchronization signal
You may make it select and output .

[0021]

The principle and operation of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram for explaining a frame synchronization circuit according to the present invention. FIG. 1 shows a case where one byte is composed of three bits for the sake of explanation.

Referring to FIG. 1, transmission signal 4 is input to shift register 1, and first to
5, the outputs of the DF / Fs 16-1 to 16-5 are branched,
For each of the three consecutive DF / F outputs,
Shift register 1 as parallel outputs 17-1 to 17-3 of
Output from

The first parallel output 17-1 is further branched and input to the synchronization pattern detection circuit 3, and when a synchronization pattern is detected, the detection signal is sent to the selector control circuit 1
9 is input.

The byte synchronization signal 8 is also input to the selector control circuit 19 at the same time. The selector control circuit 19 outputs three parallel outputs 17-1 to 17-1 synchronized with the byte synchronization signal 8.
Selector 1 to make 7-3 selected by selector 18
8 to output a selection signal.

The parallel output selected and output from the selector 18 is identified by the DF / F array 10 driven by the byte synchronization signal 8, and becomes the byte-synchronized parallel output 11.

FIG. 2 is a timing chart for selecting three parallel outputs.

Referring to FIG. 2, the transmission signal (b) is inputted in the order of the first bit of the byte → the second bit → the third bit → the first bit. In addition, FIG.
In the byte synchronization signal, a bit clock is extracted from a transmission signal (reception signal), and the extracted clock is frequency-divided into, for example, the number of bits constituting one byte (in the case of 1 byte = 8 bits, frequency division by 8). It is obtained by doing.

First to fifth DF / Fs 16-1 to 16-5
Are delayed from the input signal by 1 to 5 time slots, respectively, as shown in FIGS. 2 (c) to 2 (g).

Therefore, the first to third parallel outputs 17-1
17-3 are as shown in FIGS. 2 (h) to 2 (j).

In FIGS. 2 (h) to 2 (j), the hatched parallel outputs are synchronous with the bytes (ie, "synchronizing bytes"), and the same parallel outputs are assigned to three different time slots. Is obtained.

Since the second parallel output 17-2 is synchronized with the byte synchronization signal (a) among the three parallel outputs, the second parallel output 17-2 is selected by the selector 18. , The byte synchronization signal 8 by the DF / F array 10
, A byte-synchronized parallel output is obtained.

For byte recognition in parallel output, a frame or packet synchronization byte is used.

The synchronization byte is detected by the synchronization pattern detection circuit 3. As shown by the hatched portions in FIGS. 2 (h) to 2 (j), the first to third parallel outputs have 0 to 2 times. A synchronization byte is obtained with a slot delay. In each parallel output, a parallel output synchronized with the byte is obtained every three time slots after the synchronization byte is obtained.

Therefore, the timing at which each parallel output outputs a signal synchronized with the byte can be known from the synchronization byte detection time.

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

[0037]

Embodiment 1 FIG. 3 is a block diagram showing a configuration of a frame synchronization circuit according to a first embodiment of the present invention.

This embodiment deals with a transmission signal in which one byte is composed of 8 bits, and shows a configuration of a frame synchronization circuit in an apparatus for multiplexing a plurality of transmission signals.

Referring to FIG. 3, a transmission signal 4 is input to a first shift register 1-a which is composed of 15 DF / Fs and driven in synchronization with the transmission signal 4.

D / F in the first shift register 1-a
The output of the first shift register 1
-A outside the first shift register 1-a
Are the outputs of eight consecutive DF / Fs (for example, 1st to 8th, 2nd to 9th, 8th to 15th), and the first to eighth parallel outputs 17-1 to 17-17 are output. −8, and input to the first to eighth parallel signal output gates 6-1 to 6-8 each including eight AND gates in order from the one with the earliest phase.

The connection to the AND gate in each of the parallel signal output gates 6-1 to 6-8 is also assumed to be connected in a fixed order from the one with the earliest phase in the parallel output.

First to eighth parallel signal output gates 6-1 to 6
The other input to the AND gate in -8 connects the outputs of the first to eighth branch output AND gates 7-1 to 7-8 in the order described later.

DF / F in the first shift register 1-a
A parallel output obtained by branching the first eight outputs of F (parallel output input to the first parallel signal output gate 6-1) is input to the synchronous pattern detection circuit 3.

The output of the synchronous pattern detection circuit 3 is input to one input terminal of a two-input switch 5, and the output of the two-input switch 5 is a DF / D driven in synchronization with eight transmission signals 4.
F is input to the second shift register 2.

The other input terminal of the two-input switch 5 is
The output of the eighth DF / F of the shift register 2 is input.

Each DF / F in the second shift register 2
Are input to one input terminal of each of the first to eighth branch output AND gates 7-1 to 7-8 in order.
Through 8 branch output AND gates 7-1 through 7-8
D- of the second, seventh, and second shift registers 2
The outputs of the F / F are sequentially output from the first to eighth parallel signal output gates 6-
1 to 6-8.

This correspondence is to connect those having the same delay from the synchronous pattern detection time.

First to eighth branch output AND gates 7-1 to 7-1
The other input terminal of each of 7-8 is a byte synchronization signal 8
Is entered.

In this embodiment, the second shift register 2, the two-input switch 5, and the first to eighth branch outputs AND
The gates 7-1 to 7-8 constitute the selector control circuit 19 shown in FIG.

First to eighth parallel signal output gates 6-1 to 6
The output of −8 has the same arrangement in the parallel signal output gates as AN.
Grouped into eight groups for each D gate,
The signal is input to a parallel signal selection gate 9 composed of a gate.

Each OR gate takes the logical sum (OR) of eight signals inputting the output of a group of eight AND gates.

First to eighth parallel signal output gates 6-1 to 6
-8 and the parallel output selection gate 9 constitute the selector 18 in FIG.

The eight outputs of the parallel output selection gate 9 are input to a DF / F array 10 composed of eight DF / Fs driven by a byte synchronization signal, and the DF / F array 1
It is taken out as a parallel output 11 byte-synchronized by 0.

The byte multiplexing section 14 comprises first to eighth parallel / serial converters 13-1 to 13-8. The first to eighth parallel / serial converters 13-1 to 13-8 are synchronized with a plurality of bytes. The bits of the corresponding phase of the parallel output 11 are collected and output as a byte-multiplexed parallel output 15.

Referring to FIG. 3, the operation of this embodiment will be described below.

The transmission signal 4 input to the first shift register 1-a is output as eight parallel signals with a delay of one time slot, and the first to eighth AND gate arrays 6-1 to -1 are output.
Input to 6-8.

When the synchronization byte of the frame or packet exactly matches the first to eighth DF / Fs of the first shift register 1-a, the outputs of these DF / Fs are branched. Synchronous pattern detection circuit 3 being monitored
Input the detection signal to the two-input switch 5.

This signal is input to the second shift register 2 and sets the two-input switch 5 to the set state. During the frame or packet time, the output of the eighth DF / F of the second shift register 2 is output. Can pass through the two-input switch.

Therefore, while the two-input switch 5 is in the set state, the second shift register 2 becomes a cyclic shift register, and the detection signal output from the synchronous pattern detection circuit 3 is transmitted through the second shift register 2. Continue patrol.

The output of each DF / F of the second shift register 2 is branched and output to the outside of the second shift register 2 to open and close with a byte synchronization signal.
It passes through gates 7-1 to 7-8. Therefore, one of the DF / F branch outputs of the second shift register 2 synchronized with the byte synchronization signal is output through the branch output AND gate.

On the other hand, the transmission signal 4 is converted into eight parallel signals by the first shift register 1-a, and when the synchronous pattern detection circuit 3 outputs a detection signal (DF / F / D of the first shift register 1). F when the byte for synchronization falls within the first to eighth F), the first to eighth parallel signal output gates 6
-1 to 6-8 are sequentially input with a byte for synchronization with a delay of one time slot, and by taking out a byte synchronized with the byte synchronization signal, a byte-synchronized parallel output having a time slot of the transmission signal is obtained. can get.

The first to eighth parallel signal output gates 6
First to eighth branch output AND gates 7 arranged so that opening and closing of -1 to 6-8 are equal in delay from detection of a synchronous pattern, respectively.
By performing in steps -1 to 7-8, a parallel output of a desired time slot is obtained.

First to eighth parallel signal output gates 6-1 to 6
Since there is only one output out of -8, each parallel signal can be easily selected by a parallel output selection gate 9 that combines the corresponding bits into an OR gate.

Since the output of the parallel output selection gate 9 remains the time slot of the transmission signal, the DF / F array 10 driven by the byte synchronizing signal re-identifies the time slot as a time slot synchronized with the byte. It is output as a synchronized parallel signal 11.

A plurality of byte-synchronized parallel signals 11 are input to one byte multiplexing unit 14.

In the byte multiplexing unit 14, the first to eighth parallel / serial conversion units 13-1 to 13-8 collect the bits of the corresponding phases of the plurality of byte-synchronized parallel signals, and , And then output as a byte-multiplexed parallel output 15.

The frame synchronization circuit according to this embodiment has no delay in the delay unit 23 as compared with the conventional example. Therefore, the synchronization time is 3/4 on average in frame synchronization, and 1 in packet synchronization without delay in the buffer. / 2. In addition, since a single (one) logic circuit is required for the synchronous pattern detection circuit 3, the mounting area is about 4/5.

[0068]

Embodiment 2 FIG. 4 is a block diagram showing the configuration of a second embodiment of the frame synchronization circuit according to the present invention.

This embodiment deals with a transmission signal that constitutes one byte with eight bits, and shows an embodiment of an apparatus for multiplexing a plurality of these transmission signals. 4, components having the same functions as those in FIG. 3 are denoted by the same reference numerals.

In the first embodiment shown in FIG. 3, the logic circuit of the synchronous pattern detection circuit 3 operates at a high speed, and the synchronous pattern can be detected without delay. In order to cope with the circuit delay, the first shift register 1-a in the first embodiment shown in FIG.
And the connection between the first shift register 1-a and the synchronous pattern detection circuit 3 is changed.

Referring to FIG. 4, third shift register 1
−b is composed of 15 (= 2 × 8−1) or more DF / Fs, and is output to the first parallel signal output gate 6-1.
The outputs of eight consecutive DF / Fs before the DF / F are branched and input to the synchronous pattern detection circuit 3.

That is, the third shift register 1-b in the present embodiment increases the number of DF / Fs constituting the first shift register 1-a in FIG. Is moved forward. The other configuration is the same as that of the first embodiment shown in FIG. 3, and the description is omitted.

Referring to FIG. 4, the operation of this embodiment will be described. The transmission signal 4 input to the third shift register 1-b is first input to the synchronization pattern detection circuit 3, and is input to the first parallel signal output gate 6-1 after an appropriate time slot.

The time slot difference corresponds to the delay time generated by the logic circuit of the synchronous pattern detection circuit 3. By using such a configuration, the delay time can be absorbed.

Therefore, the third shift register 1-b
It is necessary to increase the number of DF / F from 15 to a number equal to the time slot difference.

For example, if a delay corresponding to three time slots occurs in the synchronous pattern detection circuit 3, the third shift register 1-b adds three stages of DF / Fs and the first parallel signal output gate 6- Eight consecutive Ds including three additional DF / Fs, which are three time slots earlier than output to
-Outputs eight parallel signals from the F / F to the synchronous pattern detection circuit 3. 8 consecutive D-Fs including expanded DF / F
When a synchronization pattern appears on the F / F output, the synchronization pattern detection circuit 3 outputs a detection signal.

Since the detection signal is delayed by three time slots by the synchronous pattern detection circuit 3, it passes through the two-input switch 5 and outputs the signals output from the first branch output AND gates 7-1 to 7-8. The timing coincides with the timing at which a byte for synchronization is output from the first parallel signal output gate 6-1.

Thereafter, a byte-synchronized parallel output is obtained according to the same operation as in the first embodiment shown in FIG.

In this embodiment, the delay generated in the synchronous pattern detection circuit 3 is for three time slots. However, for other delays, the DF / F may be increased by an amount corresponding to the delay. . If the delay does not match the time slot difference, the delay is adjusted by an output line or the like.

The frame synchronization circuit of this embodiment can cope with a high-speed transmission signal or a complicated logical configuration, and the synchronization time is not different from that of the first embodiment.

[0081]

Third Embodiment FIG. 5 is a block diagram showing the configuration of a third embodiment of the frame synchronization circuit according to the present invention. In this embodiment, a configuration of a device that handles transmission signals constituting one byte with 8 bits and multiplexes a plurality of transmission signals is shown. FIG.
In FIG. 6, the same reference numerals are given to components having the same functions as those in FIG.

Although the present embodiment is effective only when the frame is synchronized, the detection signal of the synchronization pattern detection circuit 3 is input to the synchronization protection circuit 12, and the frame synchronization signal used for the synchronization protection is changed to a two-input switch. Enter 5 Otherwise, the configuration is the same as that of the second embodiment shown in FIG.

In this embodiment, when handling a frame, the periodicity of the detection signal is checked by the synchronization protection circuit 12, and the frame synchronization signal used at this time is supplied to the second shift register 2 through the two-input switch 5. As a result, a synchronization protection function is provided, and the frame synchronization circuit enables reliable frame synchronization.

In multiplexing the byte-synchronized parallel outputs 11 in each of the above embodiments, if the phase of the byte synchronization signal 8 is sufficiently stable and the multiplexing circuit has a sufficient phase margin, DF The / F array 10 is not required.

The byte synchronization method described in the above embodiment is effective even if the bit pattern for frame synchronization is not a byte.

As described above, the present invention has been described with reference to the above embodiments. However, the present invention is not limited to the above embodiments, but includes various embodiments according to the principle of the present invention.

[0087]

As described above, according to the present invention,
The synchronous pattern detection circuit does not require high-speed operation, and has an effect that one circuit can cope with the phases of all bytes. Further, according to the present invention, there is an effect that the synchronization time is greatly reduced and the circuit scale and the mounting area of the frame synchronization circuit are reduced. The same effect can be obtained by a configuration in which a means for absorbing a delay in the synchronous pattern detection circuit is provided.

Further, according to the present invention, since the synchronization processing is realized at the transmission speed of the received signal, a buffer for preventing data loss due to a delay in the synchronization processing is unnecessary even in the case of packet synchronization. According to the present invention, there is an effect that the synchronization protection time is reduced even in the case of frame synchronization.

Further, according to the present invention, it is possible to easily synchronize with a desired byte synchronization signal, and a buffer for adjusting the phase is not required even when byte-synchronized parallel outputs are multiplexed. . For this reason, a reduction in the circuit scale, a reduction in the size of the device, and a reduction in cost are achieved.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of a frame synchronization circuit according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the frame synchronization circuit according to the present invention.

FIG. 3 is a block diagram showing a configuration of a byte multiplexing device using a frame synchronization circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a byte multiplexing device using a frame synchronization circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram (in the case of frame synchronization) showing a byte multiplexing device using a frame synchronization circuit according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional frame synchronization circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Shift register 1-a 1st shift register 1-b 3rd shift register 2 2nd shift register 3 Synchronous pattern detection circuit 4 Transmission signal 5 2 Input switch 6-1 to 6-8 1st to 8th Parallel signal output gate 7-1 to 7-8 First to eighth branch output AND gates 8 Byte synchronization signal 9 Parallel output selection gate 10 DF / F array 11 Byte-synchronized parallel output 12 Synchronization protection circuit 13-1 １３13-8 1st to 8th parallel-serial conversion unit 14 byte multiplexing unit 15 parallel output multiplexed by 15 bytes 16-1 to 16-5 1st to 5th DF / F 17-1 to 17-8 1st To 8 parallel outputs 18 selector 19 selector control circuit 21 transmission signal input terminal 22 serial-parallel conversion unit 23 delay unit 24 synchronization pattern detection circuit 25 phase selection unit 25a exclusive control unit 25b logic gate 6 buffer

Claims (3)

(57) [Claims] 1. A frame synchronization apparatus for synchronizing a frame or a packet composed of a predetermined number of bits (= n) as one byte and based on a byte, which is driven by a transmission synchronization signal (2n-1) or more Of flip-flops connected in a cascade configuration, and a set of n consecutive flip-flops of the flip-flops as one set, and outputs n sets of parallel signals shifted by one time slot. And a selector for selecting one of the n sets of parallel signals, and a parallel output of n consecutive flip-flops of the shift register, and a bit of a synchronization byte included in a frame or a packet. A synchronous pattern detection circuit for detecting a pattern, and the n sets of parallel signals based on the output timing of the synchronous pattern detection circuit. A selector control circuit for controlling the selector to select a parallel signal synchronized with a byte synchronization signal having a predetermined phase; and n flip-flops driven by the byte synchronization signal connected in cascade. And a second shift register for synchronizing a time slot of the parallel signal selected by the selector with a byte synchronization signal. 2. The method according to claim 1, wherein the first shift register is provided with the (2n)
-1) In addition to the flip-flops, the flip-flop further includes flip-flops of a number corresponding to a delay of a predetermined time slot generated in the synchronous pattern detection circuit, and is earlier by a predetermined time slot than outputting the parallel signal. 2. The frame synchronization circuit according to claim 1, wherein a parallel signal is output to said synchronization pattern detection circuit. 3. A synchronous protection circuit for checking the periodicity of a detection signal output from the synchronous pattern detecting circuit is inserted between the synchronous pattern detecting circuit and one input terminal of the selector. Item 2. The frame synchronization circuit according to Item 1.