JPH08172452A - Packet phase synchronizing circuit - Google Patents

Abstract

PURPOSE: To reduce a capacity and delay of a memory to be used for phase synchronization and to improve the performance of a communication equipment by performing a phase synchronization for every packet and inserting a specified fixed length packet between the packets at the time of processing the packets. CONSTITUTION: A writing control circuit 102 takes out the packets of a payload area and successively writes the packets in a first in/first out memory (FIFO) 101. A reading control circuit 103 takes out and reads each line phase synchronization for every packet of the packets stored within the memory 101. At the time of a packet reading, overhead is eliminated and phase synchronizations are performed for plural first fixed length packets by a packet unit. A uniform length second fixed length packet is inserted, and first and second fixed length packets are outputted in conformity with the phase and the signal format within a communication equipment. This second fixed length packet can be used for the transmission of control maintenance information and becomes effective for improving the performance of the communication equipment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an interface section between a communication device for processing time division multiplex communication information using fixed length packets and a transmission line, and particularly to a signal of a transmission format including a transmission overhead. And a configuration of a packet phase synchronization circuit suitable for performing phase processing of fixed length packets.

[0002]

2. Description of the Related Art Conventionally, a phase synchronization method for achieving phase synchronization between a transmission line and a switch is known as "Digital Exchange", published by The Institute of Electronics, Communication and Information Engineers (March 15, 1986, Corona Co.). The system is described in the section of "PP64-65" (2) Phase synchronization ". In this example, the head of the frame is identified by a frame aligner (phase synchronization memory) provided for each highway, pulse trains are sequentially written in the phase synchronization memory, and reading is performed by all highway frame phase synchronization.

[0003]

The above prior art has a transmission format composed of a transmission overhead area carrying a control signal for time division multiplex transmission and a payload area carrying information, which are periodically arranged in a frame. In the transmission path in which fixed-length packets are packet-multiplexed and accommodated in the payload area, it is necessary to perform phase synchronization on a frame-by-frame basis also when the packet phase is synchronized. In that case, there is a problem that the phase synchronization memory needs a capacity to store a transmission signal for one frame, and the delay due to this is large.

An object of the present invention is to perform phase synchronization for each packet, reduce the capacity of the memory used for phase synchronization, and
The purpose is to reduce the delay due to phase synchronization. further,
Phase synchronization circuit that extracts packets by removing transmission overhead, performs phase synchronization for all packets included in a frame, and processes the packets at the speed required to reliably transmit all packets It is an object of the present invention to provide a phase locked loop circuit having an economical structure. Further, by inserting a specific bit pattern or a signal between packets or in a packet during packet processing, an input / output signal speed is adjusted to provide a phase-locked circuit having an economical structure, and the phase-locked circuit is included. (EN) It is possible to economically provide a phase locked loop circuit that inserts information that is effective for control and maintenance of a communication device and that is effective for improving the performance of the communication device with a simple configuration.

[0005]

According to the present invention, there is provided a buffer memory for storing fixed-length packets, and a write control circuit for controlling writing of packets to the buffer memory.
A read control circuit for reading the packet from the buffer memory while phase-synchronizing is provided, and the packet is read from the buffer memory at a transmission speed necessary for transmitting all the packets on the input line.

Further, according to the present invention, a predetermined bit pattern is inserted at the time of reading a packet from the buffer memory, and the packet is read at the same speed as the transmission speed of the input line or at the transmission speed necessary for transmitting all packets.

Further, according to the present invention, the above-mentioned predetermined bit pattern is appropriately inserted at the same cycle and length as the transmission overhead area, or the same as the area where the packet does not exist in the payload area. Packets are read out from the buffer memory at the same transmission speed as the input line or at the transmission speed necessary for transmitting all the packets, by appropriately inserting the period and the length.

Further, according to the present invention, the packet length is an integral part of the sum of the length of the transmission overhead area inserted within a period of an integral multiple of the transmission overhead cycle and the length of the area in which no packet exists in the payload area. Select 1 so that when reading packets from the buffer memory, empty packets are inserted periodically or at appropriate intervals, and at the same transmission speed as the input line or at the transmission speed required to transmit all packets. read out.

[0009]

The write control circuit takes out the packets in the payload area and sequentially writes them in the buffer memory. The read control circuit reads out the packets accumulated in the buffer by synchronizing each line with each packet. When reading packets from the buffer, the read speed is set to the speed required for transmission of all packets on the input line, and only fixed-length packets are read on the read line, or a bit pattern that is periodically or appropriately predetermined is used. Insert and
By reading at the same speed as the input line or at the speed necessary for transmitting all packets, the length of the transmission overhead area and the payload area that are inserted within the period that is an integral multiple of the cycle of the transmission overhead area Is an integer fraction of the sum of the lengths of the areas where there are no packets
, And insert empty packets periodically or at appropriate intervals, and make only fixed-length packets on the read line at the same speed as the input line transmission speed or at the speed required to transmit all packets. Thus, packet phase synchronization is achieved.

As described above, since it is not necessary to perform phase synchronization on a frame-by-frame basis, the capacity of the buffer memory used for phase synchronization is only sufficient for absorbing phase fluctuations due to transmission overhead and for performing phase synchronization on a packet basis. It ’s going to be better and you do n’t have to store all the frames,
It is possible to reduce it. Further, since the time accumulated in the buffer memory becomes short, the packet delay time due to the phase synchronization becomes short. In addition, an economical phase synchronization circuit can be realized because the number of clock generation circuits can be reduced and the clock generation circuit can be realized with a simple configuration. Further, since the bit pattern and the empty packet can be used for transmitting the control maintenance information, the phase synchronization circuit effective for improving the performance of the communication device can be realized with a simple configuration.

[0011]

Embodiments of the present invention will be described below.

First, an example of a transmission format of a signal input to the packet phase synchronizing circuit according to the present invention will be described with reference to FIG. FIG. 12 shows a frame structure for one frame of an input signal, where OH1 to OHP are transmission overhead areas for carrying control signals for time division multiplexing transmission which are periodically arranged, and one transmission overhead area. Is L bytes long. An area excluding the transmission overheads OH1 to OHP is a payload area that carries information, and the length of the area is O × P bytes per frame. _{P 'n-6 ~P' n} , P1~P n-6 is the packet of fixed length which are packet multiplexed accommodated in the payload area, the length of one packet is M bytes. E is an empty area generated when the length of the payload area is not an integral multiple of the packet length, and has a length of N bytes.

The head of the frame shown in FIG. 12 is a transmission overhead OH1, and the end thereof is P _n-6 . However, a part after P _n-6 is shifted to the next frame. The transmission overheads OH1 to OHP are arranged in the frame at a cycle of L + O bytes. Therefore, as seen in the packet P3 and the like, a transmission overhead may enter in the middle of the packet. One frame and one payload area do not always match, as shown in FIG.
Beginning when the payload area of a packet P1, the packet _{P 'n-6 ~P' n} , empty area E is the previous payload area. Information indicating the position of the beginning of the payload area and the position of the empty area is included in the transmission overhead OH1.

Next, an embodiment of the packet phase synchronization circuit according to the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of a packet phase synchronization circuit. Reference numeral 101 is a first-in first-out memory (hereinafter referred to as a FIFO) used for storing packets and capable of writing and reading independently, and 102 on a payload. FI of packet
Reference numeral 103 is a write control circuit that controls writing to the FO 101, 103 is a read control circuit that reads out packets in phase synchronization from the FIFO 101, 104 is an input line, 105 is an output line, 106 is a frame signal line, 1
Reference numerals 07 and 111 are clock signal lines, 108 is a write control line, 109 is a read control line, and 110 is a start signal line for the read control circuit.

The operation of this embodiment will be described below. The input transmission signal transmitted through the input line 104 has the same transmission format as that shown in FIG. The packets included in the input transmission signal are sequentially FIFO
101 is written. The write control is performed by the write control circuit 102 for a transmission line clock CK1 extracted from a frame signal F created by a transmission line interface unit (not shown) and an input transmission signal, and for transmission at the beginning of a frame of the input transmission signal. The position of the input packet is detected from the information indicating the start position of the payload area and the position of the empty area included in the overhead, and the write clock is sent to the FIFO 101 via the write control line 108 only while the packet arrives. It is done by doing.
On the other hand, the packet read control from the FIFO 101 is performed by creating the read clock by the synchronization station clock CK2 having the same frequency as the clock CK1 or the frequency required for transmission of all packets and the start signal S5 output from the write control circuit 102 at the time of start. Read control line 109
It is performed by sending the data to the FIFO 101 via the.

The structure and operation of the write control circuit 102 will be described in more detail with reference to FIGS. FIG. 2 is a block diagram of the write control circuit 102. Reference numeral 112 shows a signal indicating the head position of the payload area and the position of the empty area included in the transmission overhead at the head of the frame of the input transmission signal, which is read according to the frame signal F. A pointer reading circuit for sending the result to the pointer signal line 117, and 113 is a sky area detection signal S1 indicating a sky area E in the payload from the pointer information from the pointer signal line 117, the frame signal F and the transmission line clock CK1. And a payload position detection signal S3 indicating the beginning of the payload
Is a payload position detection counter for transmitting the signal to the empty area detection signal line 118 and the payload position detection signal line 120, and 114 detects an overhead position from the frame signal F and the transmission path clock CK1 to detect an overhead detection signal S2. The overhead detection signal line 11
It is an overhead cycle counter that outputs to 9
Reference numeral 5 is a set / reset type flip-flop for generating a start signal of the read control circuit, and 116 is a FIFO.
An AND gate for controlling the gate of the write clock 101.

FIG. 3 is a time chart for explaining an operation example of the write control circuit 102. OH1 and OH2 in the input transmission signal are transmission overheads, P'n _-2 .
P _'n, P1 to P5, the fixed-length packets, E is shows a payload area empty region, is identical to that shown in FIG. 12. S4 is a write clock sent to the write control line 108, and the hatched portion indicates that the clock is sent.

Next, the write control circuit 102 will be described with reference to FIG.
Will be described. FIG. 3 shows the operation at the time of activation. First, when the frame signal F is input, the pointer reading circuit 112 is activated and a signal indicating the head position of the payload area and the position of the empty area is sent to the payload position detection counter 113. Send to. Payload position detection counter 113
Detects the empty area and the payload area by counting the transmission path clock CK1 based on the signal, and detects the empty area detection signal S1 and the payload head position detection signal S3.
Is sent. Then, the set / reset type flip-flop 115 is set by the activation signal S3, and as a result, controls the AND gate 116, and the write clock S4.
Via the write control line 108 to the FIFO shown in FIG.
101, and writing is started from the packet P1. Thereafter, the write clock S4 is controlled when the AND gate 116 is controlled by the empty area detection signal S1 and the overhead detection signal S2 and is stopped when the transmission overhead and the empty area arrive, so that only the packet portion is FI.
Written to FO101.

Next, the configuration and operation of the read control circuit 103 will be described in more detail with reference to FIGS. FIG. 4 is a configuration diagram of the read control circuit 103. Reference numeral 121 frequency-converts the synchronization station clock CK2 to a speed necessary and sufficient for transmitting all packets in the payload area to create a conversion clock CK2 '. Frequency conversion circuit, 12
2 is a delay in which the start signal S5 sent from the write control circuit 102 is delayed by the length of the transmission overhead area by using the synchronization station clock CK2 to create a read enable signal S6, which is sent to the read enable signal line 127. A circuit 123 is a packet cycle counter that sends out a packet cycle signal S7 having a pulse generated for each packet cycle by counting the clock CK2 'for exchange to the packet cycle signal line 128.
Is an edge-triggered flip-flop, 125
Is an AND gate that controls the output of the read clock S8, 126 is a clock signal line, and 129 is a read clock control line. FIG. 5 shows the read control circuit 10.
3 is a time chart for explaining the operation of No. 3, and the input transmission signal is the same as that shown in FIG. Figure 5
Shows an operation example at the time of starting. First, the starting signal S
When 5 is input, a read enable signal S6 delayed by the length of the transmission overhead area is generated by the delay circuit 122 and input to the edge trigger type flip-flop 124. Then, the packet cycle signal S7 generated next sets the edge trigger type flip-flop 124, and as a result, the AND gate 125 is controlled and the read clock S8 is transmitted through the read control line 109 to the FI of FIG.
The packet is sent to the FO 101 and the reading of the packet is started. That is, since there is a minimum length of the overhead area for transmission from the start of writing the packet to the start of reading, the speed of reading the packet is slower than the speed of writing and the overhead of the transmission is almost equal during the cycle of the overhead area for the transmission. Since packets are accumulated in excess of the area, even if the transmission overhead area has arrived at the input line and the packet is not written, the FIFO
It is possible to continuously read out the packets stored in 101 without disappearing. Therefore, the output line 105 of the packet phase synchronizing circuit of this embodiment
As shown in the output transmission signal of FIG.
The transmission overhead area and the empty area E on 4 are removed, and a signal in which fixed length packets are continuous is transmitted, and the phase of the packet is synchronized with the packet cycle signal S7.

In the present embodiment, when the packet phase synchronization of a plurality of input lines is to be achieved, the frequency conversion circuit 121 and the packet cycle counter 123 of the read control circuit 103.
Is common to all input lines, it is possible to synchronize the packet phase of all input lines.

According to the present embodiment, F for accumulating packets
The capacity of the IFO 101 is required to be L bytes in order to absorb the phase fluctuation due to the transmission overhead area, N bytes in order to fill the empty area E, and M bytes in order to match the phase for each packet, that is, L + M + N bytes in total. This is sufficiently smaller than (L + O) × P bytes (frame length) required for frame synchronization. Therefore, small capacity FI
FO (buffer memory) enables packet phase synchronization. This also reduces the time for packets to be stored in the FIFO and reduces the delay due to phase synchronization.

Next, another embodiment will be described with reference to FIGS. FIG. 6 is a block diagram of another embodiment of the packet phase synchronizing circuit according to the present invention, in which 201 is a FIFO, 2
02 is a write control circuit, 203 is a read control circuit,
Reference numeral 204 is an input circuit, 205 is an output line, 206 is a frame signal line, 207 and 211 are clock signal lines, 208 is a write control line, 209 is a read control line, 210 is an activation signal line, and 212 is predetermined. 213 is a bit pattern generation circuit for generating a bit pattern.
Is a FIFO 201 and a bit pattern generation circuit 212.
Is a selector for selecting the output of the
An output line 215 is a bit pattern generation circuit output line, and a reference numeral 216 is a bit pattern insertion signal line. The above FIFO 201 and write control circuit 202 operate in the same manner as in the previous embodiment. The read control circuit 230 of this embodiment
Controls the packet read by sending the read clock to the FIFO 201, and controls the bit pattern generation circuit 212 and the selector 213 to insert a predetermined bit pattern into the output transmission signal.

The configuration and operation of the read control circuit 203 will be described in detail below with reference to FIGS. 7 and 8. 7 is a block diagram of the read control circuit 203, and 217 is a delay circuit that operates in the same manner as the delay circuit 122 of the previous embodiment.
Reference numeral 219 denotes a packet cycle counter 219 which uses the synchronization station clock CK2 to generate a packet cycle signal S12 having a pulse generated in each packet cycle by counting the clock CK2 and sends it to the packet cycle signal line 223.
Sends to the bit pattern insertion signal line 216 a bit pattern insertion signal S9 that matches the cycle and length of the transmission overhead area in the input transmission signal transmitted through the input line 204 and the cycle and length of the empty area E on the payload area. A bit pattern insertion counter, 220 is an edge trigger type flip-flop, 221 is an AND gate, 222 is a read enable signal line, 22
Reference numeral 3 is a packet cycle signal line, and 224 is a read clock control line. FIG. 8 is a time chart for explaining the operation of the read control circuit 203, and the input transmission signal is the same as that shown in FIG. 5 of the previous embodiment. FIG. 8 shows an operation example at the time of activation. First, when the activation signal S10 is input, the delay circuit 217 creates the read permission signal S11 delayed by the length of the transmission overhead area, and the packet generated next. The edge signal type flip-flop 220 is set by the periodic signal S12, and as a result, the AND gate 221 is controlled to read the read clock S1.
3 is a FIFO 201 of FIG. 6 via the read control line 209.
And the packet reading is started. The bit pattern insertion counter 219 controls the AND gate 221 by the bit pattern insertion signal S9 at every cycle of the transmission overhead area and the cycle of the empty area E, and stops the transmission of the read clock S13, while being shown in FIG. The bit pattern generating circuit 212 and the selector 213 are controlled to output a predetermined bit pattern to the output line 205. The bit pattern insertion signal S9 is also input to the packet cycle counter 218, and the packet cycle counter 218 stops its operation while the bit pattern is being inserted. In that case, the packet generation period is lengthened by the bit pattern insertion period. According to the above, there is a minimum length of the overhead area for transmission from the start of writing the packet to the start of reading, and the cycle and length of the overhead area for transmission and the empty area E in the output transmission signal.
Since a predetermined bit pattern having the same period and length is inserted, even if the packet is not written due to the transmission overhead arriving at the input line, the FIFO
The packets stored in 201 do not disappear, and the packets can be read continuously during the period excluding the bit pattern transmission period. As described above, in the output line 205 of the packet phase synchronizing circuit of the present embodiment, the transmission overhead area and the empty area E on the input line 204 as shown in the output transmission signal of FIG. 8 are predetermined bit patterns (BP1, The signal inserted in place of BP2, BP3) is transmitted and the phase of the packet is synchronized with the packet cycle signal S11. The phase relationship between the bit patterns (BP1, BP2) corresponding to the transmission overhead, the bit pattern (BP3) corresponding to the empty area E, and the packets ( _{Pn-4 to} P4) may be arbitrary.

Also in this embodiment, the read control circuit 203 is used when packet phase synchronization of a plurality of input lines is to be achieved.
If the packet cycle counter 218 and the bit pattern insertion counter are shared, the packet phase synchronization of all input lines can be achieved.

According to the present embodiment, F for accumulating packets
The capacity of the IFO 201 is L bytes to absorb the phase fluctuation due to the transmission overhead, N bytes to the empty area E, M bytes to adjust the phase for each packet, and when the bit pattern corresponding to the transmission overhead area is inserted. In order to increase the packet accumulation amount of L, a total of 2 · L + M + N bytes are required. This is sufficiently smaller than (L + O) × P bytes (frame length) required for frame synchronization. Therefore, packet phase synchronization can be achieved with a small capacity FIFO (buffer memory). This also reduces the time for packets to be stored in the FIFO and reduces the delay due to phase synchronization. Further, in the case of this embodiment, the frequency conversion circuit 121 in the previous embodiment is unnecessary. It is also possible to transmit the transmission control signal and the like by using a predetermined bit pattern inserted in the output transmission signal.

Next, still another embodiment will be described with reference to FIGS. When the present invention is implemented, the packet length (M) is inserted into one frame, and the transmission overhead area length (LP) and the empty area length (N) are divided by an integer fraction.
So that FIG. 9 is a block diagram of still another embodiment of the packet phase synchronizing circuit according to the present invention.
FIFO, 302 is a write control circuit, 303 is a read control circuit, 304 is an input line, 305 is an output line, 3
Reference numeral 06 is a frame signal line, 307 and 311 are clock signal lines, 308 is a write control line, 309 is a read control line, 310 is an activation signal line, and 312 is an empty space that does not have transmission information included in a packet of an input transmission signal. An empty packet generation circuit for generating a packet, and 313 is an FIF
A selector for selecting the output of the O301 and the empty packet generation circuit 312, 314 is a FIFO output line, and
Reference numeral 15 is an empty packet generation circuit output line, and 316 is an empty packet insertion signal line. The above-mentioned FIFO 301 and write control circuit 302 operate in the same manner as in the previous two embodiments. The read control circuit 303 of the present embodiment controls the packet read by sending a read clock to the FIFO 301, and controls the empty packet generation circuit 312 and the selector 313 to insert an empty packet into the output transmission signal.

The configuration and operation of the read control circuit 303 will be described in detail below with reference to FIGS. 10 and 11. FIG. 10 is a block diagram of the read control circuit 303. Reference numeral 317 is a read enable signal S16 in which the start signal S15 sent from the write control circuit 302 is delayed by one packet length using the synchronization station clock CK2, and read. A delay circuit 318 is sent to the permission signal line 322, and 318 uses the synchronizing station clock CK2 to count it to create a packet period signal S17 having a pulse generated for each packet period, and to the packet period signal line 323. A packet cycle counter 319 for sending out an empty packet insertion signal S319 generated in a cycle such that the generation period of the empty packet insertion signal S14 that matches the packet length is the sum of the transmission overhead area and the empty area E within one frame. Signal line 316
To the empty packet insertion counter, 220 is an edge-triggered flip-flop, 321 is an AND gate, 322 is a read enable signal line, 323
Is a packet cycle signal line and 324 is a read clock control line. FIG. 11 is a time chart for explaining the operation of the read control circuit 303, and the input transmission signal is the same as in the previous two embodiments. FIG. 11 shows an operation example at the time of start-up. First, when the start-up signal S15 is input, the delay circuit 31
The read enable signal S delayed by one packet length by 7
16 are generated, and the edge-triggered flip-flop 320 is generated by the packet period signal S17 generated next.
Is set, and as a result, the AND gate 321 is controlled, the read clock S18 is sent to the FIFO 301 of FIG. 9 via the read control line 309, and the reading of the packet is started. The empty packet insertion counter 319 controls the AND gate 321 by the empty packet insertion signal S14 in each cycle to stop the transmission of the read clock S18, while the empty packet generation circuit 31 shown in FIG.
2 and the selector 313 are controlled to send an empty packet to the output line 305. The empty packet insertion signal S14 is also input to the packet cycle counter 318, and the operation of the packet cycle counter 318 is stopped while the empty packet is being inserted. In that case, the packet generation period becomes longer by the empty packet insertion period. As described above, since there is at least one packet length from the start of writing a packet to the start of reading and empty packets are periodically inserted in the output transmission signal, transmission overhead arrives at the input line. Even if the packet is not written due to
The packets accumulated in O301 are not lost, and the packets can be read continuously during the period excluding the empty packet transmission period. As described above, the transmission overhead area and the empty area E on the input line 304 are inserted into the output line 305 of the packet phase locked loop circuit of the present embodiment, as shown in the output transmission signal of FIG. Then, the phase of the packet is synchronized with the packet cycle signal S17. In addition, the packet length is set to be an integral fraction of the sum of the lengths of the transmission overhead area and the empty area E inserted in one frame, so that the empty packet is divided into an integral fraction of the frame period.
It is possible to regularly generate the empty packet insertion counter 319 and the circuit configuration of the empty packet insertion counter 319 can be simplified.

Also in this embodiment, the read control circuit 303 is used when packet phase synchronization of a plurality of input lines is to be achieved.
If the packet cycle counter 318 and the empty packet insertion counter are shared, the packet phase synchronization of all input lines can be achieved.

According to the present embodiment, F for accumulating packets
The capacity of the IFO 301 is M bytes to absorb phase fluctuations due to transmission overhead, M bytes to match the phase of each packet, and M bytes to increase the packet storage amount when empty packets are inserted. M bytes are required. This is necessary for frame synchronization (L +
One minute smaller than (O) × P bytes (frame length). Therefore, packet phase synchronization can be achieved with a small capacity FIFO (buffer memory). This also reduces the time for packets to be stored in the FIFO and reduces the delay due to phase synchronization. Further, in the case of this embodiment, the frequency conversion circuit 121 in the embodiment shown in FIG. 4 is unnecessary. Further, it becomes possible to transmit the transmission control signal and the like by using the empty packet inserted in the output transmission signal.

[0030]

According to the present invention, when packet phase synchronization is performed, the capacity of the buffer memory for storing packets can be small, and the packet delay due to phase synchronization can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a write control circuit in FIG.

FIG. 3 is a time chart explaining the operation of the write control circuit of FIG.

FIG. 4 is a configuration diagram of a read control circuit in FIG.

5 is a time chart explaining the operation of the read control circuit of FIG.

FIG. 6 is a configuration diagram showing another embodiment of the present invention.

7 is a configuration diagram of a read control circuit in FIG.

8 is a time chart explaining the operation of the read control circuit of FIG.

FIG. 9 is a configuration diagram showing still another embodiment.

10 is a configuration diagram of a read control circuit in FIG.

11 is a time chart illustrating the read control circuit of FIG.

FIG. 12 is a diagram for explaining a transmission format applied to the packet phase synchronization circuit of the present invention.

[Explanation of symbols]

101, 201, 301 ... First-in first-out memory, 102, 202, 302 ... Write control circuit, 103, 203, 303 Read control circuit, 104, 204, 304 ... Input line, 105, 205, 305 ... Output line, 106, 206, 306 ... Frame signal line, 107, 111, 207, 211, 307, 311 ... Clock signal line, 108, 208, 308 ... Write control line, 109, 209, 309 ... Read control line, 110, 210, 310 ... Start-up signal line, 112 ... Pointer reading circuit, 113 ... Payload position detection counter, 114 ... Overhead cycle counter, 115 ... Set / reset type flip-flop, 116 ... AND gate, 117 ... Pointer signal line, 118 ... Empty area detection Signal line, 1 9 ... Overhead detection signal line, 120 ... Payload position detection signal line, 121 ... Frequency conversion circuit, 122, 217, 317 ... Delay circuit, 123, 218, 318 ... Packet period counter, 124, 220, 230 ... Edge trigger type flip-flop 125, 221, 321 ... AND gate, 127, 222, 322 ... Read permission signal line, 128, 223, 323 ... Packet period signal line, 126 ... Clock signal line, 129, 224, 324 ... Read clock control line, 212 ... Bit pattern generation circuit, 312 ... Empty packet generation circuit, 212, 312 ... Selector, 214, 314 ... FIFO output line, 215 ... Bit pattern generation circuit output line, 315 ... Empty packet generation circuit output line, 216 ... Bit pattern Insertion signal line, 316 ... Empty packet insertion signal line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kaneichi Otsuki, 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi Ltd. Totsuka factory

Claims (5)

[Claims] 1. A time division multiplexing transmission format in which an overhead including a control signal for transmission and a payload for transmitting an information signal are periodically arranged, and a plurality of first fixed-length packets are packetized in the payload. In the packet phase synchronization circuit of the communication device, which receives a multiplexed input signal and outputs the plurality of first fixed-length packets according to a signal format in the communication device, removing the overhead, A plurality of first fixed-length packets are phase-synchronized in fixed-length packet units, a second fixed-length packet having the same length as the first fixed-length packet is inserted, and a phase and a signal format in the communication device are set. A cell phase synchronization circuit which outputs the plurality of first fixed-length packets and second fixed-length packets in total. 2. The packet phase synchronization circuit includes a buffer memory for accumulating the plurality of first fixed-length packets,
A write control circuit for writing the first fixed-length packet of the payload into the buffer memory, a read control circuit for reading the first fixed-length packet from the buffer memory in accordance with the in-device phase, and the second 2. The packet phase synchronization circuit according to claim 1, further comprising a fixed length packet generation circuit for generating the fixed length packet and the selection circuit for selecting an output of the buffer memory and an output of the fixed length packet generation circuit. 3. The packet according to claim 1, wherein the second fixed-length packet contains information corresponding to any one of monitoring, maintenance, operation, and control of the communication device or information combining them. Phase synchronization circuit. 4. The packet phase synchronization circuit further comprises a clock frequency conversion circuit or a clock input circuit, and operates the read control circuit and the fixed-length packet generation circuit by an output clock of the clock conversion circuit or the clock input circuit. The output of the packet phase synchronization circuit is converted from the signal speed of the input signal to the signal speed of the output signal, and then the plurality of first fixed-length packets and the second fixed-length packets are output.
4. The packet phase synchronization circuit according to claim 2, wherein the fixed length packet is output. 5. The packet phase synchronization circuit, wherein the length of the first fixed length packet and the length of the second fixed length packet are inserted within a period of an integral multiple of the overhead cycle, and the length of the overhead and the payload. Above, an integer fraction of the sum of the lengths of the empty portions where the first cell does not exist
Using the fixed length packet described above, the second fixed length packet is inserted after the overhead is removed, and the first fixed length packet and the second fixed length packet are inserted at the same rate as the transmission rate of the input signal of the packet phase synchronization circuit. 4. The packet phase synchronization circuit according to claim 1, which outputs fixed length packets.