JP2962213B2 - Test circuit and test method for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a test circuit and a test method for a semiconductor integrated circuit, and more particularly to a test circuit and a test method for a semiconductor integrated circuit performed by using an LSI tester.

[0002]

2. Description of the Related Art Today's CMOS semiconductor integrated circuits (hereinafter referred to as L
With the advance of SI) technology, the operation speed of a logic circuit of this type of LSI has also been greatly increased, and many products that exceed the operation speed performance of a general LSI tester have been produced. Therefore, it is difficult to use a general LSI tester to test the internal circuit of such an LSI that operates at high speed at an actual operating frequency and to select non-defective products. The reason is that in addition to the performance of the tester itself,
When the test waveform is supplied to the LSI under test and the test result waveform output from the LSI under test is observed, the test signal is distorted due to the terminal of the tester or the capacity of the mounting board of the LSI under test.

That is, the LSI under test is
When a test signal is input, the test signal may be skewed due to the influence of the tester input terminal or the capacity of the LSI mounting board, and the test signal applied to the input terminal of the LSI under test may be delayed or the input between a plurality of input terminals may be delayed. Due to the change in the signal timing, the expected test signal cannot be input, and when the test result signal output from the LSI is observed by a tester, the expected skew of the test result signal causes a problem. This is because it cannot be observed at the strobe position.

For this reason, in the conventional method for testing a semiconductor integrated circuit, performance verification at an actual operating frequency is performed only by computer simulation, and selection of an LSI is performed by confirming a logical operation at a low frequency operable by an LSI tester. This was generally done by

[0005]

The above-described conventional test circuit and test method for a semiconductor integrated circuit are described in detail below.
When the operating frequency of I exceeds the operating performance of the LSI tester, in addition to the performance of the LSI tester itself, a test waveform is supplied from the LSI tester to the LSI, and the test result waveform output from the LSI under test is observed. There is a drawback that it is difficult to select the LSI under test at the operating frequency due to the distortion of the test signal due to the terminal of the LSI under test or the capacity of the mounting board for the LSI under test.

[0006]

A test circuit for a semiconductor integrated circuit according to the present invention supplies a test signal pattern in a predetermined format to a circuit to be verified, and the circuit to be verified responds to the supply of the test signal pattern. In a test circuit of a semiconductor integrated circuit for testing the operation of the circuit under test by measuring the output test result signal, a predetermined
Generating a first clock signal having a first frequency of
The first clock signal is supplied to the verification circuit,
A second clock signal of an integer fraction of the first frequency
LSI test for generating and generating the test signal pattern
A clock generation circuit for supplying for synchronization of the apparatus, the second
And of converting the test signal pattern consisting of parallel data signals in synchronization with the clock signal number predetermined bits supplied in series test pattern signal composed of serial data signal synchronized with the first clock signal An input pattern conversion circuit to be supplied to the circuit to be verified, and the first circuit having the circuit to be verified responding to the supply of the serial test pattern signal .
Converts the serial test result signal outputted in synchronization with the lock signal to the test result signal consisting of parallel data signal before number system bits, and the output pattern conversion circuit for outputting in synchronization with the second clock signal, wherein First clock signal and test
Before supply of test enable signal for switchover control
The clock generation circuit, the input pattern conversion circuit,
Control for controlling each of the output pattern conversion circuits
And a control circuit for outputting a rule signal .

A method for testing a semiconductor integrated circuit according to the present invention comprises:
A semiconductor for testing the operation of the circuit under test by supplying a test signal pattern in a predetermined format to the circuit under test and measuring a test result signal output from the circuit under test in response to the supply of the test signal pattern In a test method of an integrated circuit, a predetermined first frequency from an input clock signal is
Generates a first clock signal and supplies it to the circuit to be verified
Then, the frequency of the first clock signal is divided to divide the frequency of the first clock signal.
Generating a second clock signal that is an integer fraction of the number
For synchronizing LSI test equipment that generates test signal patterns
Supplying receives in synchronization with the supply to the second clock signal
The supply to the circuit to be verified with the test signal pattern consisting of parallel data signals of the number of bits determined in advance has been converted to a serial test pattern signal composed of serial data signal synchronized with the first clock signal, the object A verification circuit is responsive to the supply of the serial test pattern signal to provide the first clock signal.
Reconverted to the test result signal consisting of parallel data signal before number system bit serial test result signal outputted in synchronization with the No.
And outputting in synchronization with the second clock signal .

[0008]

FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1, a test circuit for a semiconductor integrated circuit according to this embodiment shown in FIG. Is a test circuit for performing conversion by using a test rate of a frequency of 1/4 to a use frequency and performing verification, and an input pattern conversion circuit 1 for performing parallel / serial conversion of an input pattern.
A circuit under test 2, which is a circuit of an LSI under test, an output pattern conversion circuit 3 for converting an output pattern from serial to parallel, and a clock CL corresponding to a test frequency corresponding to a test frequency.
A clock generation circuit 4 for converting the clock CLKB for the K and LSI testers, a control circuit 5 for outputting a control signal C for controlling the input pattern conversion circuit 1, the output pattern conversion circuit 3, and the clock generation circuit 4, respectively; Is provided.

FIG. 2 is a block diagram showing the configuration of the input pattern conversion circuit 1. Referring to FIG.
Means that the write enable signal WE is in the enable state
The register 11 for taking in and temporarily holding the input pattern signal AP input in synchronization with the clock CLKB to generate the signal BP, and the load enable signal LD being enabled
, The signal BP is loaded from the register 11 and the clock C
A shift register 12 that shifts in response to LK to output a serial data signal SP, and a test enable signal TEN
Switching between the actual operation and the test operation in response to the supply of the output signal IP corresponding to the serial data signal SP during the test.
And a selector 13 for selecting one of the four signals W, X, Y, and Z.

Block configuration of output pattern conversion circuit 3
Referring to FIG. 3 shown in FIG.
Is selected by the select signal ST.Clock CLK frequency
Output pattern supplied from the circuit under test 2 at (m × 4) Hz
Select one of R, S, T and U of the
Supply as column verification data signal CP to shift register 32
Selector 31 and a shift enable / load
In response to the inactive signal SFT / LDB
The serial verification data signal CP is loaded and shifted by 3 bits.
Register in response to the activation of the write enable signal WE.
To load a 4-bit parallel data signal DP into the
Shift register 32 and parallel data DPCaptureHold
Signal EPGenerateRegister 33 and test enable
The signal EP is verified in response to the enable of the signal TEN.
And a selector 34 for outputting the data as a data signal OP.

Next, the operation of the present embodiment will be described with reference to FIGS. 1, 2 and 3. First, the clock generation circuit 4 determines that the frequency of the supplied input clock CLKA is When the operating frequency is the same as that of the input clock CLKA, the clock is output as the clock CLK at the frequency of the input clock CLKA.
Is divided by 4 to generate a clock CLKB. Further, when the clock CLK is generated by multiplying the frequency of the input clock CLKA, the clock CLK is divided by 4 to generate the clock CLKB. The clock CLK is supplied to each of the input pattern conversion circuit 1, the circuit under test 2, the output pattern conversion circuit 3, and the control circuit 5. The clock CLKB is supplied for adjusting the timing of the LSI tester. For convenience of explanation, in the following description, the clock C
The frequency of the LKB is set to mHz, and the frequency of the clock CLK is set to (m × 4) Hz.

The control circuit 5 supplies to the input pattern conversion circuit 1 in response to the supply of the clock CLK and the test enable signal TEN for test switching control.
A 17-bit control signal C including a bit control signal CI and a 6-bit control signal CO supplied to the output pattern conversion circuit 1 is output.

The operation of the input pattern conversion circuit 1 will be described with reference to FIG.
Is the frequency of the 4-bit clock CLKB from the LSI tester.
When receiving the input pattern signal AP having a wave number of mHz,
The pulse C1 of the clock CLK in which the write enable signal WE is enabled (hereinafter, the clock C1 and the like).
To capture and store the signal AP. Next, the shift register 12 loads the 4-bit data signal BP corresponding to the signal AP from the register 11 with the clock C2 in which the load enable signal LD is enabled, and outputs the clocks C3 and C3 in which the load enable signal LD is disabled.
The data signals BP are sequentially shifted at a frequency (m × 4) Hz at 4 and C5, output as serial data SP, and supplied to the selector 13. The selector 13 switches between the actual operation and the test operation in response to the supply of the test enable signal TEN, and outputs the output signal IP corresponding to the serial data signal SP to be supplied to the circuit under test 2 during the test operation by the converted data select signal SS. Signals W, X, Y,
One of Z, for example, W is selected. The other three signals not selected by the conversion data select signal SS,
Here, a signal having a frequency of mHz is supplied using the data set signal DS as X, Y, and Z.

As described above, the input pattern conversion circuit 1 performs the parallel / serial conversion of the input pattern signal AP, and
To supply a serial data signal IP having a frequency (m × 4) Hz. The output pattern signal PP of the verification result output through the circuit under test 2 is supplied to the output pattern conversion circuit 3. The output pattern conversion circuit 3 performs serial-parallel conversion on the input output pattern signal PP and outputs again as a 4-bit parallel output signal OP having a frequency of mHz.

The operation of the output pattern conversion circuit 3 will be described with reference to FIG. 5 which is a timing chart.
T, R, S, and R of the output pattern signal PP supplied from the verification circuit at the frequency (m × 4) Hz of the clock CLKB .
One of T and U, for example, R is selected and supplied to the shift register 32 as a serial verification data signal CP. The shift register 32 loads the serial verification data signal CP when the shift enable / load disable signal SFT / LDB is inactive. When the shift register 32 is shifted by 3 bits, that is, when the clock D is the pulse D5 (clock D5), the write enable signal is written. WE becomes active and loads the register 33 as a 4-bit parallel data signal DP corresponding to the data signal CP. Register 33 takes the coercive
Supplies were lifting the data signal DP corresponding data signal EP to the selector 34. The selector 34 controls the clock CLKB when the test enable signal TEN is enabled.
And outputs a signal EP from the register 33 as a verification data signal OP in synchronization with the data. This signal OP is compared with the expected value. In the normal mode, the selector 34 outputs the output pattern signal PP as it is as the data signal OP.

As described above, the use of the test pattern divided by 4 makes it possible to perform verification by the LSI tester at the same frequency as the actual operation before the division.

[0017]

As described above, the test circuit for a semiconductor integrated circuit and the test method for the same according to the present invention provide an input clock.
A first clock signal of a predetermined first frequency from the clock signal
Is generated and supplied to the circuit under test, and the first clock signal
A second clock having a frequency divided by 1 / n of the first frequency
LSI test that generates signals and generates test signal patterns
A clock generation circuit for supplying for synchronization of winding devices, and supplies a test signal pattern of the parallel data signals of the second clock frequency is converted to a serial test pattern signal of a first clock frequency of n times to the circuit to be verified an input pattern conversion circuit, by an output pattern conversion circuit for converting the serial test result signal of the first clock frequency output to the test result signal of the parallel data signals of the second clock frequency, general LSI tester The effect of using a test pattern of a frequency lower than the actual use frequency of the LSI by using the test pattern, converting the test frequency by serial-parallel conversion of the test pattern, and selecting the LSI at the same frequency as that in the actual use. There is.

Even if the tester terminals and the capacity of the selection board affect the test signal such as skew, LS
Since the input / output signal frequency of the I tester is low, there is a time margin for the strobe position and the phase difference between the signals, and the influence of the skew on the operation of the LSI to be verified is reduced, thereby reducing the causes of this type of tester trouble. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a test circuit for a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of the input pattern conversion circuit of FIG.

FIG. 3 is a block diagram illustrating a configuration of an output pattern conversion circuit of FIG. 1;

FIG. 4 is a time chart illustrating an operation of the input pattern conversion circuit.

FIG. 5 is a time chart illustrating an operation of the output pattern conversion circuit.

[Explanation of symbols]

 Reference Signs List 1 input pattern conversion circuit 2 circuit to be verified 3 output pattern conversion circuit 4 clock generation circuit 5 control circuit 11, 33 register 12, 32 shift register 13, 31, 34 selector

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/28-31/3193 H01L 21/822 H01L 27/04

Claims (3)

(57) [Claims] 1. A test signal pattern in a predetermined format is supplied to a circuit to be verified, and a test result signal output from the circuit under test in response to the supply of the test signal pattern is measured. In a test circuit of a semiconductor integrated circuit for testing an operation, a first clock of a predetermined first frequency is inputted from an input clock signal.
And outputs the signal to the circuit to be verified.
Divided by the integer of the first frequency.
Generating a second clock signal, the test signal pattern
Clock supplied for synchronization of LSI test equipment that generates
And click generating circuits, the serial data signal synchronized with the test signal pattern consisting of parallel data signals of the second number of predetermined bits supplied in synchronization with the clock signal to the first clock signal An input pattern conversion circuit that converts the serial test pattern signal into a serial test pattern signal and supplies the serial test pattern signal to the circuit under test; and the circuit under test outputs in synchronization with the first clock signal in response to the supply of the serial test pattern signal. converting the test result signal comprising a serial test result signal from the parallel data signal before number system bits, the second clock signal
An output pattern conversion circuit for synchronization with an output, said first Tesutoi clock signal and the test switching control
Receiving the enable signal and the clock generation circuit.
The input pattern conversion circuit and the output pattern conversion circuit
A control signal that outputs a control signal for controlling each
A test circuit for a semiconductor integrated circuit, comprising: a troll circuit . 2. The input pattern conversion circuit according to claim 2, wherein
A first register that captures and temporarily holds the test signal pattern supplied in synchronization with the clock signal and outputs a holding test signal; and loads the holding test signal and shifts in synchronization with the first clock signal. A first shift register that generates the serial test signal; and a switch between a test and an actual operation in response to a supply of a test control signal, and selectively supplies the serial test signal to the circuit under test during a test. A second selector, comprising: a first selector, wherein the output pattern conversion circuit selectively inputs one of a plurality of test result output signals supplied from the circuit to be verified as the serial test result signal; A second shift register that loads the serial test result signal and shifts by the number of bits in synchronization with the first clock to generate a parallel test result signal of the number of bits; The parallel test result signal is synchronized with the first clock.
A second register for capturing and holding; and a third selector for switching between a test and an actual operation in response to the supply of the test control signal and outputting the parallel test result signal as the test result signal during the test. 2. The test circuit for a semiconductor integrated circuit according to claim 1, wherein: 3. A test signal pattern in a predetermined format is supplied to a circuit to be verified, and the circuit to be verified measures a test result signal output in response to the supply of the test signal pattern, whereby the circuit to be verified is measured. In a test method of a semiconductor integrated circuit for testing an operation, a first clock having a predetermined first frequency is inputted from an input clock signal.
And outputs the signal to the circuit to be verified.
Divided by the integer of the first frequency.
Generating a second clock signal, the test signal pattern
Supplies for synchronization of the LSI tester for generating down, the said second of said test signal pattern consisting of parallel data signals of the number of bits determined in advance that supplied in synchronization with the clock signal first clock A signal is converted into a serial test pattern signal comprising a serial data signal synchronized with the signal and supplied to the circuit under test, and the circuit under test synchronizes with the first clock signal in response to the supply of the serial test pattern signal. the re-converted to the test result signal comprising a serial test result signal output from the parallel data signal before number system bits Te, the second clock signal
A method for testing a semiconductor integrated circuit, wherein the output is performed in synchronization with the circuit.