JP2874885B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device having a shallow impurity layer and a method for manufacturing the same.

(Prior Art) In recent years, large-scale integrated circuits (LSIs) formed by integrating a large number of transistors, resistors, and the like to achieve an electric circuit and integrating them on one chip have become an important part of computers and communication devices. It is heavily used. Improving the performance of this LSI alone is important for improving the performance of the entire device. This is achieved, for example, by increasing the degree of integration of the LSI.
It is necessary to miniaturize a basic element of SI, for example, a field effect transistor (FET). Therefore, it is required to make the source / drain regions shallow as the gate of the FET is shortened. For example, low-acceleration ion implantation is widely used for forming these regions. 0.1 μm by using this method
It is possible to form a source / drain region having a shallow degree, and it is possible to form a finer and higher performance FET. However, the impurity layer formed only by the ion implantation method has a high resistance and a sheet resistance of 100 Ω / port or more. F
In order to increase the speed of the ET, it is necessary to reduce the sheet resistance of the impurity layer and improve the flow of the drain current. For this, a method of metallizing a part of the impurity layer has been considered, for example, a method called salicide. This is shown in FIG. This method first silicon substrate (1) forms an impurity layer on the region exposed from the field oxide film (2) to (4 ₁₎ (FIG. 4 (a)).

Next to deposit a Co film ₍₇₁₎ to this layer (FIG. 4 (b)).

Over this was heated by a lamp annealing to form a Co silicide film (4 ₂₎ (FIG. 4 (c)).

Thereafter, the unreacted Co (7 ₂₎ is removed by etching (FIG. 4 (d)).

Finally, an insulating film (8) is provided and an opening is formed.
Is formed (FIG. 4 (e)).

When this method is used, for example, a 150 nm thick silicide can be formed, and the sheet resistance can be reduced to 3 to 5 Ω / port.

However, when formed by this method, the interface between the impurity layer (4 ₁ ) and the metal silicide layer (4 ₂ ) has an uneven shape. FIG. 5 is an enlarged view of the region A shown in FIG. 4 (e), and shows the state of this interface. (40) is a metal silicide layer (4 ₂ )
Are convex portions protruding from the P ⁺ -type impurity layer (4 ₁ ) side, and (4 ₁ )
Is the opposite recess. The difference between these irregularities (8) is 500
In some cases, the thickness may be from about 1000 to about 1000 mm, and it is difficult to form a wafer having a thickness of less than 1000 mm using the above-described forming method. In such a semiconductor device, the electric field concentrates on the convex portion (40), and the electric field distribution at the interface loses in-plane uniformity. In such a state, a leak current (42) is generated from the place where the electric field is concentrated to the n-type silicon substrate (1), and the PN junction between the P ⁺ -type impurity layer (4 ₁ ) and the n-type substrate (1) Introduce the destruction of the result.

(Problems to be Solved by the Invention) Although the conventional semiconductor device has a shallow impurity layer of 0.1 μm or less, since the interface between the metal compound layer and the impurity layer has an uneven shape, the concentration of electric charge is here. This causes a problem that the junction between the substrate and the impurity layer is broken.

The present invention has been made in view of the above problems, and has as its first object to provide a semiconductor device in which charge concentration at an interface between a metal compound and an impurity layer is prevented and a leak current is suppressed.

It is a second object of the present invention to provide a method for manufacturing a semiconductor device which can easily form such a semiconductor device.

[Configuration of the invention]

(Means for Solving the Problems) The present invention has been made to achieve the above object.
According to a first aspect of the present invention, there is provided a semiconductor substrate of a first conductivity type, an impurity layer of a second conductivity type selectively provided on the surface of the substrate, and a constituent element and a metal of the impurity layer provided on the surface of the impurity layer. A metal compound layer comprising:
An object of the present invention is to provide a semiconductor device, wherein an interface between the impurity layer and the metal compound layer has unevenness with a step of 100 ° or less.

According to a second aspect of the present invention, a second conductivity type impurity layer is selectively formed on a first conductivity type semiconductor substrate surface, and a metal compound containing a constituent element and a metal of the semiconductor substrate is formed on the impurity layer surface. In the method for manufacturing a semiconductor device including a step of forming, before forming the metal compound, desired ions are implanted into the semiconductor substrate or the impurity layer, so that the semiconductor substrate or the impurity layer is And a method of manufacturing a semiconductor device characterized by making the lattice constant close to the above.

(Function) According to the present invention, when forming a metal compound layer on a semiconductor substrate via a shallow impurity layer, ion implantation is performed in advance on the surface of the substrate before the formation of the shallow impurity layer or the impurity, and the lattice constant is determined. Is approximated to the lattice constant of the metal compound layer. Thus, stress generated between the impurity layer and the metal compound layer is reduced, and irregularities generated at the interface between the layers are suppressed. Therefore, the number of portions (projections) where the metal compound layer comes close to the substrate via the impurity layer is reduced, so that the current leakage from this portion toward the substrate is reduced.

(Examples) Details of the present invention will be described using examples.

FIG. 1 is a sectional view showing a field effect transistor according to one embodiment of the present invention in the order of manufacturing steps.

First, a field oxide film (2) is formed by thermal oxidation on an n-type silicon substrate (1) having (100) as a main surface. The oxide film (2) surrounded by the element formation region on the gate oxide film (3 _1), doped polycrystalline silicon layer (3 _2),
A tungsten silicide layer (3 ₃ ) and a CVD-SiO ₂ film (3 ₄ ) are sequentially laminated and then etched by gate etching to form a laminated film (FIG. 1 (a)).

Then, using the laminated film and the field oxide film (2) as a mask, Si ions are applied to the surface of the substrate (1) at an acceleration voltage of 40 ke.
V is implanted at a dose of 2 × 10 ¹⁵ cm ⁻² . As a result, the surface of the substrate became amorphous over a depth of about 0.1 μm. After that, BF ₂ ions are continuously applied at an acceleration voltage of 15 keV and a dose of 2 ×
Inject at 10 ¹⁵ cm ^-2 . Further, lamp annealing is performed at 1000 ° C. for 30 seconds. As a result, a depth of about 0.08 μm
P ⁺ -type impurity diffusion layers (4 ₁ ) and (5 ₁ ) were formed. At this time, the average lattice constant of the diffusion layers (4 ₁ ) and (5 ₁ ) was 5.44 °. After this step, SiO ₂ film ₍₃₅₎ provided in the side wall of the laminated film, to complete the gate electrode (3) (FIG. 1 (b)).

Thereafter, C ions (6) are accelerated at 5 keV using the gate electrode (3) and the field oxide film (2) as a mask.
A dose of 1 × 10 ¹⁴ cm ⁻² is implanted into the surfaces of the diffusion layers (4 ₁ ) and (5 ₁ ). Next, lamp annealing is performed at 950 ° C. for 15 seconds. As a result, the average lattice constant of the diffusion layers (4 ₁ ) and (5 ₁ ) became 5.41 °. This is because part of the substrate silicon is C
This is because the crystal structure has been changed to a substitution. Here, the average lattice constant of the diffusion layers (4 ₁ ) and (5 ₁ ) at least in the vicinity of the surface (depth of about 200 °) may be set to 5.41 ° (FIG. 1 (c)).

Further, the entire surface sputtering deposited by for example Ni film ₍₇₁₎ to 200Å thick using (FIG. 1 (d)). After this 9
The nickel silicide layers (4 ₂ ) and (5 ₂ ) are formed by performing lamp annealing at 00 ° C. for 10 seconds. Thereby, the source / drain regions (4) and (5) are prepared. At this time silicide nickel layer formed (4 _2), the lattice constant of (5 ₂₎ was 5.41A. Therefore silicide nickel layer formed here (4 _2),
(5 ₂₎ of the diffusion layer (4 _1), consistent with (5 _1). (7 ₂₎ is a Ni layer remaining without reacting (FIG. 1 (e)).

Then, using a mixed solution of HCl and H ₂ O ₂ , an unreacted Ni layer (7
₂ ) is removed at room temperature. At this time, the mixed solution was HCl: H ₂ O ₂
= 3: 1. Finally, a CVD-SiO ₂ film (8) as an interlayer insulating film is deposited on the entire surface with a thickness of 1 μm, and contact holes are provided on the source / drain regions (4) and (5).
Here, for example, an electrode wiring (9) of an Al.Si alloy is formed to complete the field effect transistor (FIG. 1 (f)).

The leakage current between the source / drain regions (4) and (5) of the field effect transistor formed by the above method and the silicon substrate (1) was examined. Figure 2 shows 1 × 10 ^-3 cm ²
Is a result of measuring a value of a leak current (I) when a reverse bias (V) is applied to a source region having an area of 0 to 15 V in a range of 0 to 15 V.

Also, in this figure, the difference (δ) between the irregularities described above is 100 °.
For comparison with the FET formed by the method of the present embodiment and the FET formed by the conventional method (δ = 500 °, 800 °), the measurement results are also shown. As is apparent from FIG. 2, when the δ is 500 ° or more, the leakage current (I) cannot be suppressed to 10 ⁻⁸ [A] or less.
Can be reduced to 10 ⁻¹¹ [A] or less until the junction is broken. Similar results were obtained for the drain region.

The reason why the leak current was reduced in this way is that in the conventional technology, the difference in the lattice constant between the diffusion layer and the metal silicide is large, so that stress is generated at this interface. And a leak current is generated from this, but in this embodiment, the P ⁺ type diffusion layers (4 ₁ ) and (5 ₁ )
Silicide Nickel (4 ₂₎ by implanting C ions (6),
Since closer to the lattice constant of (5 _2), the occurrence of the unevenness 10
It is considered that the leakage current was reduced to 0 °. The leakage current was also suppressed in FETs having a difference of more than three asperities, for example, those of 30 mm as well as those of 100 mm. However,
It was found that it was difficult to form an FET with a step smaller than 30 mm, and it was not suitable for mass production.

From the above, in the FET having a δ of 100 ° or less, the leak current is suppressed to a constant value until the junction is broken, regardless of the applied voltage, and the leak current can be reduced to about two digits compared to the conventional case. Further, such a FET in which δ is 100 ° or less,
It can be easily formed for the first time by the method of the present invention.

Next, another embodiment of the present invention will be described with reference to FIG.

First FIG. 1 (a) by the same process as ~ FIG. 1 (c) a field oxide film (2), a gate electrode (3), P ⁺ -type diffusion layer (4 _1), to form a (5 ₁₎ . At this time, the P ⁺ type diffusion layer is C
(6) is implanted, and the average lattice constant is also 5.41Å
(FIG. 3 (a)).

Then, the diffusion layer (4 _1), (5 ₁₎ a tungsten silicide layer on the (4 ₃₎ are formed by selective CVD method _(3).
Thus, the source / drain regions (4) and (5) are prepared. In this case a tungsten silicide layer selectively formed (4 _3),
Lattice constant of ₍₃₎ was 5.41A (FIG. 3 (b)).

Finally, an SiO ₂ film (8) is formed by a CVD method, a contact hole is provided, and an electrode wiring (9) of an Al.Si alloy is formed to complete the field effect transistor (FIG. 3 (c)). .

The field effect transistor formed in this manner also had the same characteristics as the previous embodiment.

In the above two embodiments, the relationship between the lattice constants is [impurity layer (BF ₂ -doped silicon layer)> metal compound (nickel silicide, tungsten silicide)]. The structure was changed to a crystal structure in which the part was replaced with C, and the average lattice constant of this layer was reduced to match the metal compound. The present invention is attained for the first time by selecting an ionic species that can bring the average lattice constant of the impurity layer closer to the lattice constant of the metal compound layer.

 The present invention is not limited to the above embodiment.

For example, in the embodiment, nickel silicide is used as the metal silicide. However, other metal compounds which have low contact resistance with the silicon impurity layer and can be treated similarly to nickel silicide, such as vanadium silicide, tungsten silicide, cobalt silicide, palladium silicide, Platinum silicide, iridium silicide, or the like may be used. In addition, manganese silicide and rhodium silicide can be used depending on the case.

In the embodiment, the metal silicide is formed after forming the impurity diffusion layer. However, the present invention can be applied to a semiconductor device in which the impurity diffusion layer is formed after forming the metal silicide.

Further, although silicon is used for the substrate, germanium or a compound semiconductor such as GaAs or InP can be used.

Although the MOS type FET has been described here, the present invention is applicable to other FETs such as a Schottky junction type FET, a pn junction type FET, and a hetero junction type FET.
The present invention is also applicable to FETs or to other semiconductor devices having shallow impurity layers other than FETs, such as diodes and bipolar transistors.

In addition, it goes without saying that the present invention can be variously modified and implemented without departing from the gist of the present invention.

〔The invention's effect〕

According to the structure of the present invention, a semiconductor device in which a leak current generated at a junction interface is suppressed can be easily formed.

[Brief description of the drawings]

FIG. 1 is a view showing one embodiment of the present invention, FIG. 2 is a view for explaining one embodiment of the present invention, FIG. 3 is a view showing another embodiment of the present invention, and FIG. FIG. 5 is a diagram for explaining a conventional example. 1 ... silicon substrate, 2 ... field oxide film, 3 ...
Gate oxide film, 4 ... source region, 5 ... drain region, 6 ... predetermined ion (C ion), 7 ... metal layer,
8 ... interlayer insulating film, 9 ... electrode wiring.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/28-21/288 H01L 29/41-29/51 H01L 29/78

Claims (4)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, an impurity layer of a second conductivity type selectively provided on the surface of the substrate, and constituent elements and metals of the semiconductor substrate provided on the surface of the impurity layer. A semiconductor device comprising: a metal compound layer including a metal compound layer, wherein an interface between the impurity layer and the metal compound layer has unevenness with a step of 100 ° or less. 2. The semiconductor device according to claim 1, wherein the laminated film of the impurity layer and the metal compound layer is a source region or a drain region of a field effect transistor. 3. An impurity layer of the second conductivity type is selectively formed on the surface of the semiconductor substrate of the first conductivity type, and a metal compound containing a constituent element of the semiconductor substrate and a metal is formed on the surface of the impurity layer. In the method for manufacturing a semiconductor device, the method further comprises implanting desired ions into the semiconductor substrate or the impurity layer before forming the metal compound, thereby forming an average lattice constant of a crystal of the semiconductor substrate or the impurity layer. Is brought closer to the average lattice constant of the metal compound. 4. The semiconductor substrate is silicon, the ion species of the ion implantation is carbon, and the metal compound layer is made of vanadium silicide, tungsten silicide, nickel silicide, cobalt silicide, baradium silicide, platinum silicide, iridium silicide. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the method is selected.