JP2745946B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor integrated circuit, and more particularly to a method of manufacturing a semiconductor integrated circuit having a resistor made of polysilicon and a shallow junction.

[0002]

2. Description of the Related Art A conventional method for manufacturing a semiconductor integrated circuit (hereinafter referred to as a "integrated circuit")
It is called the conventional method. ) Will be described with reference to FIGS.
FIG. 4 is a view for explaining a conventional method, and is a cross-sectional view in the order of steps including manufacturing steps A to C of the semiconductor chip, and FIG. FIG.

According to the conventional method, first, as shown in FIG. 4A, a P-type buried layer 2 and an N-type epitaxial layer 3 are formed on a P-type semiconductor substrate 1, and then the P-type semiconductor substrate 1 is heated. The first oxide film layer 4 is formed by oxidation. Subsequently, the first oxide film layer 4 is selectively etched and removed by photolithography, a diffusion window is opened, and the state shown in FIG.

Then, as shown in FIG. 4B, a large amount of P-type impurities are diffused to form an insulating diffusion layer 5, and after the first oxide film layer 4 is removed by etching, The P-type semiconductor substrate 1 is again thermally oxidized to form a second thin oxide film layer 6. After that, the surface of the second oxide film layer 6 other than on the collector diffusion layer window is covered and protected by the first photoresist layer 7, and then a large amount of N-type impurities are ion-implanted from the upper surface to form the collector diffusion layer 8. , The state shown in step B of FIG.

Next, the first photoresist layer 7 is entirely removed, a high-temperature heat treatment is performed to anneal the collector diffusion layer 8, and thereafter, as shown in FIG. The surface of the second oxide film 6 other than on the diffusion window is covered and protected by a second photoresist layer 9. Then, using the second photoresist layer 9 as a mask, an active base diffusion layer 10 is formed by ion-implanting, for example, B ⁺ as a P-type impurity at 30 KeV and 3 × 10 ¹⁴ / cm ² from the upper surface, as shown in FIG. The state shown in Step C is established.

Next, after removing the second photoresist layer 9, as shown in FIG. 5D, a nitride film layer 11 is formed by a normal vapor deposition method. Subsequently, after a first polysilicon layer 12 having a thickness of 0.4 μm is formed by a normal vapor phase growth method, the upper surface is made to be N-type, for example, As ⁺ is 70 KeV, 1 ×
Ion implantation is performed under the condition of 10 ¹⁵ / cm ² .

Next, the first polysilicon layer 12 is annealed.
Is performed at 800 ° C. for 30 minutes.
After uniformizing the impurity concentration distribution of the mold, the first polysilicon layer 1 other than the resistive element region is formed by ordinary photolithography.
2 is removed by etching. Next, after the third oxide film layer 13 is formed by a normal vapor deposition method, the third oxide film layer 13 other than on the polysilicon resistance region is etched away.

Subsequently, by selectively etching the nitride film layer 11 and the second oxide film layer 6 sequentially by a usual photolithography method, an emitter diffusion window, a base contact hole and a collector contact window are formed. After the opening, a second polysilicon layer 14 having a thickness of 0.2 μm is formed on the entire surface by a vapor phase growth method. Thereafter, the second polysilicon layer 14
As an N-type from the upper surface, for example, As ⁺ is 70 KeV, 1 × 10 ¹⁶ /
Ions are implanted under the condition of cm ² to obtain a state as shown in step D in FIG.

Next, as shown in FIG. 5E, after the fourth oxide film layer 15 is formed by the ordinary vapor phase growth method,
Activated base diffusion layer 1
The annealing of 0 and the formation of the emitter diffusion layer 16 having a depth of 0.1 μm are simultaneously performed. Thereafter, the fourth oxide film layer 15 and the second polysilicon layer 14 other than those on the emitter diffusion window and the collector contact window are sequentially etched and removed by a usual photolithography method. 2
The oxide film layer 6 is removed by etching to expose a part of the active base region.

Next, base contact diffusion (for example, using the third oxide film layer 13 and the fourth oxide film layer 15 as a mask).
By carrying out (900 ° C., BCl ₃ , 30 minutes), the base contact diffusion layer 17 is formed, and the state shown in step E of FIG. 5 is obtained.

Next, as shown in step F of FIG. 5, the fourth oxide film layer 15 and the third oxide film layer 13 are selectively etched and removed by a normal photolithography method, thereby forming a resistance contact window. The polysilicon layer 14 on the opening and the emitter diffusion layer 16 and the collector diffusion layer is exposed. Then, after depositing Al from the upper surface, the Al is deposited by photolithography.
Is selectively removed by etching, and the emitter electrode 18, the collector electrode 19, the base electrode 20, the resistance electrode 21, and the wiring between the elements are formed, thereby completing the bipolar integrated circuit shown in the step F of FIG.

[0012]

By the way, in order to improve the high frequency characteristics of a bipolar IC, in general, TR
It is important to miniaturize the element, to make the junction shallower, to reduce the stray capacitance of the resistance element, and to increase the cut-off frequency fr by setting the operation current of TR relatively high.

Therefore, by simultaneously opening the emitter diffusion window and the base contact window, it is possible to avoid the displacement of the diffusion window and to use a polysilicon layer containing arsenic as the emitter diffusion source and the resistance element. It is a reality that the thickness of the polysilicon layer is relatively thick, thereby increasing the electromigration resistance.

Therefore, the polysilicon layer for the emitter diffusion (for example, having a thickness of 0.1 to 0.2 μm) and the polysilicon layer for the resistive element (for example, having a thickness of 0.3 to 0.4 μm) are different in thickness. Each must be formed individually. For this reason, in the above-mentioned conventional method, annealing of the resistance polysilicon layer is performed at 800 ° C. As a result, the impurity concentration distribution is not sufficiently uniform, and the region having the maximum impurity concentration is located at the center of the polysilicon layer. And has a disadvantage that a concentration gradient occurs.

Therefore, there is a problem that the side wall shape after the etching of the polysilicon layer becomes reverse tapered due to the concentration dependency of the etching rate of the polysilicon layer, and disconnection of the wiring electrode and metal residue frequently occur. This tendency was more pronounced as the thickness of the polysilicon layer was increased.

An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit which solves the above-mentioned drawbacks and problems.
In detail, according to the present invention, annealing can be performed at a higher temperature as compared with the above-mentioned conventional method. As a result, the impurity concentration in the polysilicon layer can be made uniform, and the polysilicon layer can be etched. From the rear side wall cross-sectional shape and reverse taper to tape
It is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit, which can be improved to a par shape, and can eliminate the disconnection of the electrode metal and the residue of the electrode metal, which are often generated in the past.

[0017]

According to the present invention, annealing of a high-concentration ion-implanted layer of an N-type impurity formed in a polysilicon layer for a resistance element is performed at a high temperature simultaneously with formation of an emitter diffusion layer. It is an object of the present invention to provide a novel method of manufacturing a semiconductor integrated circuit in which a sidewall section of a polysilicon layer after etching is processed into a taper shape by making the impurity concentration in the polysilicon layer uniform.

That is, according to the present invention, (1) after forming a first insulating layer on the surface of a semiconductor substrate of the first conductivity type, selectively introducing impurities of the second conductivity type through the first insulating layer to activate the active layer; (2) forming a second insulating layer on the active base region which is not etched by a solution immersing the first insulating layer, and (3) forming the second insulating layer on the active base region. Selectively etching away to open an emitter diffusion hole and a base contact hole; and (4) selectively etching away the first insulating layer, opening an emitter diffusion window, and forming the active base. Exposing a region, (5) the exposed region and the first and second regions
Forming a polysilicon layer on the insulating layer, and then introducing a large amount of impurities of the first conductivity type from the upper surface, (6) heat treatment at a high temperature to introduce impurities into the active base region to form an emitter region. (7) etching and removing the polysilicon layer other than the resistance region to a desired thickness; (8) etching and removing at least the polysilicon layer other than the emitter region and the resistance region to remove at least the polysilicon resistance region. A method for manufacturing a semiconductor integrated circuit, which includes a step of processing the side surface into a trapezoidal shape.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIGS. 1 and 2 are diagrams for explaining a first embodiment of the present invention, and FIG. 3 is a diagram for explaining a second embodiment of the present invention.

(Embodiment 1) FIG. 1 is a view for explaining a first embodiment of the present invention, and is a cross-sectional view in the order of steps including manufacturing steps A to C of a semiconductor chip, and FIG. FIG. 2 is a process order sectional view including manufacturing steps D to G following FIG. 1.

First, an N-type buried layer 2, an N-type epitaxial layer 3 and a first
After the oxide film layer 4 is formed, an insulating diffusion window is opened (step A in FIG. 1). Thereafter, an insulating diffusion layer 5, a second oxide film layer 6, a collector diffusion layer 8, a second photoresist layer 9, and an active base diffusion layer 10 are formed in the same manner as in the conventional method (FIG. 1B). .

Next, after the second photoresist layer 9 is removed, as shown in FIG. 1C, a nitride film layer 11 is formed on the entire surface by a vapor phase growth method. Subsequently, the nitride film layer 11 and the second oxide film layer 6 are selectively etched to open an emitter diffusion window, a base contact diffusion hole, and a collector diffusion window. A polysilicon layer 22 having a thickness of 0.45 μm is formed.

Next, after As is ion-implanted into the polysilicon layer 22 at, for example, 70 KeV and 1 × 10 ¹⁶ / cm ² , a high-temperature heat treatment (for example, 950 ° C., 30 minutes) is performed to form the emitter diffusion layer 16. . Subsequently, after a third photoresist layer 23 is formed on the resistive element region, the polysilicon layer is etched and removed by a normal RIE method so as to have a thickness of 0.3 μm, and a state shown in FIG.

Next, after removing the third photoresist layer 23, as shown in step D of FIG. 2, a fourth photoresist layer 2 is formed on the emitter diffusion window and the collector contact window.
4. Cover and protect. Subsequently, the polysilicon layer is etched away by 0.15 μm by a normal RIE method using the fourth photoresist layer 24 as a mask, and then the fourth photoresist layer 24 is removed.

Thereafter, as shown in FIG. 2E, a fifth oxide film layer 25 is formed by vapor phase epitaxy, and then the fifth oxide film layer 2 on the base contact diffusion window is formed by photolithography.
5 and the second oxide film layer 6 are removed by etching. next,
Using the fifth oxide film layer 25 as a mask, base contact diffusion (for example, 900 ° C., BCl ₃ , 30 minutes) is performed to form the base contact diffusion layer 17, and the state shown in FIG.

Thereafter, the fifth oxide film layer 25 is selectively etched away, and as shown in FIG. 1F, the opening of the resistance contact window and the polysilicon layer 22 on the emitter diffusion layer 16 and the collector contact window are formed. Perform exposure. Next, as shown in FIG. 1G, an emitter electrode 18, a collector electrode 19, a base electrode 20, a resistance electrode 21 and a wiring between elements are formed in the same manner as in the conventional method to complete a bipolar integrated circuit. I do.

(Embodiment 2) FIG. 3 is a view for explaining a second embodiment of the present invention, and is a cross-sectional view in the order of steps A to D for manufacturing semiconductor chips.

First, an N-type buried layer 2, an N-type epitaxial layer 3,
An insulating diffusion layer 5, a second oxide film layer 6, a collector diffusion layer 8,
After forming an active base diffusion layer 10, a nitride film layer 11, an emitter diffusion window, a base contact diffusion hole, a collector contact window and a polysilicon layer 22 having a thickness of 0.3 μm, a sixth layer is formed by a vapor phase growth method. An oxide film layer 26 is formed. next,
After performing the high-temperature heat treatment (for example, 950 ° C., 30 minutes) to form the emitter diffusion layer 16, the sixth oxide film layer 26 other than on the resistance element region is selectively etched away (Step A in FIG. 3).

Next, as shown in FIG. 2B, the polysilicon layer 22 is etched away by 0.15 μm by a normal RIE method using the sixth oxide film layer 26 as an etching-resistant mask, and then, on the emitter diffusion window and The polysilicon layer 22 on the collector contact window is covered and protected by a fourth photoresist layer 27. Subsequently, the polysilicon layer 22 is etched away by 0.15 μm again by the usual RIE method using the sixth oxide film layer 26 and the fourth photoresist layer 27 as an etching-resistant mask, to obtain a state shown in FIG. 3B.

Next, after the sixth oxide film layer 26 is removed by etching, as shown in FIG. 3C, a fifth oxide film layer 25 is formed by a vapor growth method. Subsequently, the fifth oxide film layer 25 and the second oxide film layer 6 on the base contact diffusion holes are formed.
Then, base contact diffusion (for example, 900 ° C., BCl ₃ , 30 minutes) is performed to form a base contact diffusion layer, and the state shown in step C of FIG. 3 is obtained. Next, the emitter electrode 18, the collector electrode 19, the base electrode 20, the resistance electrode 21, and the inter-element wiring are formed in the same manner as in the first embodiment (Step D in FIG. 3).

[0031]

As described above, in the semiconductor integrated circuit to which the present invention is applied, the annealing of the polysilicon layer for resistance can be performed simultaneously with the formation of the emitter diffusion layer. Annealing can be performed at a higher temperature (800 ° C. → 950 ° C.). Therefore, the impurity concentration in the polysilicon layer can be made uniform, and the cross-sectional shape of the side wall of the polysilicon layer after etching can be improved from a reverse taper to a taper shape. This has the effect of eliminating any disconnection of the electrode and the rest of the electrode metal.

[Brief description of the drawings]

FIG. 1 is a view for explaining a first embodiment of the present invention and is a sectional view in the order of steps including manufacturing steps A to C of a semiconductor chip.

FIG. 2 is a process order sectional view including manufacturing steps DG following FIG. 1;

FIG. 3 is a view for explaining a second embodiment of the present invention, and is a sectional view in the order of steps including manufacturing steps A to D of a semiconductor chip.

FIG. 4 is a view for explaining a conventional method, and is a cross-sectional view in the order of steps including manufacturing steps A to C of a semiconductor chip.

FIG. 5 is a sectional view in the order of steps including manufacturing steps DF following FIG. 4;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 P-type semiconductor substrate 2 P-type buried layer 3 N-type epitaxial layer 4 first oxide film layer 5 insulating diffusion layer 6 second oxide film layer 7 first photoresist layer 8 collector diffusion layer 9 second photoresist layer Reference Signs List 10 active base diffusion layer 11 nitride film layer 12 first polysilicon layer 13 third oxide film layer 14 second polysilicon layer 15 fourth oxide film layer 16 emitter diffusion layer 17 base contact diffusion layer Reference Signs List 18 Emitter electrode 19 Collector electrode 20 Base electrode 21 Resistive electrode 22 Polysilicon layer 23 Third photoresist layer 24 Fourth photoresist layer 25 Fifth oxide layer 26 Sixth oxide layer 27 Fourth photoresist layer

Claims (1)

(57) [Claims] (1) After forming a first insulating layer on the surface of a first conductive type semiconductor substrate, an active base region is formed by selectively introducing a second conductive type impurity through the first insulating layer. (2) forming a second insulating layer on the active base region which is not etched by a liquid immersing the first insulating layer; (3) selectively etching the second insulating layer Removing and opening an emitter diffusion hole and a base contact hole; (4) selectively etching away the first insulating layer, opening an emitter diffusion window and exposing the active base region. (5) forming a polysilicon layer on the exposed region and the first and second insulating layers, and then introducing a large amount of a first conductivity type impurity from the upper surface; Forming an emitter region by introducing impurities into the active base region; (8) etching away the polysilicon layer other than at least the emitter region and the resistance region, and processing so that at least the side surface of the polysilicon resistance region becomes trapezoidal. A method for manufacturing a semiconductor integrated circuit, comprising: