JP2870502B2 - Digital data demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a demodulator for digital data, and more particularly to a demodulator for digital data randomized and modulated by a random number sequence.

[0002]

2. Description of the Related Art In a recording / reproducing apparatus which records and reproduces pulse code modulation (PCM) data on a recording medium such as a magnetic tape or an optical disk, in order to record a binary digital signal, the characteristics of the recording medium are changed. Efficient recording is performed by converting to a suitable code.

As the modulation method for the above code conversion, for example, EFM (eight-to-fourteen modulation), MFM (modified frequency modulation), 8-10 modulation, 1-7 modulation and the like are known. I have. By these modulations, the minimum value and the maximum value of the data inversion of “1” and “0” on the recording medium are limited to certain values. Among them, in the 1-7 modulation, data is NRZI (non-return-to-zero data).
Inverted) recording is performed, but since the modulation method does not become direct current (DC) -free, NRZI recording is performed after the modulated code sequence is randomized with M-sequence random numbers.
In general, randomization is often performed in units of a generation cycle of a frame synchronization signal.

[0004]

In a conventional digital data demodulation circuit for demodulating randomized recording data by a random number sequence, the reproduced data is clock-shifted and the frame synchronizing signal and the reproduced data sequence are shifted even by one bit. Occasionally, it becomes impossible to perform de-randomization correctly, and there is a drawback that data after demodulation is erroneous every frame synchronization period until frame synchronization is re-established.

[0005] The present invention has been made in view of the above points,
It is an object of the present invention to provide a demodulator for digital data capable of demodulating with less data errors even if the timing of the reproduced data and the timing of the detected frame synchronization signal are clock-shifted in a frame synchronization detection circuit.

[0006]

According to the present invention, in order to achieve the above object, a random number is randomized by a known random number sequence, and a bit of a predetermined logical value is continuous for a predetermined number or more.
A clock recovery circuit that receives as input signals a digital signal composed of data and a synchronization word modulated in accordance with a predetermined rule and that reproduces a bit clock, and detects a synchronization word of the digital signal and outputs a frame synchronization signal A frame synchronization detection and protection circuit, which receives a digital signal directly or with a delay, outputs demodulated data, and counts a count value of a pattern in which demodulated data violates a predetermined rule generated within a predetermined period. A total of N (where N is an integer of 3 or more) demodulated blocks to be output and the timing of the digital signal input to the N demodulated blocks with respect to the frame synchronization signal are represented by:
For one demodulation block, regular timing is used,
Of the remaining (N-1) demodulation blocks, M (where M is a positive integer smaller than N-1) demodulation blocks precede regular timings and differ from each other by one clock period. Timing and (NM-1)
With respect to the demodulation blocks, the timing adjustment means delays from the regular timing and differs from each other by one clock cycle, and outputs the smallest count value among the count values separately output from the N demodulation blocks. And selecting means for selecting and outputting the output demodulated data of one demodulation block.

According to the present invention, the stability of the bit clock obtained by reproducing the input digital signal by the clock recovery circuit is impaired, or the detection of the frame synchronization signal is not properly performed due to the occurrence of a bit error, and the input digital signal is not protected. Even if the timing relationship between the frame and the frame synchronization signal changes, demodulated data from one demodulation block having the smallest count value indicating the number of times of demodulation of a pattern violating the modulation rule is selected from the N demodulation blocks. As a result, demodulated data with few data errors can be obtained.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, a binary digital signal a input via an input terminal 1 is randomized modulated data, which is digital data in which two or more “1” bits do not continuously occur from a recording medium. This is the reproduced digital data.

FIG. 2 shows an example of the frame format of the input digital signal a. In the figure, a data frame is composed of sync words 21 and 22 each having a fixed pattern, and a data word 2 of 190 words in total following them.
3 (D0 to D189), and is composed of a total of 192 words. Each of the data words D0 to D189 is randomized by half-adding the M-sequence random number for each bit. One word is 12 bits.

Returning to FIG. 1, the input digital signal a is supplied to a clock recovery PLL circuit 2 to recover a bit clock b by a known phase-locked feedback loop circuit operation. b is input to each unit as an operation clock of each unit of this circuit. Also, the input digital signal a is supplied to the frame synchronization detection and protection circuit 3 to detect both or one of the synchronization words 21 and 22. The frame synchronization signal c obtained by detecting the synchronization word by the frame synchronization detection and protection circuit 3 is input to each of the derandomizing / demodulating blocks 101, 102, and 103 described later.

Further, the input digital signal a is supplied to the derandomizing circuit 6 in the derandomizing / demodulating block 101.
a while the D-type flip-flop (DF /
F) The data is input to the data input terminal 4 and is latched by the bit clock b input to the clock terminal, whereby the data is delayed by one clock cycle.

The input digital signal d output from the DF / F 4 and delayed by one clock cycle is supplied to a derandomizing
While being input to the derandomizing circuit 6b in the demodulation block 102, it is input to the data input terminal of the D-type flip-flop (DF / F) 5, where it is latched by the bit clock b input to its clock terminal. This further delays by one clock cycle. Therefore, D
From the F / F 5, a digital signal e delayed by two clock cycles with respect to the input digital signal a is extracted and input to the derandomizing circuit 6 c in the derandomizing / demodulating block 103.

Three derandomizing / demodulating blocks 10
The timing relationship between the input digital signals a, d, and e respectively provided to 1, 102 and 103 and the frame synchronization signal c differs by one clock cycle. Here, when the bit clock b obtained from the input digital signal a by the clock recovery PLL circuit 2 is stable and the relationship between the input digital signal a and the bit clock b is normally maintained, the derandomizing / demodulating block 102 When the operation timing of the circuit is set so that the de-randomization is correctly performed in the de-randomizing circuit 6b, the digital signal a which precedes the frame synchronization signal c by one clock cycle is set in the de-randomizing / demodulating block 101.
, And a digital signal e delayed by one clock cycle from the frame synchronization signal c is supplied to the derandomizing / demodulating block 103.

Derandomizing / demodulating blocks 101, 1
02 and 103 have the same configuration, respectively, and include derandomizing circuits 6a, 6b and 6c, serial / parallel converting circuits 7a, 7b and 7c, and demodulating circuits 8a, 8b and 8c.
And violation pattern counting circuits 9a, 9b, 9c. Also, demodulation circuits 8a, 8b and 8c
Are configured to output a violation pattern demodulation detection signal indicating the violation pattern demodulation, and output the violation pattern demodulation detection signal to the violation pattern count circuits 9a, 9b, and 9c.

The derandomizing circuits 6a, 6b, 6c are:
A known de-randomizing process is performed on the input digital signals a, d, and e in synchronization with the frame synchronizing signal c using the same M-sequence random number used during randomization during recording. Here, the derandomizing / demodulating block 102
As described above, since the operation timing is set so that the timing relationship between the data word bit of the input digital signal d and the frame synchronization signal c matches, the input digital signal d is de-randomized by the de-randomization circuit 6b. Is returned to the original digital signal before the randomization.

On the other hand, the derandomizing / demodulating block 10
Also in 1 and 103, de-randomization is performed on the input digital signals a and e in the de-randomizing circuits 6a and 6c. However, the timing relationship between the data word bits of the input digital signals a and e and the frame synchronization signal c is normal. Since there is a leading and lagging relationship by one clock cycle from the timing, correct modulation data cannot be reproduced as a result of the derandomization. In other words, "1"
Data that violates the rule that two or more bits do not occur consecutively are output from the derandomizing circuits 6a and 6c.

The serial / parallel conversion circuits 7a, 7b and 7c are provided with de-randomizing circuits 6a, 6b and 6 respectively.
The data serially output from c is converted into parallel data having the original word structure synchronized with the frame synchronization signal c and supplied to the demodulation circuits 8a, 8b and 8c, where the data is demodulated into PCM data. Also, demodulation circuits 8a, 8b
In 8c and 8c, when demodulating data, the occurrence of an input signal that violates the rules of modulation is detected, and a violation pattern detection signal is supplied to violation pattern count circuits 9a, 9b and 9c to be counted.

The violating pattern counting circuits 9a, 9b and 9c count the number of violating patterns input to the demodulating circuits 8a, 8b and 8c of data violating the modulation rule generated during one frame synchronization period, and count the counted value. Minimum value detection circuit 10
To supply. In the derandomizing / demodulating block 102 in which the timing relationship between the bit of the data word and the frame synchronization signal c is at a regular timing, no violation pattern occurs unless there is a bit error. On the other hand, in the derandomizing / demodulating blocks 101 and 103, the timing relationship between the bits of the data words of the input digital signals a and e and the frame synchronization signal c is different from the normal timing, so that a violation pattern occurs.

The minimum value detection circuit 10 compares the number of violating patterns from each of the derandomizing / demodulating blocks 101, 102, and 103 to find a derandomizing / demodulating block with the least number of violating patterns and generates a select signal i. Then, the select signal i is input to the data selector 11. The data selector 11 receives demodulated data (PCM data) f, g, and h from the three derandomizing / demodulating blocks 101, 102, and 103 as input signals,
From this, only one demodulated data is selected based on the select signal i and output to the output terminal 12 as output data j. The select signal i causes the data selector 11 to select the output demodulated data of the derandomizing / demodulating block having the smallest number of violation patterns.

Here, in the derandomizing / demodulating block 102 in which the timing relationship between the data word bit and the frame synchronization signal c is at a regular timing, no violation pattern occurs unless there is a bit error. Demodulated data g from demodulation block 102 is selected by data selector 11 and output to output terminal 12.

Here, when the stability of the bit clock b obtained by reproducing the input digital signal a by the clock reproducing PLL circuit 2 is impaired or a bit error occurs, the detection protection of the frame synchronization signal c is performed normally. Gone
The timing relationship between the input digital signal a and the frame synchronization signal c changes. Accordingly, assuming that the timing relationship between the frame synchronization signal c and the input digital signal a at the input of the derandomizing / demodulating block 101 becomes normal, the derandomizing / demodulating blocks 102 and 103 transmit normal demodulated data. The number of violation patterns in the derandomizing / demodulating block 101 is minimized. As a result, the data selector 11
It operates to select the output demodulated data f of the derandomizing / demodulating block 101, and outputs correct demodulated data to the output terminal 12.

Conversely, the derandomizing / demodulating block 10
Assuming that the timing relationship between the frame synchronization signal c and the input digital signal e becomes normal at the input of No. 3, the derandomizing / demodulating blocks 101 and 10
In the case of 2, normal demodulated data cannot be obtained, and the number of violation patterns of the derandomizing / demodulating block 103 is minimized. As a result, the data selector 11 operates so as to select the output demodulated data h of the derandomizing / demodulating block 103, and outputs correct demodulated data to the output terminal 12.

Thus, according to this embodiment, 3
Input digital signal a, corresponding to the frame synchronization signal c input to the three derandomizing circuits 6a, 6b and 6c.
Output demodulation data of a demodulation circuit to which data with the smallest number of violation patterns is input, between the timings d and e having a regular timing relationship and those having a timing relationship shifted one clock cycle back and forth. Is selected by the data selector 11, so that even if the clock timing relationship between the frame synchronization signal c and the input digital signal is shifted by ± 1 clock cycle, demodulated data with few errors can be obtained.

The present invention is not limited to the above embodiment. For example, five derandomizing / demodulating blocks are prepared, and the timing of the input digital signal of each derandomizing / demodulating block with respect to the frame synchronization signal is determined. , Two clocks ahead, one clock ahead, regular timing, one clock delay, and two clock delays, respectively. In short, a plurality of derandomizing / demodulating blocks may be provided.

[0026]

As described above, according to the present invention,
The timing of the input digital signal and the frame synchronization signal is lost because the stability of the bit clock obtained from the input digital signal recovered by the clock recovery circuit is impaired or the detection of the frame synchronization signal is not properly performed due to the occurrence of a bit error. Even if the relationship changes, by selecting demodulated data from one demodulation block having the smallest count value indicating the number of times of demodulation of a pattern violating the modulation rule among the N demodulation blocks, the data error is reduced. Demodulated data can be obtained, and thus, even before frame synchronization is re-established as compared with the conventional method, demodulated data that has been correctly de-randomized can be obtained. Can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a frame format of the input digital signal of FIG.

[Explanation of symbols]

 Reference Signs List 1 playback digital signal input terminal 2 clock recovery PLL circuit 3 frame synchronization detection protection circuit 4, 5 D-type flip-flop (DF / F) 6a, 6b, 6c de-randomizing circuit 7a, 7b, 7c serial / parallel conversion circuit 8a, 8b , 8c demodulation circuit 9a, 9b, 9c violation pattern counting circuit 10 minimum value detection circuit 11 data selector 12 demodulation data output terminal 101-103 de-randomizing / demodulation block a input reproduction digital signal b bit clock c frame synchronization signal d, e delay Digital signal f, g, h Demodulated data i Select signal j Output demodulated data

Claims (3)

(57) [Claims] 1. A method according to claim 1, wherein the random number is randomized by a known random number sequence, and a bit of a predetermined logical value is continuous for a predetermined number or more.
A clock recovery circuit that receives as input signals a digital signal composed of data and a synchronization word modulated in accordance with a predetermined rule, and recovers a bit clock; and detects a synchronization word of the digital signal to generate a frame synchronization signal. A frame synchronization detection / protection circuit to be output, the digital signal being input directly or with a delay, the bit clock and the frame synchronization signal being input, outputting demodulated data, and outputting the demodulated data within a predetermined period. A total of N demodulation blocks (where N is an integer of 3 or more) for outputting count values of patterns that violate the predetermined rule generated in the demodulation block, and a digital signal input to the N demodulation blocks The timing with respect to the frame synchronization signal is set to a regular time for one demodulation block. Of the remaining (N-1) demodulation blocks, M demodulation blocks (where M is a positive integer smaller than N-1) precede the regular timing and are 1 A timing adjusting unit that sets a timing different from the clock cycle, and delays the (NM−1) demodulation blocks from the normal timing and sets the timing different from the normal timing by one clock cycle; Selecting means for selecting and outputting output demodulation data of one demodulation block which outputs the smallest count value among the output count values. 2. The timing adjustment means receives the digital signal as an input signal, and comprises (N-1) cascaded delay circuits each having a delay time of one clock cycle, and directly converts the digital signal. One of the N demodulation blocks is input to one of the demodulation blocks, and the remaining (N-1) demodulation blocks are respectively input with the delayed digital signals output from the (N-1) delay circuits, 2. The digital data demodulation device according to claim 1, wherein the operation timing is set so that the timing relationship between the data bits of the digital signal delayed by M clock cycles and the frame synchronization signal in all. 3. The demodulation block receives the digital signal or a delayed digital signal thereof as an input signal,
De-randomizing in synchronization with the frame synchronization signal using the known random number sequence, a de-randomizing circuit for restoring data before the randomizing, and demodulating output data of the de-randomizing circuit and outputting demodulated data A demodulation circuit that outputs a violation pattern detection signal when demodulating data that violates the modulation rule; and a count circuit that counts the violation pattern detection signal and outputs the count value. Receiving, as an input signal, the count value within the predetermined period, which is separately output from the N demodulation blocks, and a minimum value detection circuit for detecting a minimum count value among the input signal; Each demodulated data output from the minimum value detection circuit is received as an input signal, and the output signal of the minimum value detection circuit is received as a select signal. 3. The digital data according to claim 1, further comprising a data selector for selecting and outputting output demodulated data of one demodulation block that outputs a count value detected as a minimum value by the small value detection circuit. Demodulator.