JPS6260747B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a method of digital modulation method.
This invention relates to a demodulation circuit for signals modulated by MFM (MODIFIED FM) modulation method.

Recently, devices that convert audio signals into PCM (pulse code modulation) signals and record and reproduce them have been put into practical use. When recording such a PCM signal,
Broadly speaking, there is a method of recording diagonally on a magnetic tape using the rotating magnetic head of a video tape recorder, and a method of recording on multiple tracks in the width direction of the magnetic tape using a fixed magnetic head of a reel-to-reel tape recorder. There is a method. When recording onto multiple tracks of a magnetic tape using a fixed magnetic head, the PCM signal is converted at a low speed, but if an NRZ format PCM signal is recorded directly onto a magnetic tape, for example, "0" will be long. If this continues, if there is no change in the signal and the tape running speed is uneven, the number of "0"s may be erroneously reproduced during reproduction. Therefore, it is necessary to record so that there is always a change in the recording current within a certain period of time, and one such recording method is to record digital data (PCM signal) by MFM modulation. In other words, as shown in Figure 1 a and b, MFM modulation inverts the polarity at the center of the bit corresponding to data "1" and when data "0" continues, the polarity is reversed at the boundary of that bit. be.

Next, a method for demodulating this MFM modulation signal using a phase locked loop (hereinafter referred to as PLL) circuit will be briefly explained with reference to FIGS. 1 and 2. The MFM signal reproduced from the magnetic tape (see Figure 1b) is sent to the edge detection pulse generation circuit 1.
(for example, configured with a differentiating circuit),
Therefore, this circuit 1 generates an edge detection pulse (first pulse) synchronized with the edge (rising, falling) of the MFM signal.
(see figure c) is output. This edge detection pulse is input to a PLL circuit 2, from which a clock pulse (see FIG. 1d) synchronized with the edge detection pulse is obtained. This clock pulse d
has a period of (T/2), where T is the bit period of the original digital data. Then, this clock pulse d is frequency-divided by two in a flip-flop (hereinafter referred to as FF) circuit 3 to obtain a clock pulse e with a period T. By using the FF circuit 4 to read out the etching detection pulse c at the rising edge of the demodulation clock pulse e, the original digital data (see Figure 1g) (this data is
(in NRZ format) can be obtained.

By the way, if the phase of the demodulating clock pulse e differs by 180 degrees from the phase e shown in FIG. 1 due to the initial state of the F-F circuit 3, correct data cannot be demodulated.

For this purpose, the phase of the demodulated clock pulse e is initialized by the "101" pattern detection circuit 5, and the phases of the edge detection pulse c and the demodulated clock pulse e are matched. In other words, the signal inversion interval of the MFM modulation signal b becomes "2T" only when the data pattern is "101", so when this pattern is detected, the reset pulse (see Figure 1 f) is sent to F.
In addition to the -F circuit 3, the phase (polarity) of the demodulated clock pulse e is initialized to ensure that data "1" is correctly demodulated in response to the trailing edge of "2T". In order to ensure that data is read out, the rise of the demodulation clock pulse e is not coincident with the rise of the edge detection pulse c, but is positioned approximately at the center of the width of the edge detection pulse c. That is, it is assumed that the PLL circuit 2 outputs a clock pulse d having the above-mentioned phase relationship with respect to the edge detection pulse. Using PLL circuit
A demodulation circuit for MFM modulated signals is also explained in detail in, for example, Japanese Patent Laid-Open No. 55-28567.

By the way, MFM is better than magnetic tape, disk, etc.
When reproducing the modulated signal, there is a possibility that pulses other than the edge detection pulses responding to the data of the present invention may be generated due to dropouts, noise effects, and the like.

When such a pulse is input to the PLL circuit 2, the demodulated clock pulses d and e are disturbed, and the phase relationship between the demodulated clock pulse e and the edge detection pulse c is changed.
Erroneous data will be demodulated. and,
Depending on the state of the FF circuit 3, data errors may continue until the next "101" pattern appears and the correct phase relationship is set again. In other words, even if a random error occurs, a burst of errors will occur until the next "101" pattern is detected.

Therefore, the present invention utilizes two PLL circuits in order to prevent the propagation of data demodulation errors.

The details will be explained below with reference to Examples.

In the present invention, as shown in Fig. 3g, the demodulated signal is composed of data and a synchronization signal related to this data. It is assumed that the pattern (distinguished from data) is added as a unique pattern. The feature of the present invention is that the clock pulse is demodulated again using the PLL circuit based on the demodulated synchronization signal of the data and synchronization signal demodulated using the PLL circuit 2.

Therefore, in FIG. 5 showing the circuit of the present invention,
The PLL circuit 2 is called the first PLL circuit, and the FF circuit 3
The clock pulse e outputted from the first demodulated clock pulse is called the first demodulated clock pulse. Further, the unique pattern of the synchronization signal is detected by the synchronization signal detection circuit 6, and the demodulated synchronization signal (see FIG. 3j) detected by the detection circuit 6 is used as the reference signal of the second PLL circuit 8. However, the F-F circuit 4 and the synchronization signal detection circuit 6
will be referred to as the first demodulation circuit 7 for the demodulated synchronization signal j.

Now, the second PLL circuit 8 demodulates the second clock pulse k (its period is T) synchronized with the demodulation synchronization signal j. Since the period of the demodulated synchronizing signal j, which is the reference signal of the second PLL circuit 8, is 140T, the second demodulated clock pulse k is divided by the frequency dividing circuit 9.
The signal l whose frequency has been divided by 1/140 is fed back to the phase comparison input side of the second PLL circuit 8. Since the second demodulation clock pulse k is demodulated in conjunction with the synchronization signal, as long as the synchronization signal is accurately reproduced, even if the data reproduction is disrupted during that time, the second demodulation clock pulse k will not be disturbed. Therefore, by using the second demodulation clock pulse k, demodulated data with fewer errors can be obtained. It should be noted that if a dropout occurs in the demodulated synchronizing signal j (see broken line j in FIG. 3), the second PLL circuit 8 is configured not to perform phase comparison with the second demodulated clock pulse k.

When demodulating data based on the second demodulation clock pulse k, in the embodiment shown in FIG.
Edge detection pulse c to widen the data detection window
The pulse width is widened. That is, the monostable multivibrator 10 is triggered by the edge detection pulse c, and its width is expanded to the metastable period (T/2 in the embodiment) of the monostable multivibrator 10 to obtain the pulse h. Correspondingly, the second demodulated clock pulse k is delayed by the delay circuit 11 so that the rising edge of the second demodulated clock pulse k is positioned approximately at the center of the width of the pulse h. By using the F-F circuit 12 to read out (latch) the pulse h using the delayed second demodulation clock pulse i, the original data (NRZ) m can be obtained (the fourth (see figure).

According to the present invention described above, the synchronization signal is once demodulated using the first PLL circuit, and the second PLL circuit is demodulated using the demodulated synchronization signal as a reference signal to demodulate the clock pulse. Since the structure is such that the original data is demodulated based on the clock pulse, even if the reproduction of the data between the synchronization signals is disturbed, this will not cause the demodulation clock pulse to be disturbed, thereby reducing data errors. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a conventional operating waveform diagram, FIG. 2 is a conventional demodulation circuit diagram, FIGS. 3 and 4 are operational waveform diagrams of the present invention, and FIG. 5 is a demodulation circuit diagram according to the present invention. 1 is the edge detection pulse generation circuit, 2 is the first PLL
circuit, 7 is the first demodulation circuit, 8 is the second PLL circuit, 1
2 is an FF circuit (second demodulation circuit).

Claims (1)

[Claims] 1 This is a circuit for demodulating the original data from the MFM modulated signal of digital data and synchronization signal, and the edge (rising, falling) of the MFM modulated signal
an edge detection pulse generation circuit that generates an edge detection pulse when the edge detection pulse is detected; a first phase-locked loop circuit that receives the edge detection pulse output from the pulse generation circuit and demodulates a clock pulse synchronized with the edge detection pulse; a first demodulation circuit that restores the original synchronization signal based on the edge detection pulse and a first demodulation clock pulse output from the first phase-locked loop circuit; and a demodulation synchronization signal output from the first demodulation circuit is inputted. and a second phase-locked loop circuit that demodulates the clock pulse synchronized with the demodulation synchronization signal, and demodulates the original digital data based on the edge detection pulse and the second demodulation clock pulse output from the second phase-locked loop circuit. A demodulation circuit for an MFM modulated signal, comprising a second demodulation circuit.