JP2869988B2 - Television signal transceiver - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television signal transmitting / receiving apparatus used for image communication, satellite communication, CATV, etc., for transmitting and receiving a video signal in which a part or all of the same signal is omitted.

2. Description of the Related Art In a conventional television signal transmission system, an uncompressed television signal is transmitted in all periods, or compressed transmission is performed in units of horizontal scanning lines or fields. However, in this case, since all the signals are compressed and transmitted, an extremely large-scale device is required.

Thus, in the conventional time-base compression transmission method of a signal,
The device becomes large-scale, and in particular, the device on the receiving side becomes large-scale, and there is a problem that it is difficult to use it except for a large-scale transmission company. Therefore, the present inventor has solved a problem of the related art, and has specially described a signal processing method which can transmit a television signal in a substantially short time and can simplify a signal processing device therefor. No. 63-257560.

In this signal processing method, a television signal is divided into horizontal scanning lines, and a video signal Vn in an _n- th horizontal scanning period and a video signal in an (n-1) -th horizontal scanning period in one field. compares the signal V _n-1, both the video signal of a part or a video signal portion of the video signal V _n which is different from the the video signal V _n-1 instead of the video signal V _n when all are different It is characterized by transmitting only Vx or a part of Vn identical to Vn-1.

At that time, as also delivered into the field included the the video signal V _x a code signal indicating the position of the beginning or end of the video signal V _x, also, the video signal V _x of the n-th horizontal scanning period together with the video signal V _x of the timing of transmitting in the original video signal V _n is changed from the existing timing, it is sent a code signal indicating the change position in the field included the video V _x Good.

Further, so as to deliver to insert code signals indicating the code signal or change position indicating the position of the beginning or end of the video signal V _x narrowing the period of the horizontal synchronizing signal in the television signal at its narrow position be able to.

Then, having the features also be transmitted by inserting an analog or digital signal to a portion other than the video signal V _x of the n-th horizontal scanning period.

According to such a signal processing method, instead of transmitting all of the television signals, two consecutive horizontal scanning periods are compared, and only the portions that are different between the two and the same portion are transmitted, and the same is transmitted. Is not transmitted, so that the period required for transmission can be substantially shortened and compressed.
Therefore, it is possible to insert another signal and transmit it during the remaining period.

In addition, as means for determining the signal to be transmitted, the television signals of two successive horizontal scanning periods are compared to detect the difference, so that the transmission side is, for example, a delay line and a comparator and their control. The receiving side can be configured with a delay line and a signal insertion switching circuit and their control circuits, and can be implemented with a simple configuration.

Further, other signals can be inserted and transmitted during the period of the same signal that does not need to be transmitted, so that the signal transmission efficiency,
The range of use can be greatly expanded.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a novel television signal transmitting / receiving apparatus using the signal processing method proposed prior to the present invention. An object of the present invention is to realize a television signal transmitting apparatus that is smaller and more practical than an axial compression transmission type television transmitting / receiving apparatus.

Means for Solving the Problems In order to achieve the above object, a television signal transmitting / receiving apparatus of the present invention divides a television signal into horizontal scanning line units, and outputs an image of an nth horizontal scanning period in one field. comparing the video signal V _n-1 of the signal V _n and the (n-1) th horizontal scanning period, it differs from the video signal V _n-1 when a portion or all of the two video signals are different and including a portion of the video signal Vx or only Vn-1 identical to the Vn portion of the video signal V _n are further brought closer to the trailing edge of the horizontal synchronizing signal to the leading edge, and the remaining portions of said video signal Vx A television signal transmitter for transmitting information by adding one piece of information; and a video signal V _{n-1 in} the (n-1) th horizontal scanning period of the television signal transmitted from the television signal transmitter. When the video signal V _x of the n-th horizontal scanning period as an input, Mixing an image signal V _x to a part or the whole of the video signal V _n-1, superimposed, further comprising a television signal receiver for reproducing a video signal V _n of the replacement or the n-th horizontal scanning period by the calculation It is a feature.

Operation With the above-described configuration, not all of the television signals are transmitted, but two consecutive horizontal scanning periods are compared, and only the different portions or the same portions are partially transmitted from the transmitter. In addition, it is possible to realize a television signal transmitting / receiving apparatus having a substantially short transmission time.

In addition, another signal can be inserted and transmitted during the period of the same signal that does not need to be transmitted, so that the transmission efficiency and use range of the signal can be greatly expanded.

Embodiment Hereinafter, a television transmitting / receiving apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a signal processing circuit of a television signal transmitter. In the figure, 1 is a source of television signals, it is assumed here that the television signal phi ₁ of the signal source of the NTSC system.
Reference numeral 2 denotes a synchronizing signal reproducing circuit which outputs the vertical drive signal VD, the horizontal drive signal HD, and the color subcarrier _SC to the output φ _{1 of the} signal source _1.
And a clock signal having a frequency four times that of the _SC is created. This 4 _SC clock signal is HD, VD and
Synchronized with _SC .

3 is a one line memory is assumed here that one line memory by the digital signal by a television signals phi ₁ and analog / digital conversion (A / D conversion). A /
The D converter is not shown. As the clock signal for the one-line memory 3, the aforementioned 4 _SC or a clock signal synchronized therewith is used. The one-line memory 3 stores the output signal φ ₁ of the signal source 1 for one line, thereby forming one horizontal scanning period (1
H) only because delays, the relationship between the television signal phi ₁ and the output signal phi ₃ both the one-line memory 3 is shifted 1H by one as shown in Figure 2. o, p, q, r, s... represent an appropriate horizontal scanning period in one field.
Is the end of the vertical flyback period, that is, the 21st H, and p is the 22H. Hereinafter, similarly, q is the 23rd H, r is the 24H, and s is the 25th.
H eyes. The contents of the video signal in each horizontal scanning period are A ₀ , A ₁ , A ₂ ,....

Reference numeral 4 denotes a comparator, which is an output television signal φ ₁ of the signal source _1.
And compared to the output television signal phi ₃ of one line memory 3 is 1H delayed by converting A / D, during the period in which both match, outputs a coincidence signal of the coincidence signal, for example a high level. Although the output of the comparator 4 changes by the length of one clock unit of the 4 _SC clock signal, the timing control circuit 5 ignores the coincidence signal in a narrow period and uses the coincidence signal in a longer period than a predetermined period. , And the AND gate 8 is controlled. For example, as shown in FIG. 3, a coincidence signal is always output during periods other than tq4 to tq5 of the pH and qH periods, and a coincidence signal having a short width is output during the period of tq4 to tq5. case, the high level signal is supplied from the timing control circuit 5 during the period t _q4 ~t _q5 to the aND gate 8,
The output signal of the signal source 1 becomes the output of the AND gate 8, and is alternately switched and supplied to the memory 7A or 7B by a signal from the timing control circuit 5 every horizontal scanning period.
That is, in the television signal of one line before the horizontal scanning period in FIG. 3 (a pH th) and the current horizontal scanning period (th first qH), in the partial t _q4 ~t _q5 but differentiated part the difference comprising a first qH th television signal (difference signal) phi ₈ of that is taken out as an output signal of the aND gate 8. This signal corresponds to C ₂ parts in Figure 2 phi _8. Similarly by comparing the first qH eyes and the television signal of the rH th, when taking out only part of the difference, a C ₃ in Figure 2 phi _8. Thereafter, the comparison is performed in increments of 1H, and only the portions having a difference are passed through the AND gate 8. This control is performed by the timing generation circuit 5 using the output of the comparator 4 and the output of the synchronous reproduction circuit 2.

The output of AND gate 8 is transmitted to AND gates 9A and 9B. The television signal of the part having a difference between the pH and the rH (the even H of the 22H, 24H ...) is the AND gate 9A.
Is stored in the memory 7A. Similarly, oH, qH, sH
The odd-numbered H signal of the (21H, 23H, 25H,...) Television signal is the AND gate 9B
Is stored in the memory 7B. That is, the switching output from the timing control circuit 5 applied to the AND gate 9A and the inverter 9R becomes a high level (low level) at the even H-th (odd H-th), and the AND gate 9A (9B) is turned on. Table 9R
Output becomes low level (high level) and AND gate 9B
(9A) is cut off. Therefore, the memory 7A is in the write mode at the even-numbered H and is in the read mode at the odd-numbered H, and the memory 7B is controlled by the output of the timing control circuit 5 so as to be reversed.

Next, writing to the memory 7B will be described. In Figure 3, phi ₁₀₁ and phi ₁₀₂ is first pH-th and the qH th signal, the qH
At the time of the eye, the television signals φ ₁₀₁ and φ ₁₀₂ (φ in FIG. 2)
When corresponding to A ₁ in A ₂ and phi ₃ in ₁₎ are compared and determined by the comparator 4 and there is a difference in the two signals in a portion of the _{t q4 ~t q5, t q4 ~t} q5
Written into the memory 7B the parts of the television signal or signals C ₂ portions in FIG. 2 phi ₈ at the timing t _q4 ~t _q5 shown in phi _102. The main 7B and memory capacity for one line, if the addressing and only the column direction, the second half of the memory of the signal C ₂ one line portion (FIG. 3 phi ₁₀₂ in t _q4 ~
(address corresponding to the position of t _q5 ). This writing position is stored in the timing control unit 5, and at the rH-th time,
As Figure 2 phi ₁₁ reads as a q'H th signal. That is, as in FIG. 2 phi _1, A ₀ of the signal of A ₁ of the first pH th th first oH
When When all different, the output of the AND gate 8 is C ₁ = A ₁ i.e., the output signal of the signal source 1 is stored as it is the memory 7A, IH late, first p'H in Figure 2 phi ₁₁ to the qH th It is read as the eye signal. That, different horizontal scanning period and a signal before the entire 1H, as shown in phi ₁ and phi _11, the overall signal from the OR gate 11 of one horizontal scanning period behind 1H is outputted.
P in Figure 2 _{φ 11 ', q', r} ' indicates that the 1H delayed than phi _1. The signal stored in the memory 7B at the qH-th time is φ
₂₀₂ or are read at the timing of t _q4 ~t _q5 of phi _'202. The read timing from the memory 7B is arbitrary within the corresponding 1H period.

On the other hand, the code signal indicating the whether those signals C ₂ of which position in the signal A ₂ of the second qH th original between t _q4 ~t _q5, for example, the position of the beginning t _q4 and end t _q5 to generate a code signal indicating the code signal forming circuit 6, between t _q1 ~t _q3 in FIG. 3, the horizontal sync pulse, if transmitted by inserting with color burst, this is detected at the receiving side, normal read at timing can from a ₁ and C ₂ is easily possible to synthesize a _2. Hereinafter, phi ₁₁ of FIG. 2 when subjected delivery is obtained alternately for the odd and even lines of the same operation. C ₁ (= A ₁ ) C ₃ ... in the memory 7A, C ₂ , C ₄ ... in the memory 7B
Are stored alternately.

It describes the formation of a second view of phi _11. In the rH eyes,
A ₂ in the output signal or phi ₃ of one line memory 3 and the signal source 1
To compare the output signal i.e. phi ₁ in A _3, the portion of the difference, the relevant portions of memory 7A of A ₃ through an AND gate 8
And the signal of q ′ is output from the OR gate 11. That is, read out signals C ₂ parts of A ₂ with the difference of A ₁ and A ₂ from the memory 7B. In FIG. 2, t _q0 to t _{q0 in} FIG.
_{q3, that} is, the display of the horizontal retrace period is omitted.
At the sH-th time, the output signal of the one-line memory 3, that is, A in the φ _3
3 and compares the signal source 1 output signal i.e. phi ₁ A ₄ in, for part of the difference, to conduct an AND gate 8, to store the corresponding part of the A ₄ to the memory 7B, a signal therebetween r ' Output from OR gate 11. That is, read out signals C ₃ portions of A ₃ with the difference A ₂ and A ₃ from the memory 7A. This is repeated thereafter.
The OR gate 10 passes the output signal of the memory 7A or 7B,
The gate 11 combines the output signal of the OR gate 10 and the code signal of the output of the code signal forming circuit 6 and passes the combined signal.
The signals ₂₀₁ , φ ₂₀₂ and φ ′ ₂₀₂ are formed.

Next, the formation of φ ₂₀₂ and φ ′ ₂₀₁ will be described.
₂₀₂ and φ ′ ₂₀₂ , the horizontal scanning portion other than t _{q4 to} t _q5 may be black or white, but is gray (intermediate value) here.
This level setting clamps the output of OR gate 10,
It can be easily changed by changing the clamp level.

Also, phi _'202 as may release the position of the signal t _q4 ~t _q5 from t _q3, may be each H changing this distance. t
a code signal indicating the distance _q3 ~t _q4 may be inserted between the t _q1 ~t _q2. Also, another digital signal in a portion other than t _q3 ~t _q4, can be transmitted by inserting an analog signal or the like (t _q11 ~t _q12). Also, the signal processing becomes slightly complicated,
As shown in Figure, signals of the differences from A _n and A _n1 C _n1, C _n2,
.. _{May be} plural, and the position information of C _n1 , C _n2 ,... _{May be} encoded and inserted into the same H signal. That is, in FIG.
t _n4 ~t _n5 part, t _n14 ~t _n15 of C _n1 is a part of the C _n2.
'code signal indicating the original position in the A _n of the signal C _n1 to _n4 ~t _n4, t' t indicating the original position in the A _n of the signal C _n2 to _n14 ~t _n14 and insert the code signal, the receiving side can insert C _n1, C _n2 in position of the original a _n of the signal by the code signal. These controls are performed by the timing control 5. 5 includes an MPU.

Next, a code signal in the case where the signal indicating the difference is one per 1H will be described with reference to FIG. FIG. 5 is an enlarged view of φ ′ ₂₀₂ of FIG. In FIG. 5, t _n1 is t
_q1 and t _n2 correspond to t _q2 . If a 1H signal is sampled with a 4 _SC clock signal, 910 samples will be obtained. _Tq3
Since the number of samples in the horizontal scanning period from to _tq6 is 512 or more, 10 bits are required as an address signal. As shown in Figure 5, represents the position of t _q4 in the phi ₂₀₁ in 10-bit a ₀ ~a _9, it represents the position of t _q5 in phi ₂₀₁ in 10-bit b ₀ ~b _9. The 6-bit c ₀ to c _5, showing the position of t _q4 of phi _'202 in 16 clock units of 4 _SC. That is, as phi _'202, if the time shift signals t _q4 ~t _q5, the 4 _SC 16
Even a roughness of about a clock (that is, about 1.1 μsec) does not hinder practical use. Therefore, in order to save the number of bits, 6 bits are used here. before and after a ₀ to c _5, the start, when adding one bit of stop, the total of 28 bits.
If the width of one bit is 1 / _SC ≒ 139.7nsec, 28 × 139.7
≒ 3.91μsec. Therefore, it is possible to allocate most of the NTSC-type synchronizing signal to the above 28 bits and to apply a horizontal synchronizing trigger to t _{n1 to} t _n8 as shown in FIG.

The synchronization signal and the burst signal are transmitted to the code signal forming circuit 6.
More may be sent continuously before and after a ₀ to c _5.

In the case of FIG. 4, t ' _{n4 to} t _n4 are unnecessary and t' _{n14 to} t ' _n14
What is _necessary is _just to put 28 bits in _n14 . If the difference between the signal of the previous horizontal scanning period and the signal of the current horizontal scanning period is transmitted and received and the remaining common part is not transmitted, the considerable horizontal scanning period in one field is shown in FIG. φ ′ ₂₀₂
, Other signals can be inserted _between tq11 and _tq12 . Generally, the television signal, because it contains considerably more of the same signal, need not signal synchronized with the screen can be sent using the t _q11 ~t _q12 in Figure 3 phi _'202. Such an additional signal can be generated by an additional signal forming circuit (not shown) controlled by the output of the timing control circuit 5 and sent out by supplying it to the OR gate 11.

As described above, the television signal compressed and added with the data signal by the signal processing circuit shown in FIG.
Transmission is performed after frequency conversion so as to conform to a broadcasting system such as ATV. For example, for satellite broadcasting, the bandwidth is 27MHz, 36MHz
As a _Ku band signal or _a Ka band signal having _a bandwidth of 100 MHz.

Next, a receiving device that receives a television signal transmitted from the above-described transmitting device will be described. If the broadcast signal transmitted from the transmitting device is, for example, a satellite broadcast,
K _u hand, the original UHF from the frequency of the K _a band, is converted to the VHF frequency level, is input to the receiver shown in Figure 6. FIG. 6 is a block diagram showing a configuration of a television receiver according to one embodiment of the present invention. In FIG. 6, reference numeral 21 denotes a video detection circuit, and reference numeral 22 denotes an A / D converter. Video detection circuit 21
Is input, for example, in FIG.
_In the video signal of a certain field as shown in ₂₀₂ , 1
Image signal compression processing is performed to delete the same video portion as the video signal before the field. Further to the signal of one field period is compressed, Fig. 3 signal period t _q4 ~t _q5 video signal C ₂ is the original first qH th signals of different time tq1~tq2 as shown in phi _'202 code signal indicating whether it is of any position in the a ₂ are inserted. Also, the period t
_q1 is the ~t _q2 code signal indicating whether video signals t _q4 ~t _q5 in this signal phi _'202 is inserted at any time have also been inserted.

The television signal including the image signal and the code signal that have been compressed as described above is supplied from the video detection circuit 21 to the synchronization separation circuit 23 and the chrominance subcarrier ( _SC ) reproduction circuit 24. Is the horizontal synchronization signal (drive signal)
Outputs a H _D and the vertical sync signal (drive signal) V _D, and outputs a color subcarrier _SC from _SC reproducing circuit 24. Horizontal, vertical synchronizing signals H _D, V _D and the color subcarrier _SC is input to the control logic 28 to be described later all. Since the sync separation circuit 23 and the _SC reproduction circuit 24 are already known, detailed description thereof is omitted here.

The television signal output from the video detection circuit 21 is converted into a digital signal by the A / D converter 22 and output to the first and second line memories 26 and 27. This digital television signal is input to the data processing circuit 29, and the code signal in one field is extracted and sent to the control logic 28. The control logic 28 receives the horizontal and vertical synchronizing signals H _D , V _D from the sync separation circuit 23, the color subcarrier _SC from the _SC reproduction circuit 24, and the code signal from the data processing circuit 29, as described above. first on the basis of the synchronizing signal H _D the timing information as a reference of the timing clock, the write clock of the image signal is outputted from the write control unit 30 to the second Rainmomeri 26, 27 and the third Rainmomeri 25, and,
The read control unit 31 outputs a read clock. In FIG. 6, 32, 33, 36, 37 are AND gates, 34, 38
Is an OR gate, 35 and 39 are inverters, 40 is a reproduction circuit including a D / A converter for digital-to-analog (D / A) conversion of the digital television signal output from the OR gate 14, and 41 is a D / A converter A cathode ray tube (CRT) for reproducing and displaying an output television signal of the device reproducing circuit 40.

The operation of the receiving apparatus of the present embodiment configured as described above will be described below with reference to FIGS. 7 and 8.

7 and 8, the received signal is a vertical blanking period (VBL) before OH (horizontal period: 21H), and a video signal starts from pH (22H). still,
This video signal is shown corresponding to the video signal in the transmission device shown in FIGS.

Now, 21 of the video signals input to the video detection circuit 21
The H signal is first written to the line memory 25, and in this state, the video signal from the A / D converter 22 is supplied to the line memory 26. The line memory 25 is written is zero code indicating that no video signal component from the time t ₃ ~t ₆ signal components or control logic 28 of 21H.

22H signal φ ₃₀₁ partially omitted (Fig. 3, φ ₂₀₁ )
In, As described in the foregoing embodiments of the transmission device, the period t ₁ ~t ₂ is inserted code signal indicating whether the video signal differs from the video signal of 21H is inserted at the timing of the 22H throat This code signal is extracted from the signal φ _{301 by the} data processing circuit 29 and the control logic 2
Dispatched 8, from further control logic 28 controls to high-level signal to execute the 22H of t ₃ ~t ₆ period a write operation from the write control unit 30 to the line memory 26 (write clock) is output A control signal is provided. As a result, as shown in FIG.
Video signal component (period t ₃ ~t ₆₎ φ ₃₀₁ of is written.
When τ = 1/4 _SC during the period t _{1 to} t ₃ , one bit 8
This is a code signal having a length for each τ.

On the other hand, at 22H, a control signal for driving the read control unit 31 is supplied from the control logic 28, and a read clock is supplied from the read control unit 31 to the line memory 25. In addition, the output of the read control unit 31 turns on the AND gate 32, and the output inverted by the inverter 35 shuts off the AND gate 33. Accordingly, during the period 22H, the output of the OR gate 34 outputs the memory content of the line memory 25, and is zero, and new zero data is written through the feedback loop. In addition, the line memory 25
Between 262H from 22H (or 263H), the write clock is supplied from the write control unit 30 over a period t ₃ ~t _6.

Next, the case where a 23H signal (FIG. 8, φ ₄₀₂ ) is received will be described. In the following description, the description will be made ignoring the phase difference between the output of the line memory 26 and the input of the write clock to the line memory 25. The technique of transferring data from a memory to a next-stage memory with a phase difference belongs to the well-known art, and a description thereof will be omitted.

The 23H video signal (φ _{402 in} FIG. 8) transmitted from the transmitter and indicating the difference between the 23H video signal before the partial omission processing and the 22H video signal is transmitted in the same manner as in the case of 22H described above.
After passing through the A / D converter 22, the video signal component (the component of φ ₄₀₂ during the period from t ₃ to t ₆ ) is written into the line memory 27. Two
3H video signal during writing into the line memory 27, read out the written video signal in 22H (φ ₃₀₁₎ from the line memory 26. At this time based on the memory of the control logic 28 22H code signal stored in the (not _{shown) (t 1 ~t 2),} t 3 of the signals in the line memory 26 (image signal phi ₃₀₁ ~
t ₆ ) are all transferred to the line memory 25 and controlled to output.

That is, the write control unit 31 supplies the AND gate 32 with φ ₁₁
(FIG. 6), a low level signal is supplied to the AND gate 3.
2 is shut off. On the other hand, the output of the inverter 35 becomes an inverted signal i.e. a high level signal phi _11, the AND gate 33 becomes conductive. Similarly, high-level signal of the control signal phi ₁₂ from the write control unit 31 is supplied to the AND gate 36, AND gate 36 is rendered conductive. On the other hand, the AND gate 37 by the inverter 39 outputs the inverted signal phi ₁₂ is interrupted. Thus, the output of OR gate 38 is the output of the line memory 26 over the seventh FIG period T ₂₃₀ through T _240. Of course, it goes without saying that the read clock is continuously supplied to the line memory 26 during this time.

In this way, the received signal is 23H, i.e., a video signal of period t ₃ ~t ₆ in Figure 8 phi _402, t ₃ in FIG. 7 T ₂₃₀ through T _240, during the video signal phi ₃₀₁ from the line memory 26 ~t ₆ is read from the line memory 26, sequentially through the aND gate 36 → OR gate 38 → aND gate 33 → OR gate 34 is output to the CRT41 is converted into an analog video signal by the D / a converter 40 . At this time OR
The output of the gate 34, that is, t ₃ to t ₆ of the video signal φ ₃₀₁ is
The data is written to the line memory 25 via a feedback loop.

Here, supplementary explanation relates to Figure 7, Figure 7 T ₂₃₀ is
While corresponding to the time t ₀ of 23H, signals between t ₀ ~t ₃ are not shown in in FIG. 7. Omission of this description does not hinder the description of the operation of this embodiment. Hereinafter, the same applies to 24H, 25H.

Next, an operation when a 24H signal is input as a reception signal will be described. The waveform of the input signal of 24H is not shown.

24H video signal (Fig. 7 T ₂₄₀ through T ₂₅₀₎ is written in the line memory 26 by the write control of the control logic 28. At this time, the control signal φ ₁₂ from the read control unit 31 is
This is a low level signal. Therefore, in the 24H, the AND gate 36 is cut off, the AND gate 37 is rendered conductive by the low level signal phi _12.

The received signal 23H, a period t ₁ ~t ₂ of the signal phi ₄₀₂ 23
H (read at the 24th H in FIGS. 7 and 8) includes a code signal indicating at which timing the video signal is inserted. This code signal is decoded by the data processing circuit 29 as described above, and as a result, a control signal is input from the control logic 28 to the write control unit 30 and the read control unit 31,
A clock is output to each of the line memories 25, 26, and 27, and a control signal shown in FIG. 7 is output from the read control unit 31 to each gate or the inverters 32, 33, 35, 36, 37, and 39. You.

Based on this code signal, the read clock only during Figure 7 T ₂₃₄ '~T _235' is supplied to the line memory 27 in 24H, T ₂₄₀ except T ₂₃₄ '~T _235' to the line memory 25 ( = T ₂₃₀ ′) to T ₂₅₀ (= T ₂₄₀ ′), the read clock is supplied.

Control signal phi _11, based on the code signal 23H stored in the memory in the control logic 28, the 24H, T ₂₄₀
Through T ₂₃₄ 'and T _235' high level T ₂₃₄ in through T ₂₅₀ 'through T
Low level at ₂₃₅ '.

Accordingly, in the period from T _{240 to} T ₂₃₄ ′, the control signal φ ₁₁ sets the AND gate 32 to the conductive state and the AND gate 33 to the cut-off state, and the signal read from the line memory 25 to which the read clock is supplied, that is, 8 video signals t ₃ ~t ₄ periods of FIG phi ₃₀₁ is, from the line memory 25 through the aND gate 32, OR gate 34, D / a converter 40, is outputted to the CRT 41.

Next, the T ₂₃₄ '~T _235' period, the control signal phi ₁₁ of low level, the AND gate 32 is cut off, the AND gate 33 is set in a conducting state. As a result, the read signal from the line memory 27 during the supply of the read clock T ₂₃₄ '~T _235', i.e. the video signals t ₄ ~t ₅ period eighth FIG phi ₄₀₂ is, the AND gate 37 → OR Gate 38 → AND gate 33 → OR gate
The signal is input to the D / A converter 40 via 34 and output to the CRT 41. The signal read from the line memory 27 is written to the line memory 25 via a feedback loop as in the case described above.

Next, in the period from T ₂₃₅ ′ to T ₂₅₀ , the high-level control signal φ
By _11, the AND gate 32 is rendered conductive, and the AND gate 33 is set to the cutoff state, t ₅ ~t ₆ therebetween video signal read from the supplied and are line memories 25 of the read clock, i.e. FIG. 8 phi ₃₀₁ The video signal for the period is
From the AND gate 32 to the OR gate 34, the D / A converter 40, and C
Output to RT41. The video signal read from the line memory 25 is written into the line memory 25 through a feedback loop in the same manner as described above.

As described above, with respect to 22H of the received signal, the original signal of 23H to only t ₄ ~t ₅ parts of a 8 Figure phi ₄₀₂ is different from the eighth
It is restored at 24H as shown in Fig. ₃₀₂ . At this time, the storage contents of the line memory 25 are as shown in FIG.
₃₀₁ t ₃ ~t ₆ period of the video signal (T ₂₃₀ of FIG. 7 memory 25 through T
₂₄₀ is a horizontal portion) of the hatched portion of the t ₄ ~t ₅ periods of the video signal in Fig. 8 phi ₄₀₂ to the storage contents (T ₂₃₄ of FIG. 7 memory 25 'through T _235' at 23H in 24H ) Is the rewritten video signal.

On the other hand, the line memory 26 is in the writing state as described above, and the reception signal of 24H is written. As a result, a signal indicating the difference between the original video signal of 23H and the original video signal of 24H (No. 7)
The 24H cross hatch of the received signal in the figure) is the line memory 26.
Is written to.

By the same operation as the restoration of the 23H original video signal at the 24H, the 24H original video signal is restored at the 25H, and the original image is reproduced on the CRT ₄₁ by repeating the same operation.

Next, for example, the eighth signal included in the signal received by the receiver
Figure phi _301, an example of a code signal t ₁ ~t ₂ period of phi _402, will be described with reference to FIG. 9.

In FIG. 9, t ₁ ~t ₁₃ is a horizontal synchronizing signal by a combination of "1" and "0", t ₁₃ ~t ₂₀ is a code signal described above. Incidentally t ₂₀ in FIG. 9 corresponds to FIG. 8 time t _2. the next "1" of t ₁₃ is a start bit, this bit is always "1". The next “x” indicates that the signal on that line is
This bit indicates whether the signal includes a part of the original video signal (partial signal) or the signal (all signals) including the entire original video signal for one line. If "0", it is a partial signal, and if "1", it is a full signal. In the previous embodiment, the 22H signal phi ₃₀₁ "x" is "1", 23H, the receiving signal of 24H is "x" is "0". The "x" followed by bit, 7-bit a ₀ ~a ₆ is a code bit indicating whether the head of the video signal to which timing in the television signal to be restored at the receiving side is located, for example, the 8φ
From t ₁ of ₃₀₂ is a code bit indicating the length of t _4. Then, a ₀ ~a 7 bits b ₀ ~b ₆ following the ₆ bits, the code bit indicating whether the rear end of which timing the video signal in the television signal to be restored on the receiving side is located There is a code bit indicating the length of the t _5, for example, from t ₁ in Figure 8 phi _302. b ₀ 6-bit ~b ₇ following the bit c ₀ to c ₅ is an encoded bit indicating whether the head is located in what timing the video signal in the television signal partially omitted processed at the transmitting end , for example, t ₄ from t ₁ in FIG. 8 phi ₄₀₂
Is a code bit indicating the length of. Furthermore, 6-bit d ₀ to d ₅ following the c ₀ to c ₅ bit code indicating the head is positioned in another data code signal to which timing in television signal is compressed at the transmitting end a bit, a code bit indicating the length of t _11, for example, from t ₁ in Figure 8 phi _402. “1” at t _{19 to} t ₂₀ is a stop bit.

1H from t ₀ of the television signal shown in FIG. 8 to t ₆
Is about 63.5 μs for an NTSC signal, and when this is sampled at 4 _SC , 910 samples are obtained. Therefore, t _{1 to} t ₅
There is no practical problem even if the lower 3 bits of t _{1 to} t ₆ are omitted and expressed by 7 bits. On the other hand, for t _{1 to} t ₁₁ , the lower 4 bits of the 10 bits are discarded, and t ₁ to t ₁₁ are (1/4 _SC ) × 16 with the upper 6 bits.
決 め る Determine in 1.12μs steps. t ₁ ~t ₅ and t ₁ ~t ₆ are according to the screen, but it is better to be determined in one sample increments, no problem even practically 8 sample units (about 0.56μs). t _{11 to} t
Another data location ₁₂ is not necessary to determine precisely, since t ₁₁ is sufficient knowing, determined at 16 sample units. Sixth
In the data processing circuit 29 in the figure, data of t13 to t19 and t
₁₁ performs the extraction process both data of ~t _12. t _{11 to} t ₁₂
Includes a code indicating a data length or start and stop bits. Incidentally, Supplementally, t ₁ ~t ₁₅ is as Figure 9, a 32-fold t ₁₄ ~t _15, t
When the ₁₄ ~t ₁₅ and _{1/2 SC ≒ 139.7ns, 32 × 139.7ns} ≒ 4.
47 μs, which is smaller than the width of the horizontal synchronization signal of NTSC. Thus, even without moving the color burst may be replaced a horizontal synchronization signal t ₁ ~t ₁₅ of Figure 9. t ₁₃ the highest frequency component of ~t ₂₀ falls within the transmission band of the _SC, and the normal NTSC (In general television, the amplitude is 1/2, the processing on the trouble free.).

As described above, according to the present embodiment, even if only a part of the signal including a part different from the previous line is transmitted, the original image on the transmitting side can be accurately reproduced on the receiving side. In this case, a ₀ ~a ₆ of FIG. _{9, b 0 ~b 6, c 0} ~c 5, d 0 ~d 5 to performs certain processing, the transformation procedure, while only know specific party further If it does, secret story (picture) transmission is possible.

In the above example, the signal processing in line units has been described. However, it is of course possible to make each line memory in FIG. 6 a field memory or a frame memory and perform the same processing in field or frame units. Of course, it is easy to combine the unit processing with the field or frame unit processing.

In the D / A converter 40, it goes without saying that processing is performed so that the phase relationship between the color subcarrier and the color signal output from the line memory 25 becomes normal. As is well known, the color subcarrier is inverted every horizontal scanning period, but the color signal of the line memory 25 is not inverted. In addition, since the signals are synthesized with a plurality of lines of signals and stored in the line memory 25, a color signal of a certain portion can be color-demodulated using the color subcarrier of the horizontal scanning period as it is, It is also known that color demodulation can be correctly performed on a portion by inverting and using the color subcarrier. However, in which part the color sub-conveyance needs to be inverted, the signal of each horizontal scanning line is stored in the line memory 26 or 27 and transferred to the line memory 25 in the small-capacity memory in the control logic 28. , The start and end of the address in the horizontal direction, and one bit indicating whether or not the color subcarrier is inverted may be stored. Inversion or non-inversion may be based on, for example, the 21H-th scanning line.
All of these processes can be realized by a combination of known techniques. Another method is to take out the color signal components in the outputs of the line memories 26 and 27 by YC separation and extract them, and perform inversion or non-inversion processing so that they become the same as the color signal components of the video signal stored in 25. Therefore, the color signal components in the memory 25 can be color-demodulated by the color subcarriers having the same phase. In this case, one bit indicating the relationship between the color signal component and the color sub-carrier in the memory 25 is supplied from the control logic 28 to the D / A converter 40, and the inversion or non-inversion of the color sub-carrier may be determined.

Effects of the Invention According to the present invention, only a difference between a video signal of a certain line and a video signal of a line following the certain line or a portion including the same portion is transmitted, and a system for reproducing the same is provided. ) Secret transmission of image communication with a specific partner can be easily performed.

(2) Data other than images can be sent at the same time.

(3) The synchronizing signal is deformed and cannot be seen by a normal television receiver unless the synchronizing signal is restored based on the data.

(4) If the video is inverted, the screen becomes more difficult to understand.

Thus, it is possible to realize a television transmission / reception device that is particularly effective for confidential transmission.

[Brief description of the drawings]

FIG. 1 is a block diagram of a signal processing circuit of a television signal transmitter according to one embodiment of the present invention, and FIGS. 2, 3, 4, and 5 are diagrams for explaining the operation of the television signal transmitter. FIG. 6 is a block diagram of a television signal receiver according to one embodiment of the present invention, and FIGS. 7, 8, and 9 are waveforms for explaining the operation of the television signal receiver. FIG. 1 ... signal source, 2 ... synchronous reproduction circuit, 3 ... 1 line memory, 4 ... comparator, 5 ... timing control circuit, 6 ...
… Code signal forming circuit, 7A, 7B …… Buffer memory, 8, 9
A, 9B …… AND gate, 10,11 …… OR gate, 25,26,27 ……
Line memory 28 control logic 29 data processing circuit 30 write control unit 31 read control unit 32 3
3,36,37 …… AND gate, 34,38 …… OR gate, 35,39 ……
Inverter.

Claims (6)

(57) [Claims] 1. A television signal is divided into horizontal scanning lines, and a video signal Vn in an nth horizontal scanning period and a video signal in an (n-1) th horizontal scanning period in one field.
Vn-1 and, when a part or all of the two video signals are different, the signal Vx of a part of the video signal Vn that includes a part different from the video signal Vn-1 or a part including before and after the different part, A transmitter that sends a signal in which the width of the horizontal synchronization signal is narrowed by bringing the trailing edge of the horizontal synchronization signal closer to the leading edge, and separately detects the leading edge of the horizontal synchronization signal of the television signal sent from the transmitter, The color subcarrier is reproduced, and a drive signal to the memory is generated from the control logic unit for controlling the memory circuit, and the video signal Vn-1 and the nth video signal in the (n-1) th horizontal scanning period of the television signal are generated. The video signal Vx of the horizontal scanning period is input, and the video signal Vx is mixed, superimposed, replaced or calculated with a part or all of the video signal Vn-1 to reproduce the video signal Vn of the nth horizontal scanning period. And a television signal receiver that performs That television signal transmitting and receiving device. 2. A television signal is divided into horizontal scanning lines, and a video signal Vn in an n-th horizontal scanning period and a video signal in an (n-1) -th horizontal scanning period in one field.
Vn−1, and when a part or all of the two video signals are different, only the video signal Vx of the portion of the video signal Vn that is different from the video signal Vn−1 or the same Vn as Vn−1 A television signal transmitter for transmitting a signal including a part of the horizontal synchronization signal, wherein the width of the horizontal synchronization signal is reduced by bringing the trailing edge of the horizontal synchronization signal closer to the leading edge. 3. The video signal Vn-1 of the television signal transmitted from the television signal transmitter according to claim 1 in the (n-1) th horizontal scanning period and the video signal in the nth horizontal scanning period. The signal Vx is input and the video signal Vx is converted to the video signal Vn−
A television signal receiver that reproduces a video signal Vn in an n-th horizontal scanning period by mixing, superimposing, replacing, or calculating a part or the whole of one. 4. A video signal Vx of a different portion between a video signal Vn-1 in the (n-1) th horizontal scanning period and a video signal Vn in the nth horizontal scanning period in one field of the television signal. A first line memory that stores only Vn or a part of Vn that is the same as Vn−1, a video signal Vn of the nth horizontal scanning period, and a video signal of the (n + 1) th horizontal scanning period
A second line memory for storing the video signal Vx + 1 of a different part of Vn + 1, a reproduced video signal V'x reproduced from the video signal Vn-1 and the video signal Vx, and a reproduced video signal V'x reproduced from the reproduced video signal V'x and the video signal Vx + 1 The television signal receiver according to claim 3, further comprising a third line memory that sequentially stores the reproduced video signal V'x + 1. 5. When the received television signal is in the nth horizontal scanning period, a video signal is formed from the contents stored in the first line memory and the third line memory, and the (n-1) th horizontal signal is formed. 5. The television signal receiver according to claim 4, wherein a video signal is formed from the stored contents of the second line memory and the third line memory during a scanning period. 6. A device according to claim 3, further comprising means for receiving and decoding a data signal superimposed on part or all of a horizontal scanning period of an image display portion of a television signal.
Or the television signal receiver according to (5).