JP2869907B2 - Connection structure of semiconductor device - Google Patents

Connection structure of semiconductor device

Info

Publication number
JP2869907B2
JP2869907B2 JP3338013A JP33801391A JP2869907B2 JP 2869907 B2 JP2869907 B2 JP 2869907B2 JP 3338013 A JP3338013 A JP 3338013A JP 33801391 A JP33801391 A JP 33801391A JP 2869907 B2 JP2869907 B2 JP 2869907B2
Authority
JP
Japan
Prior art keywords
layer
opening
semiconductor device
film carrier
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3338013A
Other languages
Japanese (ja)
Other versions
JPH05152376A (en
Inventor
義裕 河村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KASHIO KEISANKI KK
Original Assignee
KASHIO KEISANKI KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KASHIO KEISANKI KK filed Critical KASHIO KEISANKI KK
Priority to JP3338013A priority Critical patent/JP2869907B2/en
Publication of JPH05152376A publication Critical patent/JPH05152376A/en
Application granted granted Critical
Publication of JP2869907B2 publication Critical patent/JP2869907B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • H01L2224/05559Shape in side view non conformal layer on a patterned surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05575Plural external layers
    • H01L2224/0558Plural external layers being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • H01L2224/13006Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は半導体装置の接続構造
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection structure for a semiconductor device.

【0002】[0002]

【従来の技術】半導体装置の分野では、電極を有し、I
Cチップ等からなる半導体装置をフィルムキャリア上に
搭載することがある。この場合、フィルムキャリアは、
一般に、ポリイミド等の樹脂からなるフィルム基板の上
面にパターン形成された導電層を保護したり絶縁性を確
保したりするために、導電層を含むフィルム基板の上面
全体に絶縁層が設けられた構造となっている。
2. Description of the Related Art In the field of semiconductor devices, electrodes having electrodes are used.
A semiconductor device composed of a C chip or the like may be mounted on a film carrier. In this case, the film carrier
Generally, a structure in which an insulating layer is provided on the entire upper surface of a film substrate including a conductive layer in order to protect a conductive layer patterned on the upper surface of a film substrate made of a resin such as polyimide or to secure insulation. It has become.

【0003】ところで、このようなフィルムキャリア上
に半導体装置を搭載する場合、導電層の所定の個所に対
応する部分の絶縁層に平面方形状の開口部を形成し、こ
の開口部を介して露出された導電層に半導体装置の電極
を半田を介して接続することにより、フィルムキャリア
上に半導体装置を搭載するようにしている。この場合、
平面方形状の開口部を有する絶縁層を形成する方法とし
てスクリーン印刷がある。このスクリーン印刷によれ
ば、フィルム基板上に所定パターンを有したスクリーン
マスクを一定の間隔をおいて平行に配置し、スキージで
スクリーンマスクを押え付けて絶縁性インクを押し出す
という一工程で、フィルム基板上等に平面方形状の開口
部を有する絶縁層を簡単にかつ短時間で形成することが
できる。
When a semiconductor device is mounted on such a film carrier, a planar rectangular opening is formed in a portion of the insulating layer corresponding to a predetermined portion of the conductive layer, and the opening is exposed through the opening. The semiconductor device is mounted on the film carrier by connecting the electrode of the semiconductor device to the conductive layer thus formed via solder. in this case,
Screen printing is known as a method for forming an insulating layer having a planar rectangular opening. According to this screen printing, a screen mask having a predetermined pattern is arranged in parallel on a film substrate at a predetermined interval, and the squeegee presses the screen mask to extrude the insulating ink. It is possible to easily and quickly form an insulating layer having an opening having a flat rectangular shape on an upper side.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、従来の
このようなフィルムキャリアでは、絶縁性インクが粘性
を有しているので、印刷直後における絶縁層ににじみが
生じ、またスキージでスクリーンマスクを押え付けてい
るので、スクリーンマスクが伸縮して印刷位置にずれが
生じ、このようなことから開口部の大きさとして200
μm角程度が限界であり、またそのピッチも400μm
程度が限界である。したがって、半導体装置の電極をよ
り一層微細化することができても、このようなフィルム
キャリアには搭載することができないという問題があっ
た。この発明の目的は、スクリーン印刷による絶縁層を
有するフィルムキャリアに、より一層微細化した電極を
有する半導体装置を搭載することのできる半導体装置の
接続構造を提供することにある。
However, in such a conventional film carrier, since the insulating ink has viscosity, bleeding occurs in the insulating layer immediately after printing, and the screen mask is pressed with a squeegee. , The screen mask expands and contracts, causing a shift in the printing position.
The limit is about μm square, and the pitch is 400 μm
Degree is the limit. Therefore, there is a problem that even if the electrodes of the semiconductor device can be further miniaturized, they cannot be mounted on such a film carrier. An object of the present invention is to provide a connection structure of a semiconductor device in which a semiconductor device having further miniaturized electrodes can be mounted on a film carrier having an insulating layer formed by screen printing.

【0005】[0005]

【課題を解決するための手段】この発明は、電極上に半
田バンプを有する半導体装置と、フィルム基板の上面に
パターン形成された導電層の上面のうち絶縁層開口部を
形成すべき開口部形成領域内で少なくともその周囲にフ
ォトレジスト層を設け、前記開口部形成領域以外の領域
にスクリーン印刷により絶縁層を形成し、この後前記フ
ォトレジスト層を剥離することにより、前記絶縁層に前
記開口部形成領域に対応した開口部が形成されたフィル
ムキャリアとを具備し、前記半導体装置の前記半田バン
プを前記フィルムキャリアの前記開口部における前記導
体層に接続したものである。
SUMMARY OF THE INVENTION The present invention relates to a semiconductor device having a solder bump on an electrode, and an opening for forming an insulating layer opening on an upper surface of a conductive layer patterned on an upper surface of a film substrate. A photoresist layer is provided at least around the inside of the region, an insulating layer is formed by screen printing in a region other than the opening forming region, and then the photoresist layer is peeled off to form the opening in the insulating layer. A film carrier having an opening corresponding to the formation region, wherein the solder bumps of the semiconductor device are connected to the conductor layer in the opening of the film carrier.

【0006】[0006]

【作用】この発明によれば、開口部形成領域内で少なく
ともその周囲に微細パターン形成可能なフォトレジスト
層を形成した状態で開口部形成領域以外の領域にスクリ
ーン印刷により絶縁層を形成したフィルムキャリアを用
いているので、フォトレジスト層の端面で印刷範囲が規
制されることにより、開口部の大きさおよびそのピッチ
をより一層微細化することができ、したがってスクリー
ン印刷による絶縁層を有するフィルムキャリアに、より
一層微細化した電極を有する半導体装置を搭載すること
ができる。
According to the present invention, a film carrier in which an insulating layer is formed by screen printing in a region other than the opening forming region while a photoresist layer capable of forming a fine pattern is formed at least around the opening forming region. Because the printing range is regulated by the end face of the photoresist layer, the size of the opening and the pitch thereof can be further miniaturized, and therefore, a film carrier having an insulating layer formed by screen printing can be used. In addition, a semiconductor device having further miniaturized electrodes can be mounted.

【0007】[0007]

【実施例】図1はこの発明の一実施例における半導体装
置とフィルムキャリアの接続前の状態を示したものであ
る。半導体装置1は、装置本体2の下面にAl等からな
る電極3がパターン形成され、電極3の下面の所定の一
部を除く全下面に保護膜4が設けられ、電極3の露出面
上に、TiとWとからなる合金の下面にCuを積層して
なるもの等からなるアンダーバンプメタル5が設けら
れ、アンダーバンプメタル5の下面にCu等からなる金
属層6が設けられ、金属層6等の周囲に半田バンプ7が
設けられた構造となっている。フィルムキャリア11
は、後で詳述するが、フィルム基板12の上面にパター
ン形成された導電層13の上面のうち開口部14を形成
すべき開口部形成領域にフォトレジスト層を設け、開口
部形成領域以外の領域にスクリーン印刷により絶縁層1
5を形成し、この後フォトレジスト層を剥離することに
より、絶縁層15に開口部形成領域に対応した開口部1
4が形成され、該開口部14における導電層13上に半
田層16が設けられた構造となっている。そして、半導
体装置1の半田バンプ7をフィルムキャリア11の半田
層16に接合すると、図2に示すように、両半田層7、
16が溶融して一体化した後固化することにより、半田
バンプ7が導電層13に接続され、すなわち半導体装置
1がフィルムキャリア11上に搭載される。
FIG. 1 shows a state before connection between a semiconductor device and a film carrier according to an embodiment of the present invention. In the semiconductor device 1, an electrode 3 made of Al or the like is pattern-formed on the lower surface of the device main body 2, and a protective film 4 is provided on the entire lower surface of the lower surface of the electrode 3 except for a predetermined part. , An under bump metal 5 made of, for example, a laminate of Cu on the lower surface of an alloy made of Ti and W, a metal layer 6 made of Cu or the like is provided on the lower surface of the under bump metal 5, And the like, and a solder bump 7 is provided around the same. Film carrier 11
As will be described in detail later, a photoresist layer is provided in an opening forming region where an opening 14 is to be formed on the upper surface of the conductive layer 13 patterned on the upper surface of the film substrate 12, and a photoresist layer other than the opening forming region is provided. Insulation layer 1 by screen printing on the area
5 is formed, and then the photoresist layer is peeled off, so that the insulating layer 15 has openings 1 corresponding to the opening forming regions.
4 is formed, and a solder layer 16 is provided on the conductive layer 13 in the opening 14. Then, when the solder bumps 7 of the semiconductor device 1 are joined to the solder layers 16 of the film carrier 11, as shown in FIG.
The solder bumps 7 are connected to the conductive layer 13 by solidification after being melted and integrated, that is, the semiconductor device 1 is mounted on the film carrier 11.

【0008】次に、フィルムキャリア11の構造につい
て図3〜図8を参照しながらその製造方法と併せ説明す
る。まず、図3に示すように、ポリイミド等の樹脂から
なるフィルム基板12の上面に導電層13をパターン形
成する。この場合、フィルム基板12の全面にスパッタ
リング法、無電解メッキ法、接着剤を用いたラミネート
法等によって導電膜を設け、その後この導電膜をエッチ
ングすることにより導電層13を形成するようにしても
よいが、銅箔等からなる長尺の導電膜にポリイミド等の
樹脂のワニスをコーティングするキャスティング法によ
りその導電膜の表面にフィルム基板12を設け、その後
同様にこの導電膜をエッチングすることにより導電層1
3を形成する方が耐熱性の面において好ましい。次に、
図4に示すように、全表面に厚さが例えば50μm程度
のフォトレジスト層21を設ける。この場合、ネガ型の
フィルム状フォトレジストを熱圧着してもよく、またネ
ガ型の液状フォトレジストをロールコート等により塗布
してもよい。次に、導電層13の上面のうち例えば10
0μm角の開口部14(図1参照)を形成すべき開口部
形成領域22に対応する所定のパターンのフォトマスク
を用いて紫外線等の光を照射し、開口部形成領域22に
対応する部分のフォトレジスト層21を露光する。この
後、現像すると、開口部形成領域22以外の不要な部分
のフォトレジスト層21が剥離され、開口部形成領域2
2のみにフォトレジスト層21が残存する。次に、開口
部形成領域22よりやや大きめの島状パターンを有する
スクリーンマスク(図示せず)および絶縁性インクを用
いてスクリーン印刷を行うことにより、図5に示すよう
に、フォトレジスト層21およびその周囲を除く全表面
に絶縁性インク層23を10〜25μm程度の厚さに塗
布する。この場合、スクリーンマスクの島状パターンの
大きさは、絶縁性インクの粘度にもよるが、開口部形成
領域22の大きさ100μm角よりも各辺で20〜30
μm程度大きくしておく。絶縁性インクとしては、エポ
キシ系樹脂を有機溶剤に溶かしたものを用いる。この
後、ある程度放置すると、絶縁性インク層23が流動し
て広がるが、図6に示すように、フォトレジスト層21
の端面で堰き止められ、フォトレジスト層21を除く全
表面が絶縁性インク層23によって覆われることにな
る。次に、絶縁性インク層23を乾燥してその厚さを1
0〜20μm程度とした後フォトレジスト層21を剥離
すると、図7に示すように、開口部形成領域22に対応
する部分に開口部14を有する絶縁層15が形成され
る。次に、図8に示すように、開口部14における導電
層13上に半田層16を形成する。この場合、半田層1
6の厚さは、その表面が絶縁層15の表面以下となるよ
うにしてもよいが、絶縁層15の表面と同一かもしくは
それ以上となるようにすると、接続信頼性を高めること
ができる。半田層16の形成方法は、電気メッキや印
刷、成形半田使用等のいずれであってもよい、かくし
て、開口部14を有する絶縁層15を備えたフィルムキ
ャリア11が製造される。
Next, the structure of the film carrier 11 will be described with reference to FIGS. First, as shown in FIG. 3, a conductive layer 13 is patterned on the upper surface of a film substrate 12 made of a resin such as polyimide. In this case, a conductive film may be formed on the entire surface of the film substrate 12 by a sputtering method, an electroless plating method, a laminating method using an adhesive, or the like, and then the conductive layer may be formed by etching the conductive film. It is preferable to provide a film substrate 12 on the surface of the conductive film by a casting method in which a long conductive film made of a copper foil or the like is coated with a varnish of a resin such as a polyimide, and then similarly etch the conductive film to form a conductive film. Layer 1
Forming 3 is preferable in terms of heat resistance. next,
As shown in FIG. 4, a photoresist layer 21 having a thickness of, for example, about 50 μm is provided on the entire surface. In this case, a negative film photoresist may be thermocompression bonded, or a negative liquid photoresist may be applied by roll coating or the like. Next, for example, 10
Irradiation with light such as ultraviolet light is performed using a photomask having a predetermined pattern corresponding to the opening forming region 22 where the opening 14 (see FIG. 1) of 0 μm square is to be formed. The photoresist layer 21 is exposed. Thereafter, when development is performed, unnecessary portions of the photoresist layer 21 other than the opening forming region 22 are peeled off, and the opening forming region 2 is removed.
2 only, the photoresist layer 21 remains. Next, by performing screen printing using a screen mask (not shown) having an island-like pattern slightly larger than the opening forming region 22 and an insulating ink, as shown in FIG. An insulating ink layer 23 is applied to the entire surface except the periphery to a thickness of about 10 to 25 μm. In this case, although the size of the island pattern of the screen mask depends on the viscosity of the insulating ink, the size of the opening forming region 22 is more than 20 to 30 μm on each side than the size of 100 μm square.
Increase the size by about μm. As the insulating ink, one obtained by dissolving an epoxy resin in an organic solvent is used. After that, if left to some extent, the insulating ink layer 23 flows and spreads, but as shown in FIG.
And the entire surface except the photoresist layer 21 is covered with the insulating ink layer 23. Next, the insulating ink layer 23 is dried to reduce its thickness to 1.
When the photoresist layer 21 is peeled off after the thickness is set to about 0 to 20 μm, an insulating layer 15 having an opening 14 at a portion corresponding to the opening forming region 22 is formed as shown in FIG. Next, as shown in FIG. 8, a solder layer 16 is formed on the conductive layer 13 in the opening 14. In this case, the solder layer 1
The thickness of 6 may be such that its surface is equal to or less than the surface of the insulating layer 15, but if it is equal to or greater than the surface of the insulating layer 15, the connection reliability can be improved. The method of forming the solder layer 16 may be any method such as electroplating, printing, or using molded solder. Thus, the film carrier 11 including the insulating layer 15 having the opening 14 is manufactured.

【0009】このようにして製造されたフィルムキャリ
ア11では、開口部形成領域22に微細パターン形成可
能なフォトレジスト層21を形成した状態で開口部形成
領域22以外の領域にスクリーン印刷により絶縁層14
を形成しているので、フォトレジスト層21の端面で印
刷範囲を規制することができ、このため印刷直後におけ
る絶縁性インク層23が所定の絶縁層15を形成すべき
領域以外ににじみ出るのを防止することができ、またス
クリーンマスクが伸縮して印刷位置に若干のずれが生じ
ても、絶縁性インク層23の粘性を利用することにより
所定の絶縁層15を形成すべき領域のみに絶縁層15を
形成することができ、したがって例えば開口部14の大
きさを100μm、そのピッチを200μm程度とより
一層微細化することができる。したがって、スクリーン
印刷による絶縁層15を有するフィルムキャリア11
に、より一層微細化した電極を有する半導体装置1を搭
載することができる。
In the film carrier 11 manufactured as described above, the insulating layer 14 is formed by screen printing in a region other than the opening forming region 22 with the photoresist layer 21 capable of forming a fine pattern formed in the opening forming region 22.
Is formed, the printing range can be regulated by the end face of the photoresist layer 21. Therefore, the insulating ink layer 23 immediately after printing is prevented from oozing out of a region other than the region where the predetermined insulating layer 15 is to be formed. Even if the printing position is slightly shifted due to the expansion and contraction of the screen mask, the viscosity of the insulating ink layer 23 is utilized so that the insulating layer 15 is formed only in the area where the predetermined insulating layer 15 is to be formed. Therefore, for example, the size of the opening 14 can be further reduced to 100 μm and the pitch thereof to about 200 μm. Therefore, the film carrier 11 having the insulating layer 15 by screen printing
In addition, the semiconductor device 1 having further miniaturized electrodes can be mounted.

【0010】なお、上記実施例では、例えば図4に示す
ように、開口部形成領域22全体にフォトレジスト層2
1を設けているが、要はフォトレジスト層の端面で印刷
範囲を規制することができればよいので、スクリーン印
刷すべき領域の少なくとも周囲にフォトレジスト層が設
けられていればよい。また、上記実施例ではネガ型のフ
ォトレジストを用いているが、上記実施例と逆パターン
のフォトマスクを使用して、ポジ型のフォトレジストを
用いてもよい。
In the embodiment described above, for example, as shown in FIG.
Although the number 1 is provided, the point is that it is only necessary that the printing range can be regulated by the end face of the photoresist layer. Therefore, the photoresist layer only needs to be provided at least around the area to be screen-printed. In the above embodiment, a negative photoresist is used. However, a positive photoresist may be used by using a photomask having a pattern opposite to that of the above embodiment.

【0011】[0011]

【発明の効果】以上説明したように、この発明によれ
ば、開口部形成領域内で少なくともその周囲に微細パタ
ーン形成可能なフォトレジスト層を形成した状態で開口
部形成領域以外の領域にスクリーン印刷により絶縁層を
形成したフィルムキャリアを用いているので、フォトレ
ジスト層の端面で印刷範囲が規制されることにより、開
口部の大きさおよびそのピッチをより一層微細化するこ
とができ、したがってスクリーン印刷による絶縁層を有
するフィルムキャリアに、より一層微細化した電極を有
する半導体装置を搭載することができる。
As described above, according to the present invention, screen printing is performed on a region other than the opening forming region in a state where a photoresist layer capable of forming a fine pattern is formed at least around the opening forming region. Since the film carrier on which the insulating layer is formed is used, the size of the opening and the pitch thereof can be further reduced by restricting the printing range at the end face of the photoresist layer, and thus screen printing. A semiconductor device having further miniaturized electrodes can be mounted on a film carrier having an insulating layer according to (1).

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の一実施例における半導体装置とフィ
ルムキャリアの接続前の状態の断面図。
FIG. 1 is a sectional view showing a state before connection between a semiconductor device and a film carrier according to an embodiment of the present invention.

【図2】半導体装置とフィルムキャリアの接続後の状態
の断面図。
FIG. 2 is a cross-sectional view showing a state after connection of a semiconductor device and a film carrier.

【図3】フィルムキャリアの製造に際し、フィルム基板
の上面に導電層をパターン形成した状態の断面図。
FIG. 3 is a cross-sectional view showing a state in which a conductive layer is pattern-formed on an upper surface of a film substrate in manufacturing a film carrier.

【図4】フィルムキャリアの製造に際し、導電層の上面
の開口部形成領域にフォトレジスト層を形成した状態の
断面図。
FIG. 4 is a cross-sectional view showing a state in which a photoresist layer is formed in an opening forming region on the upper surface of a conductive layer in manufacturing a film carrier.

【図5】フィルムキャリアの製造に際し、スクリーン印
刷により絶縁性インク層を塗布した直後の状態の断面
図。
FIG. 5 is a cross-sectional view of a state immediately after an insulating ink layer is applied by screen printing in manufacturing a film carrier.

【図6】フィルムキャリアの製造に際し、絶縁性インク
層が流動してフォトレジスト層の端面で堰き止められた
状態の断面図。
FIG. 6 is a cross-sectional view showing a state in which an insulating ink layer flows and is blocked at an end face of a photoresist layer in manufacturing a film carrier.

【図7】フィルムキャリアの製造に際し、フォトレジス
ト層を剥離して絶縁層に開口部を形成した状態の断面
図。
FIG. 7 is a cross-sectional view illustrating a state where an opening is formed in an insulating layer by removing a photoresist layer in manufacturing a film carrier.

【図8】フィルムキャリアの製造に際し、開口部の部分
における導電層上に半田層を設けた状態の断面図。
FIG. 8 is a cross-sectional view showing a state where a solder layer is provided on a conductive layer in an opening portion in manufacturing a film carrier.

【符号の説明】[Explanation of symbols]

1 半導体装置 2 電極 7 半田バンプ 11 フィルムキャリア 12 フィルム基板 13 導電層 14 開口部 15 絶縁層 16 半田層 Reference Signs List 1 semiconductor device 2 electrode 7 solder bump 11 film carrier 12 film substrate 13 conductive layer 14 opening 15 insulating layer 16 solder layer

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 21/60 311 H05K 3/28 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60 311 H05K 3/28

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 電極上に半田バンプを有する半導体装置
と、 フィルム基板の上面にパターン形成された導電層の上面
のうち絶縁層開口部を形成すべき開口部形成領域内で少
なくともその周囲にフォトレジスト層を設け、前記開口
部形成領域以外の領域にスクリーン印刷により絶縁層を
形成し、この後前記フォトレジスト層を剥離することに
より、前記絶縁層に前記開口部形成領域に対応した開口
部が形成されたフィルムキャリアとを具備し、 前記半導体装置の前記半田バンプを前記フィルムキャリ
アの前記開口部における前記導体層に接続したことを特
徴とする半導体装置の接続構造。
1. A semiconductor device having solder bumps on electrodes, and a photo-resistor at least in an opening forming region where an insulating layer opening is to be formed on an upper surface of a conductive layer patterned on an upper surface of a film substrate. A resist layer is provided, an insulating layer is formed by screen printing in a region other than the opening forming region, and then the photoresist layer is peeled off, so that the opening corresponding to the opening forming region is formed in the insulating layer. A connection structure for a semiconductor device, comprising: a formed film carrier; and wherein the solder bump of the semiconductor device is connected to the conductor layer in the opening of the film carrier.
【請求項2】 前記フィルムキャリアのフィルム基板お
よび該フィルム基板の上面に形成される導電層はキャス
ティング法により形成されていることを特徴とする請求
項1記載の半導体装置の接続構造。
2. The connection structure for a semiconductor device according to claim 1, wherein the film substrate of the film carrier and the conductive layer formed on the upper surface of the film substrate are formed by a casting method.
JP3338013A 1991-11-28 1991-11-28 Connection structure of semiconductor device Expired - Fee Related JP2869907B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3338013A JP2869907B2 (en) 1991-11-28 1991-11-28 Connection structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3338013A JP2869907B2 (en) 1991-11-28 1991-11-28 Connection structure of semiconductor device

Publications (2)

Publication Number Publication Date
JPH05152376A JPH05152376A (en) 1993-06-18
JP2869907B2 true JP2869907B2 (en) 1999-03-10

Family

ID=18314130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3338013A Expired - Fee Related JP2869907B2 (en) 1991-11-28 1991-11-28 Connection structure of semiconductor device

Country Status (1)

Country Link
JP (1) JP2869907B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102349141B (en) * 2009-03-12 2015-07-01 纳美仕股份有限公司 Underfill material and method for mounting electronic component
TWI445147B (en) 2009-10-14 2014-07-11 Advanced Semiconductor Eng Semiconductor device
TW201113962A (en) 2009-10-14 2011-04-16 Advanced Semiconductor Eng Chip having metal pillar structure
TWI478303B (en) 2010-09-27 2015-03-21 Advanced Semiconductor Eng Chip having metal pillar and package having the same
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods

Also Published As

Publication number Publication date
JPH05152376A (en) 1993-06-18

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