JP2001156203A - Printed wiring board for mounting semiconductor chip - Google Patents
Printed wiring board for mounting semiconductor chipInfo
- Publication number
- JP2001156203A JP2001156203A JP33342499A JP33342499A JP2001156203A JP 2001156203 A JP2001156203 A JP 2001156203A JP 33342499 A JP33342499 A JP 33342499A JP 33342499 A JP33342499 A JP 33342499A JP 2001156203 A JP2001156203 A JP 2001156203A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- opening
- mounting
- wiring board
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
- H01L2924/384—Bump effects
- H01L2924/3841—Solder bridging
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップをフ
リップチップ方式で実装する半導体チップ実装用プリン
ト配線板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board for mounting a semiconductor chip on which a semiconductor chip is mounted by a flip chip method.
【０００２】[0002]
【従来の技術】近年、半導体装置の小型化、高性能化を
指向して、半導体チップをプリント配線板にフリップチ
ップ方式で実装する実装技術が実用化されてきている。
このような実装方式は、図４に示すように、あらかじめ
半導体チップ１の電極部２にはんだバンプ３を形成して
おき、プリント配線板７の絶縁基板４上に形成した導体
回路５よりなるフリップチップパッド部６に、フェイス
ダウン方式により接続する方式である。この方式の場
合、はんだリフロー法等によってはんだバンプ３とフリ
ップチップパッド部６を接合する。そして、半導体チッ
プ１を実装したプリント配線板７は、さらにマザーボー
ドに実装されて電子機器に組込まれる。2. Description of the Related Art In recent years, mounting techniques for mounting a semiconductor chip on a printed wiring board by a flip-chip method have been put to practical use in order to downsize and improve the performance of a semiconductor device.
As shown in FIG. 4, a solder bump 3 is formed on an electrode portion 2 of a semiconductor chip 1 in advance, and a flip circuit including a conductor circuit 5 formed on an insulating substrate 4 of a printed wiring board 7 is used. This is a method of connecting to the chip pad section 6 by a face-down method. In the case of this method, the solder bumps 3 and the flip chip pad portions 6 are joined by a solder reflow method or the like. Then, the printed wiring board 7 on which the semiconductor chip 1 is mounted is further mounted on a motherboard and incorporated into an electronic device.
【０００３】そして、この半導体チップの実装方式の場
合には、フリップチップパッド部６となる導体回路５、
５間の間隔（図５に示すｔ）が狭いために、導体回路５
を露出させた状態にして、導体回路５、５間にソルダー
レジストを塗布することは困難であり、図５に示すよう
にフリップチップパッド部６となる位置の導体回路５、
５間にはソルダーレジスト８を塗布していないのが一般
的である。すなわち、図５に示すようにソルダーレジス
ト８はフリップチップパッド部６となる位置を除いた導
体回路５上を覆って、絶縁基板４上に塗布されるのが一
般的である。[0003] In the case of this semiconductor chip mounting method, the conductor circuit 5 serving as the flip chip pad portion 6,
5 (t shown in FIG. 5), the conductor circuit 5
It is difficult to apply a solder resist between the conductor circuits 5 and 5 in a state where the conductor circuits 5 and 5 are exposed. As shown in FIG.
It is general that no solder resist 8 is applied between the spaces 5. That is, as shown in FIG. 5, the solder resist 8 is generally applied on the insulating substrate 4 so as to cover the conductor circuit 5 except for the position where the flip chip pad 6 is formed.
【０００４】[0004]
【発明が解決しようとする課題】上記のように半導体チ
ップ実装用プリント配線板に半導体チップをフリップチ
ップ方式で実装する場合、フリップチップパッド部とな
る導体回路間の間隔が極めて狭いために、導体回路の形
成精度や、半導体チップの位置合わせ精度が不十分な場
合には、はんだリフロー法等によってはんだバンプとフ
リップチップパッド部を接合して実装品を製造した際
に、実装品にブリッジが発生して、実装歩留まりが悪い
という問題があった。When a semiconductor chip is mounted on a printed wiring board for mounting a semiconductor chip by a flip-chip method as described above, the interval between conductor circuits serving as flip-chip pads is extremely small. If the accuracy of circuit formation or the alignment accuracy of the semiconductor chip is insufficient, bridges will occur in the mounted product when the solder bump and flip chip pad are joined by solder reflow method etc. to manufacture the mounted product As a result, there is a problem that the mounting yield is poor.
【０００５】本発明は上記の点に鑑みてなされたもので
あり、半導体チップをフリップチップ方式でプリント配
線板に直接実装する場合に、ブリッジの発生が低減し、
実装歩留まりを向上することができる半導体チップ実装
用プリント配線板を提供することを目的とするものであ
る。The present invention has been made in view of the above points, and when a semiconductor chip is directly mounted on a printed wiring board by a flip chip method, the occurrence of bridges is reduced,
An object of the present invention is to provide a printed wiring board for mounting a semiconductor chip, which can improve a mounting yield.
【０００６】[0006]
【課題を解決するための手段】請求項１に係る発明の半
導体チップ実装用プリント配線板は、半導体チップの電
極部に形成したはんだバンプと接合する、導体回路より
なる複数のフリップチップパッド部を絶縁基板上に備え
ている半導体実装用プリント配線板において、前記フリ
ップチップパッド部が、前記導体回路の表面を被覆して
いる絶縁樹脂に開口部を設けて形成される、前記絶縁樹
脂で包囲された導体回路の露出面よりなることを特徴と
する半導体チップ実装用プリント配線板である。According to a first aspect of the present invention, there is provided a printed wiring board for mounting a semiconductor chip, comprising a plurality of flip chip pad portions formed of a conductor circuit and joined to solder bumps formed on electrode portions of the semiconductor chip. In a printed wiring board for semiconductor mounting provided on an insulating substrate, the flip-chip pad portion is formed by providing an opening in an insulating resin covering the surface of the conductive circuit, and is surrounded by the insulating resin. And a printed wiring board for mounting a semiconductor chip, comprising an exposed surface of a conductive circuit.
【０００７】請求項１に係る発明の半導体チップ実装用
プリント配線板では、フリップチップパッド部が、導体
回路の表面を被覆している絶縁樹脂に開口部を設けて形
成される、絶縁樹脂で包囲された導体回路の露出面より
なるので、フリップチップパッド部となる部分の面積が
小さくなり、その結果フリップチップパッド部間の間隔
が広がり、また、前記開口部が半導体チップのはんだバ
ンプを保持する働きをするので、ブリッジの発生が低減
する。In the printed wiring board for mounting a semiconductor chip according to the first aspect of the present invention, the flip chip pad portion is formed by providing an opening in the insulating resin covering the surface of the conductive circuit, and is surrounded by the insulating resin. The exposed surface of the conductive circuit thus formed, the area of the portion to be the flip chip pad portion is reduced, as a result, the interval between the flip chip pad portions is widened, and the opening holds the solder bump of the semiconductor chip. As it works, the occurrence of bridges is reduced.
【０００８】請求項２に係る発明の半導体チップ実装用
プリント配線板は、前記開口部における開口面の大きさ
の方が、前記開口部の底面にある導体回路の露出面の大
きさより大きくなるように、前記開口部の側面を傾斜面
として形成している請求項１記載の半導体チップ実装用
プリント配線板である。According to a second aspect of the present invention, in the printed wiring board for mounting a semiconductor chip, the size of the opening surface in the opening is larger than the size of the exposed surface of the conductor circuit on the bottom surface of the opening. 2. The printed wiring board for mounting a semiconductor chip according to claim 1, wherein a side surface of said opening is formed as an inclined surface.
【０００９】請求項２に係る発明の半導体チップ実装用
プリント配線板では、開口部における開口面の大きさの
方が、開口部の底面にある導体回路の露出面の大きさよ
り大きくなるように、開口部の側面を傾斜面として形成
しているので、開口部が半導体チップのはんだバンプを
保持する働きがより強まるので、ブリッジの発生がより
低減する。In the printed wiring board for mounting a semiconductor chip according to the present invention, the size of the opening surface in the opening is larger than the size of the exposed surface of the conductor circuit on the bottom surface of the opening. Since the side surface of the opening is formed as an inclined surface, the opening has a stronger function of holding the solder bumps of the semiconductor chip, and thus the occurrence of bridges is further reduced.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態を説明
する。Embodiments of the present invention will be described below.
【００１１】銅張積層板等を加工して、図１に示すよう
に、絶縁基板４上に、導体回路５を形成する。そして、
塗布等の方法で導体回路５及び導体回路間を絶縁樹脂１
０で被覆する。次いで、図２に示すように、導体回路５
の表面を被覆している絶縁樹脂１０に開口部１１を設け
て、この開口部１１の底面に導体回路５の表面を露出さ
せてフリップチップパッド部６を形成する。この実施形
態では、図１の開口部１１の形状を円形状とすることに
より、図２に示すようにフリップチップパッド部６を円
形状に形成している。このようにして、図１に示す本発
明の実施形態である半導体チップ実装用のプリント配線
板７を製造することができる。By processing a copper-clad laminate or the like, a conductor circuit 5 is formed on an insulating substrate 4 as shown in FIG. And
Insulating resin 1 between the conductor circuits 5 and the conductor circuits by a method such as coating.
Cover with 0. Next, as shown in FIG.
An opening 11 is provided in the insulating resin 10 covering the surface of the conductive circuit 5, and the surface of the conductive circuit 5 is exposed at the bottom of the opening 11 to form the flip chip pad 6. In this embodiment, the flip chip pad 6 is formed in a circular shape as shown in FIG. 2 by making the shape of the opening 11 in FIG. 1 circular. Thus, the printed wiring board 7 for mounting a semiconductor chip according to the embodiment of the present invention shown in FIG. 1 can be manufactured.
【００１２】絶縁基板４の材質としては、絶縁体であれ
ばよいが、ガラス布基材であってエポキ樹脂やポリイミ
ド樹脂等をマトリックス樹脂とした基板を用いることが
できる。導体回路５は銅箔をエッチング加工した銅回路
を用いることができるが、銅以外の金属であってもよ
く、スパッタリング、メッキ等によって形成してもよ
い。また、銅回路の上に、更に他の金属層を形成した構
成であってもよい。そして、絶縁樹脂１０については、
後の半導体チップの実装工程に耐える樹脂であればよ
く、一般にソルダーレジストとして使用されているもの
を使用できる。絶縁樹脂１０に開口部１１を設ける方法
としては、レーザー加工法や絶縁樹脂１０として感光性
樹脂を用いて露光、現像処理を行うフォトビア形成法で
行うことができる。開口部１１の形状については、円形
状、四角形状等に形成することができるが、大きさとし
ては直径が５０〜１００μｍの円形又は辺の長さが５０
〜１００μｍの四角形程度の大きさが好ましい。図２に
示す実施形態では図１の開口部１１の形状を円形状とす
ることにより、フリップチップパッド部６を円形状に形
成している。The insulating substrate 4 may be made of any material as long as it is an insulator. However, a substrate made of a glass cloth and using an epoxy resin, a polyimide resin, or the like as a matrix resin can be used. The conductor circuit 5 may be a copper circuit obtained by etching a copper foil, but may be a metal other than copper, or may be formed by sputtering, plating, or the like. Further, a configuration in which another metal layer is further formed on the copper circuit may be employed. And about the insulating resin 10,
Any resin that can withstand the subsequent semiconductor chip mounting process may be used, and a resin generally used as a solder resist can be used. The method for providing the opening 11 in the insulating resin 10 can be performed by a laser processing method or a photo-via forming method of performing exposure and development processing using a photosensitive resin as the insulating resin 10. The shape of the opening 11 can be formed in a circular shape, a square shape, or the like. The size of the opening 11 is a circle having a diameter of 50 to 100 μm or a side having a length of 50 μm.
A size of about 100 μm square is preferred. In the embodiment shown in FIG. 2, the flip chip pad 6 is formed in a circular shape by making the shape of the opening 11 in FIG. 1 circular.
【００１３】この図1、図２に示す半導体チップ実装用
のプリント配線板７では、図４、図５に示す導体回路５
がそのままフリップチップパッド部６となっている従来
の場合に比べ、フリップチップパッド部６を形成してい
る面積が小さくなり、フリップチップパッド部６、６間
の間隔が実質的に広がり、また、絶縁樹脂１０に形成し
ている開口部１１が半導体チップ１の電極部２に形成し
たはんだバンプ３を保持する働きをするので、ブリッジ
の発生が低減し、従って実装歩留まりが向上する。In the printed wiring board 7 for mounting a semiconductor chip shown in FIGS. 1 and 2, the conductor circuit 5 shown in FIGS.
Is smaller than the conventional case where the flip chip pad portion 6 is formed as it is, the area where the flip chip pad portion 6 is formed is reduced, the interval between the flip chip pad portions 6 and 6 is substantially widened, and Since the opening 11 formed in the insulating resin 10 functions to hold the solder bump 3 formed on the electrode 2 of the semiconductor chip 1, the occurrence of bridges is reduced, and the mounting yield is improved.
【００１４】また、図３に示すように絶縁樹脂１０に形
成する開口部１１の形状を、開口面１２の大きさの方
が、開口部１１の底面１３にある導体回路５の露出面の
大きさより大きくなるように、開口部１１の側面１４を
傾斜面として形成すると、図１に示す半導体チップ１の
電極部２に形成したはんだバンプ３をこの開口部１１に
誘導しやすくなり、且つ開口部１１に収納したはんだバ
ンプ３を保持する働きがより強まるので、半導体チップ
実装工程でのブリッジの発生がより低減する。なお、傾
斜面に形成する方法については、レーザー加工の場合は
加工条件の選択で行うことができ、フォトビア形成法の
場合は２段階でビア形成する方法で行うことができる。As shown in FIG. 3, the shape of the opening 11 formed in the insulating resin 10 is such that the size of the opening surface 12 is larger than the size of the exposed surface of the conductor circuit 5 on the bottom surface 13 of the opening 11. If the side surface 14 of the opening 11 is formed as an inclined surface so as to be larger than that, the solder bump 3 formed on the electrode portion 2 of the semiconductor chip 1 shown in FIG. Since the function of holding the solder bumps 3 housed in the semiconductor device 11 becomes stronger, the occurrence of bridges in the semiconductor chip mounting process is further reduced. Note that the method of forming on the inclined surface can be performed by selecting processing conditions in the case of laser processing, and can be performed by a method of forming a via in two steps in the case of the photo via forming method.
【００１５】さらに、本発明の絶縁樹脂１０に開口部１
１を設けた後で、形成されたフリップチップパッド部６
の表面に、更に金属層や表面処理層等を設けて、はんだ
濡れ性やはんだバンプとの接合強度の向上を図るように
してもよい。Furthermore, the opening 1 is formed in the insulating resin 10 of the present invention.
1 is provided, and the formed flip chip pad portion 6 is formed.
A metal layer, a surface treatment layer, or the like may be further provided on the surface of the substrate to improve the solder wettability and the bonding strength with the solder bump.
【００１６】[0016]
【発明の効果】請求項１に係る発明の半導体チップ実装
用プリント配線板では、フリップチップパッド部となる
部分の面積が小さくなり、その結果フリップチップパッ
ド部間の間隔が広がり、また、前記開口部が半導体チッ
プのはんだバンプを保持する働きをするので、ブリッジ
の発生が低減する。従って請求項１に係る発明の半導体
チップ実装用プリント配線板によれば、フリップチップ
方式で半導体チップをプリント配線板に直接実装する場
合に、ブリッジの発生が低減し、実装歩留まりを向上す
ることができる。In the printed wiring board for mounting a semiconductor chip according to the first aspect of the present invention, the area of a portion to be a flip chip pad portion is reduced, and as a result, the interval between the flip chip pad portions is widened and the opening is formed. Since the portion functions to hold the solder bumps of the semiconductor chip, the occurrence of bridges is reduced. Therefore, according to the printed wiring board for mounting a semiconductor chip of the first aspect of the present invention, when the semiconductor chip is directly mounted on the printed wiring board by the flip-chip method, the occurrence of bridges is reduced and the mounting yield is improved. it can.
【００１７】請求項２に係る発明の半導体チップ実装用
プリント配線板では、開口部における開口面の大きさの
方が、開口部の底面にある導体回路の露出面の大きさよ
り大きくなるように、開口部の側面を傾斜面として形成
しているので、開口部が半導体チップのはんだバンプを
保持する働きがより強まるので、ブリッジの発生がより
低減すし、実装歩留まりをより向上することができると
いう効果を奏する。In the printed wiring board for mounting a semiconductor chip according to the second aspect of the present invention, the size of the opening surface in the opening is larger than the size of the exposed surface of the conductor circuit on the bottom surface of the opening. Since the side surface of the opening is formed as an inclined surface, the opening further strengthens the function of holding the solder bumps of the semiconductor chip, so that the occurrence of bridges can be further reduced and the mounting yield can be further improved. To play.
【図１】実施形態の構成を説明するための断面図であ
る。FIG. 1 is a cross-sectional view illustrating a configuration of an embodiment.
【図２】同上の部分平面図である。FIG. 2 is a partial plan view of the same.
【図３】他の実施形態の構成を説明するための部分断面
図である。FIG. 3 is a partial cross-sectional view illustrating a configuration of another embodiment.
【図４】従来例の構成を説明するための断面図である。FIG. 4 is a cross-sectional view illustrating a configuration of a conventional example.
【図５】従来例の構成を説明するための部分平面図であ
る。FIG. 5 is a partial plan view for explaining a configuration of a conventional example.
１ 半導体チップ ２ 電極部 ３ はんだバンプ ４ 絶縁基板 ５ 導体回路 ６ フリップチップパッド部 ７ プリント配線板 ８ ソルダーレジスト １０ 絶縁樹脂 １１ 開口部 １２ 開口面 １３ 底面 １４ 側面 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Electrode part 3 Solder bump 4 Insulating substrate 5 Conductor circuit 6 Flip chip pad part 7 Printed wiring board 8 Solder resist 10 Insulating resin 11 Opening 12 Opening surface 13 Bottom surface 14 Side surface
Claims (2)
バンプと接合する、導体回路よりなる複数のフリップチ
ップパッド部を絶縁基板上に備えている半導体実装用プ
リント配線板において、前記フリップチップパッド部
が、前記導体回路の表面を被覆している絶縁樹脂に開口
部を設けて形成される、前記絶縁樹脂で包囲された導体
回路の露出面よりなることを特徴とする半導体チップ実
装用プリント配線板。1. A printed circuit board for mounting a semiconductor, comprising: a plurality of flip-chip pads made of a conductive circuit on an insulating substrate, the flip-chip pads being joined to solder bumps formed on electrode portions of a semiconductor chip. A printed circuit board for mounting a semiconductor chip, wherein the printed circuit board comprises an exposed surface of a conductor circuit surrounded by the insulation resin, which is formed by providing an opening in the insulation resin covering the surface of the conductor circuit. .
が、前記開口部の底面にある導体回路の露出面の大きさ
より大きくなるように、前記開口部の側面を傾斜面とし
て形成している請求項１記載の半導体チップ実装用プリ
ント配線板。2. The side surface of the opening is formed as an inclined surface such that the size of the opening in the opening is larger than the size of the exposed surface of the conductor circuit on the bottom of the opening. The printed wiring board for mounting a semiconductor chip according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33342499A JP2001156203A (en) | 1999-11-24 | 1999-11-24 | Printed wiring board for mounting semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33342499A JP2001156203A (en) | 1999-11-24 | 1999-11-24 | Printed wiring board for mounting semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001156203A true JP2001156203A (en) | 2001-06-08 |
Family
ID=18265966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33342499A Pending JP2001156203A (en) | 1999-11-24 | 1999-11-24 | Printed wiring board for mounting semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001156203A (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007511103A (en) * | 2003-11-10 | 2007-04-26 | チップパック，インク． | Bump-on-lead flip chip interconnect |
| JP2007281269A (en) * | 2006-04-10 | 2007-10-25 | Nec Corp | Mounting structure of electronic part, and its manufacturing method |
| JP2008085308A (en) * | 2006-08-30 | 2008-04-10 | Sanyo Electric Co Ltd | Substrate for mounting element, semiconductor module, and portable apparatus |
| US7901983B2 (en) | 2004-11-10 | 2011-03-08 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| US8076232B2 (en) | 2008-04-03 | 2011-12-13 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
| USRE44500E1 (en) | 2003-11-10 | 2013-09-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
| USRE44562E1 (en) | 2003-11-10 | 2013-10-29 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
| US8574959B2 (en) | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
| USRE44579E1 (en) | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| USRE44608E1 (en) | 2003-11-10 | 2013-11-26 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
| WO2014045491A1 (en) * | 2012-09-21 | 2014-03-27 | 日本特殊陶業株式会社 | Wiring board and method for manufacturing same |
| US8810029B2 (en) | 2003-11-10 | 2014-08-19 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
| US8841779B2 (en) | 2005-03-25 | 2014-09-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate |
| US9029196B2 (en) | 2003-11-10 | 2015-05-12 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| US9159665B2 (en) | 2005-03-25 | 2015-10-13 | Stats Chippac, Ltd. | Flip chip interconnection having narrow interconnection sites on the substrate |
| US9773685B2 (en) | 2003-11-10 | 2017-09-26 | STATS ChipPAC Pte. Ltd. | Solder joint flip chip interconnection having relief structure |
| US9930790B2 (en) | 2013-01-30 | 2018-03-27 | Denso Corporation | Method for manufacturing multilayer substrate for having BGA-type component thereon |
| USRE47600E1 (en) | 2003-11-10 | 2019-09-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
| WO2021071060A1 (en) * | 2019-10-11 | 2021-04-15 | 삼성디스플레이 주식회사 | Adhesive member, display device comprising same, and method for manufacturing display device |
-
1999
- 1999-11-24 JP JP33342499A patent/JP2001156203A/en active Pending
Cited By (47)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE44579E1 (en) | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| US9899286B2 (en) | 2003-11-10 | 2018-02-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| US9865556B2 (en) | 2003-11-10 | 2018-01-09 | STATS ChipPAC Pte Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| USRE44608E1 (en) | 2003-11-10 | 2013-11-26 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
| US7973406B2 (en) | 2003-11-10 | 2011-07-05 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| US9385101B2 (en) | 2003-11-10 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
| US8188598B2 (en) | 2003-11-10 | 2012-05-29 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| KR101237172B1 (en) * | 2003-11-10 | 2013-02-25 | 스태츠 칩팩, 엘티디. | Bump-on-lead flip chip interconnection |
| US9773685B2 (en) | 2003-11-10 | 2017-09-26 | STATS ChipPAC Pte. Ltd. | Solder joint flip chip interconnection having relief structure |
| USRE44355E1 (en) | 2003-11-10 | 2013-07-09 | Stats Chippac, Ltd. | Method of forming a bump-on-lead flip chip interconnection having higher escape routing density |
| KR101286379B1 (en) | 2003-11-10 | 2013-07-15 | 스태츠 칩팩, 엘티디. | Bump-on-lead flip chip interconnection |
| USRE44377E1 (en) | 2003-11-10 | 2013-07-16 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| USRE44431E1 (en) | 2003-11-10 | 2013-08-13 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| USRE44500E1 (en) | 2003-11-10 | 2013-09-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
| USRE44524E1 (en) | 2003-11-10 | 2013-10-08 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| US8558378B2 (en) | 2003-11-10 | 2013-10-15 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| USRE44562E1 (en) | 2003-11-10 | 2013-10-29 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
| US8574959B2 (en) | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
| KR101249555B1 (en) * | 2003-11-10 | 2013-04-01 | 스태츠 칩팩, 엘티디. | Bump-on-lead flip chip interconnection |
| US9379084B2 (en) | 2003-11-10 | 2016-06-28 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| US9922915B2 (en) | 2003-11-10 | 2018-03-20 | STATS ChipPAC Pte. Ltd. | Bump-on-lead flip chip interconnection |
| US9373573B2 (en) | 2003-11-10 | 2016-06-21 | STATS ChipPAC Pte. Ltd. | Solder joint flip chip interconnection |
| JP2007511103A (en) * | 2003-11-10 | 2007-04-26 | チップパック，インク． | Bump-on-lead flip chip interconnect |
| US8759972B2 (en) | 2003-11-10 | 2014-06-24 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
| US8810029B2 (en) | 2003-11-10 | 2014-08-19 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
| USRE44761E1 (en) | 2003-11-10 | 2014-02-11 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
| TWI478254B (en) * | 2003-11-10 | 2015-03-21 | Chippac Inc | Bump-on-lead flip chip interconnection |
| US9029196B2 (en) | 2003-11-10 | 2015-05-12 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| USRE47600E1 (en) | 2003-11-10 | 2019-09-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
| US9064858B2 (en) | 2003-11-10 | 2015-06-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
| US9219045B2 (en) | 2003-11-10 | 2015-12-22 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| US7901983B2 (en) | 2004-11-10 | 2011-03-08 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| US9159665B2 (en) | 2005-03-25 | 2015-10-13 | Stats Chippac, Ltd. | Flip chip interconnection having narrow interconnection sites on the substrate |
| US10580749B2 (en) | 2005-03-25 | 2020-03-03 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming high routing density interconnect sites on substrate |
| US8841779B2 (en) | 2005-03-25 | 2014-09-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate |
| JP2007281269A (en) * | 2006-04-10 | 2007-10-25 | Nec Corp | Mounting structure of electronic part, and its manufacturing method |
| JP2008085308A (en) * | 2006-08-30 | 2008-04-10 | Sanyo Electric Co Ltd | Substrate for mounting element, semiconductor module, and portable apparatus |
| US8076232B2 (en) | 2008-04-03 | 2011-12-13 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
| JP2014063932A (en) * | 2012-09-21 | 2014-04-10 | Ngk Spark Plug Co Ltd | Wiring board and manufacturing method of the same |
| CN104662655B (en) * | 2012-09-21 | 2017-07-11 | 日本特殊陶业株式会社 | Circuit board and its manufacture method |
| US9516751B2 (en) | 2012-09-21 | 2016-12-06 | Ngk Spark Plug Co., Ltd. | Wiring board and method for manufacturing same |
| EP2899751A4 (en) * | 2012-09-21 | 2016-06-22 | Ngk Spark Plug Co | Wiring board and method for manufacturing same |
| CN104662655A (en) * | 2012-09-21 | 2015-05-27 | 日本特殊陶业株式会社 | Wiring board and method for manufacturing same |
| WO2014045491A1 (en) * | 2012-09-21 | 2014-03-27 | 日本特殊陶業株式会社 | Wiring board and method for manufacturing same |
| US9930790B2 (en) | 2013-01-30 | 2018-03-27 | Denso Corporation | Method for manufacturing multilayer substrate for having BGA-type component thereon |
| DE112014000614B4 (en) | 2013-01-30 | 2019-07-04 | Denso Corporation | A method of producing a multi-layer substrate to place a BGA-type component thereon |
| WO2021071060A1 (en) * | 2019-10-11 | 2021-04-15 | 삼성디스플레이 주식회사 | Adhesive member, display device comprising same, and method for manufacturing display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2592038B2 (en) | Semiconductor chip mounting method and substrate structure | |
| JP2001156203A (en) | Printed wiring board for mounting semiconductor chip | |
| JP2004343030A (en) | Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board | |
| JP2000138313A (en) | Semiconductor device and its manufacture | |
| JP2005109496A (en) | Semiconductor package substrate for forming pre-solder structure, the semiconductor package substrate in which pre-solder structure is formed, and the manufacturing methods | |
| JP2002246535A (en) | Semiconductor integrated circuit | |
| USRE49286E1 (en) | Method of making flip chip | |
| KR100206866B1 (en) | Semiconductor apparatus | |
| US5109601A (en) | Method of marking a thin film package | |
| US6278185B1 (en) | Semi-additive process (SAP) architecture for organic leadless grid array packages | |
| JP3554650B2 (en) | Circuit board | |
| US4965700A (en) | Thin film package for mixed bonding of chips | |
| JP2004235420A (en) | Electronic device, manufacturing method thereof, circuit board, manufacturing method thereof, electronic device, and manufacturing method thereof | |
| JPH0425038A (en) | Semiconductor device and manufacture of the same and electronic circuit utilizing the semiconductor device | |
| USRE48422E1 (en) | Method of making flip chip | |
| JP3800298B2 (en) | Bump forming method and semiconductor device manufacturing method | |
| JP2005183868A (en) | Semiconductor device and its packaging structure | |
| JP2002231765A (en) | Semiconductor device | |
| JP2004072043A (en) | Semiconductor wafer, semiconductor chip, and semiconductor device and its manufacturing method | |
| KR100343454B1 (en) | Wafer level package | |
| JP2000195890A (en) | Manufacture of semiconductor device | |
| JP2652222B2 (en) | Substrate for mounting electronic components | |
| JPH11204677A (en) | Semiconductor device and manufacture thereof | |
| JP2004319792A (en) | Semiconductor device and its manufacturing method | |
| JPH09130000A (en) | Double sided wiring board and semiconductor device using it |