JP2848987B2 - Waveform equalization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform equalizing circuit for automatically correcting a waveform distortion in an input video signal when the input video signal includes the waveform distortion. The present invention relates to a waveform equalization circuit that can perform waveform equalization using an arbitrary video waveform instead of the reference signal even when a ghost removal reference signal used for waveform equalization is not included.

[0002]

2. Description of the Related Art With the start of the clear vision broadcasting in 1989, a reference signal (GCR signal) for ghost removal is inserted during a vertical retrace period of video signals of all broadcast waves. Using this signal, ghost removal with high accuracy and equalization of waveform distortion in a transmission path can be performed.

A ghost removal reference signal (GCR)
FIG. 2 shows an example of a waveform equalizing circuit using the signal (e.g., signal).
In the figure, 201 is a video signal input terminal, 202 is A
D converter 203, transversal filter 203
Is a DA converter, 205 is a video signal output terminal, 206 is a noise removal circuit, 207 is a waveform memory, 208 is a difference circuit, 209 is a subtractor, 210 is a reference waveform generation circuit, 21
1 is a tap coefficient control circuit, and 212 is a tap coefficient memory.

Next, the circuit operation will be described. AD converter 20
The video signal converted into a digital signal by 2 is input to the noise removal circuit 206 via the transversal filter 203. Normally, the tap coefficients of the transversal filter at the start of the waveform equalization operation are all 0, and the input video signal is output as it is to the subsequent stage.

[0005] The noise removing circuit 206 extracts a portion including the GCR signal in the video signal, averages it for several fields, removes a random noise component, and removes the noise component.
To memorize. The GCR signal read from the waveform memory 207 is differentiated by the difference circuit 208 to form an impulse waveform.

From the reference waveform generation circuit 210, an ideal G
The impulse waveform of the CR signal is output, and the subtractor 209 subtracts the impulse waveform from the GCR signal (output of the difference circuit 208) extracted from the input video signal. As a result, an error signal due to distortion is output.

The tap coefficient to be given to the transversal filter 203 is calculated in the tap coefficient control circuit 211 based on the error caused by the distortion thus obtained, and stored in the tap coefficient memory 212. Tap coefficient memory 2
By providing the tap coefficients read from the filter 12 to the transversal filter 203, the distortion of the input video signal is reduced and output from the filter 203.

By repeating the above operation, the distortion is gradually reduced, and the finally equalized video signal is output via the DA converter 204. An example of a document describing such a waveform equalizing circuit is disclosed in JP-A-1-228.
No. 4179, and the like.

[0009]

In the above-described waveform equalizing circuit according to the prior art, for some reason, the input video signal is subjected to GC.
If the R signal is not inserted, no consideration is given to it, and there is a possibility of causing a system malfunction or deteriorating image quality. As described above, a GCR signal is inserted in a broadcast wave, but a GCR signal is not inserted in a video signal from a video disc, VTR, CATV, or the like, and a video signal without a GCR signal is inserted. Is often input.

An object of the present invention is to solve the above-mentioned problems and to provide a waveform equalizing circuit which operates correctly even when a GCR signal is inserted into an input video signal as well as when it is not inserted. Is to do.

[0011]

The object of the present invention is to provide a waveform equalizing circuit for detecting whether or not a GCR signal is inserted into an input video signal, and using the GCR signal when the signal is inserted. In the case where it is not inserted, the delay is achieved by providing a delay detecting means for detecting a delay time as waveform distortion using an arbitrary video waveform.

[0012]

The means for detecting the presence or absence of GCR signal insertion detects whether or not a GCR signal has been inserted into the video signal,
Output. By this output, the signal used for waveform equalization is G
It is determined whether to use a CR signal or a video waveform. The delay detecting means detects a delay time as waveform distortion from the GCR signal or the video waveform. By setting the tap in the transversal filter corresponding to the detected delay time to a required value, ghost and waveform distortion included in the input video signal can be removed.

[0013]

Embodiments of the present invention will be described below. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 101 is a video signal input terminal, 102 is an AD converter, 103 is a transversal filter, and 104 is a D
A converter, 105 is a video signal output terminal, 106 is a noise removal circuit, 107 is a waveform memory, 108 is a delay detection circuit, 109 is a subtractor, 110 is a reference waveform generation circuit, 11
1 is a tap coefficient control circuit, 112 is a tap coefficient memory,
113 is a GCR detection circuit, and 114 is an integration circuit.

The operation will be described below. First, an outline of the waveform equalizing operation will be described. At the start of operation, all tap coefficients in the transversal filter 103 are set to 0.
, And the input video signal is passed through as it is and supplied to the noise removal circuit 106. The noise removing circuit 106 extracts a GCR signal portion in the video signal, and uses the waveform memory 107 to average the video signal for several fields to remove a noise component.

The G from which the noise component has been removed in this way
The CR signal is input to the delay detection circuit 108, and the delay time from the main signal of the unnecessary wave (ghost) is detected as distortion information. The distortion information output from the delay detection circuit 108 is input to the integration circuit 114. This integration circuit 11
4 normally outputs a signal without any processing. The distortion information output from the integration circuit 114 is input to the subtractor 109.

In the subtractor 109, the distortion information obtained by performing the subtraction between the signal from the reference waveform generation circuit 110 and the distortion information from the integration circuit 114 is input to a tap coefficient control circuit 111. Based on this distortion information,
The required tap coefficient is calculated and stored in the tap coefficient memory 112. At the same time, the calculated tap coefficients are given to the transversal filter 103, and the filter 10
Then, the tap coefficients in 3 are controlled, and the first waveform equalization operation ends.

FIG. 3 is a block diagram showing a circuit configuration of the transversal filter 103 in FIG. In the figure, reference numeral 301 denotes a video signal input terminal;
3, 304, 305 are delay circuits, 306, 307, 30
8, 309 are multipliers, 310, 311, 312, 313
Is a tap coefficient input terminal, 314 and 315 are adders, 31
Reference numeral 6 denotes a video signal output terminal.

A tap coefficient (a tap coefficient corresponding to each delay time) calculated based on the distortion information is input to a tap coefficient input terminal 3.
The correction signal is obtained from the output of the adder 314 by giving the signals from 10, 311, 312, and 313. Waveform equalization is performed by adding this signal to the input signal. Since the correction signal is 0 at the start of the operation, the input signal is output as it is through the delay circuit 302 and the adder 315.

FIG. 4 is a block diagram showing a circuit configuration of the noise removing circuit 106 in FIG. In the figure, 401 is a video signal input terminal, 402 is a switching signal generation circuit, 403 is a buffer memory, 404 is a multiplier,
405 and 408 are selection circuits, 406 is an adder, 407 is a divider, 409 is an initialization signal input terminal, and 410 is a GCR
Signal input terminals 411 and 412 are GCR signal output terminals.

FIG. 8 is a waveform chart for explaining the operation of the noise elimination circuit shown in FIG. In FIG. 4, a GCR waveform (a portion including the GCR signal extracted from the input video signal) as shown in FIG. 8A is extracted and temporarily stored in the buffer memory 403. It should be noted that the GCR signal is set at 8H and 281H in the vertical retrace interval of the video signal,
It is well known that the bar signal is transmitted in a field sequence.

At this time, the switching signal generation circuit 402 determines whether the input GCR signal is a sinX / X bar signal or a pedestal level signal, and outputs a switching signal. In the selection circuit 405, the GC
When the R signal is a sinX / X bar signal shown in FIG. 8A, the output of the buffer memory 403 is selected, and FIG.
In the case of the pedestal level signal shown in FIG. Then, the adder 40
At 6, the output from the selection circuit 408 is added and stored in the waveform memory 107.

In the initial state, the selection circuit 408 is connected to GND
By selecting 0, ie, 0, the input GCR signal is stored in the waveform memory 107 as it is,
From the field, the output of the waveform memory 107 is selected, added to the input GCR signal, and stored in the waveform memory 107.

The GCR signal obtained by repeating this operation for each field and adding for several fields becomes a GCR waveform from which noise is removed as shown in FIG. , Output terminal 412. The number of fields to be added is preferably an integer multiple of 8, since the GCR signal is inserted as an 8-field sequence. For example, 1
Assuming that 28 fields have been added, the divider 4
At 07, it is multiplied by (1/64).

FIG. 6 shows the delay detection circuit 1 in FIG.
It is a block diagram which shows the circuit structure of 08. In the figure, 601 is a video signal input terminal, 602 and 604 are Fourier transform circuits, 603 is a logarithmic transform circuit, and 605 is a video signal output terminal.

A video signal input from a video signal input terminal 601 is input to a Fourier transform circuit 602, and a signal on a time axis is converted into a signal on a frequency axis. The signal converted to the signal on the frequency axis is then converted to a logarithmic conversion circuit 603.
And is logarithmically converted. Further, the logarithmically converted video signal is Fourier-transformed by the Fourier transform circuit 604, and is again converted into a time-dimensional signal.

The Fourier transform / logarithmic transform / Fourier transform is a conventionally known conversion method called cepstrum.
When a reflected wave (corresponding to a ghost) or the like is included in a signal, the signal is used to determine a delay time of the reflected wave. If this conversion is performed separately for the amplitude and the phase, both the delay time and the phase can be obtained.

At this time, the signal obtained at the output terminal 605 is distortion information indicating that the phase is shifted from the basic video signal, so that the result is an interference wave causing ghost and waveform distortion. The Fourier transform circuits 602 and 604 and the logarithmic transform circuit 603 used here may be either hardware circuits or software calculation circuits.

Next, FIG. 9 shows the subtractor 109 in FIG.
FIG. 6 is a waveform diagram showing a state of subtraction performed in the step (a). In the subtracter 109, a signal of a reference waveform calculated in advance as shown in FIG. 9A output from the reference waveform generation circuit 110 and a signal of the reference waveform output from the integration circuit 114 in FIG. Is subtracted from the distortion information (a waveform given from the delay detection circuit 108 via the integration circuit 114) as shown in FIG. As a result, distortion information due to distortion and ghost as shown in FIG. 9C is obtained and output to the tap coefficient control circuit 111.

FIG. 5 is a block diagram showing a configuration example of the tap coefficient control circuit 111 in FIG. In the figure, 501 is a distortion information input terminal, 502 is a multiplier, 5
03 is an adder, 504 is a selection circuit, 505 is an initialization signal input terminal, 506 is a tap coefficient input terminal, 507 and 50
8 is a tap coefficient output terminal.

In FIG. 5, the input distortion information is multiplied by −α by a multiplier 502, and a selection circuit 504 is added by an adder 503.
, And the result is stored in the tap coefficient memory 112. α is a correction coefficient, usually α <1. In the initial state, the selection circuit 504 outputs 0 as a tap coefficient to all taps of the transversal filter 103 by selecting the GND side, that is, 0, and stores the distortion information multiplied by -α in the tap coefficient memory 112 as it is. .

Now that the description of the specific configuration example of most of the circuits constituting the equalization circuit of FIG. 1 has been completed, returning to FIG. 1 again, the second and subsequent waveform equalization operations will be described. 2
After the first time, the selection circuit 504 (FIG. 5) in the tap coefficient control circuit 111 selects the output from the tap coefficient memory 112,
To the corresponding taps of the transversal filter 103.

The video signal that has passed through the transversal filter 103 is output with less distortion than in the previous time. From this video signal, the GCR signal portion is extracted as in the first time, noise is removed, the delay time is detected, and the ideal GCR signal waveform is subtracted from the signal subjected to the delay time detection processing to obtain distortion information. obtain. The distortion information is multiplied by -α, added to the previous tap coefficient, and stored in the tap coefficient memory 112.

The final equalized waveform can be obtained by repeating such a waveform equalizing operation several times or for a predetermined time. Note that the waveform equalization operation as described above
As described above, the comparison may be performed with successive comparisons. Alternatively, the tap coefficients may be calculated in advance, and the final result may be finally input to the transversal filter 103 to perform waveform equalization.

In the above-described waveform equalization circuit, if a GCR signal is not inserted into an input video signal, if the GCR signal is operated as it is, there is a possibility that an erroneous operation such as adding distortion will occur. . Therefore, in FIG. 1, a GCR detection circuit 113 for detecting the presence or absence of a GCR signal is provided.
When there is no GCR signal, the waveform equalization operation using the GCR signal is stopped, and the waveform equalization using the video waveform is performed.

Generally, the video waveform itself is not a signal having a wide band and a flat gain like a GCR signal, and therefore, it is difficult to directly detect the delay time. However, if the detection of the delay time is repeated many times using various video waveforms, the effect of the video waveform content can be ignored, so that the waveform can be equalized as in the case of using the GCR signal.

In this case, the operation of the noise removing circuit 106 is stopped in FIG.
The integrating operation is performed by causing the integrating circuit 114 connected after 8 to function. Thus, the distortion information output from the delay detection circuit 108 is integrated. If this is repeated many times, it means that the delay has been detected for various video waveforms, and more accurate distortion information can be obtained. This will be described with reference to FIG.

FIG. 10 is a waveform diagram showing a state of waveform equalization when there is no GCR signal. FIG. 10A shows one scanning line of the input video signal on the time axis. When such a signal is input, the signal is deviated on the time axis, so that a noise removing effect cannot be expected. Therefore, the noise removing circuit 106 stops the noise removing operation and outputs the signal to the delay detecting circuit 108. The delay detection circuit 108 performs cepstrum conversion on the input video signal as shown in FIG.

When another video waveform is input, as shown in FIG. 10C, the delay detection circuit 1
At 08, cepstrum conversion is performed and output. The cepstrum-converted video waveform is integrated with the integration circuit 11 in FIG.
The noise is removed by integration at 4. The integrated distortion information is subtracted by the subtractor 109 from the signal output from the reference waveform generation circuit 110, and only the distortion information as shown in FIG. 10D is obtained.

The reference waveform output from the reference waveform generation circuit 110 basically has a video signal band (4.2 MHz).
This signal is a signal obtained by cepstrum-converting the flat signal up to z) by the delay detection circuit 108. However, when the GCR signal is not inserted into the input signal, it is difficult to equalize the waveform to the full band of the video signal. Therefore, the GCR signal detection circuit 11 uses a narrow band signal as a reference waveform.
3 may be switched.

Next, the GC in the GCR detection circuit 113
The presence or absence of the R signal can be detected from the peak position and the magnitude of the peak value of the differentiated GCR signal.
This can be realized by the configuration shown in FIG.

FIG. 7 shows the GCR detection circuit 11 in FIG.
3 is a block diagram illustrating a configuration example of FIG. In FIG. 7, 7
01 is an address signal input terminal of the waveform memory 107;
2 is a GCR signal input terminal (read from the waveform memory 107 and passing through the noise removal circuit 106);
Reference numerals 3 and 705 denote latch circuits, 704, 706 and 707 denote comparison circuits, 708 denotes a gate circuit, 709 denotes an initialization signal output terminal, 710 denotes an input terminal of a signal indicating a reading period of the waveform memory 107, and 711 denotes a difference circuit. .

The GCR signal input from the input terminal 702 takes one clock difference by the difference circuit 711 to form an impulse waveform. The impulse waveform output from the difference circuit 711 is supplied to the latch circuit 705 and the comparison circuit 706. The comparison circuit 706 compares the input and output of the latch circuit 705, and outputs a latch pulse to the latch circuits 705 and 703 when the former is larger than the latter.

As a result, the latch circuit 705 latches the peak value of the signal read and input from the waveform memory 107, and the latch circuit 703 stores the address of the waveform memory 107 in which the signal peak value is stored. But,
Latched. In the comparison circuit 707, the latch circuit 705
If the peak value latched in is smaller than a predetermined value, it is determined that there is no GCR signal.

In the comparison circuit 704, the latch circuit 7
If the address latched at 03 is not within the predetermined range, it is determined that there is no GCR signal. (Because the address where the GCR waveform is stored in the waveform memory 107 is predetermined, a predetermined range including that address is compared. Circuit 7
04, two fixed values are set).

In the gate circuit 708, the waveform memory 107
If the comparison circuit 704 or 707 determines that there is no GCR signal during the readout period, an initialization signal is output. With this initialization signal, the noise removal circuit 106 in FIG. 1 is initialized, and the integration circuit 114 and the reference waveform generation circuit 110 are switched. By holding the initialization signal, the waveform equalization operation can be stopped. However, after the waveform equalization operation has been completed normally, even if it is detected that there is no GCR signal or that there is a GCR signal,
It is not always necessary to initialize.

In this embodiment, the GCR signal is detected using the differentiated waveform. However, the GCR signal can also be detected from the signal before the differentiation, that is, from the output of the noise removing circuit 106. According to this embodiment, when there is a GCR signal, waveform equalization using a GCR signal can be performed, and when there is no GCR signal, waveform equalization using a video waveform can be performed.

Next, a second embodiment of the present invention will be described.
FIG. 11 is a block diagram showing a second embodiment of the present invention. In the second embodiment, in the circuit configuration shown in FIG.
13, instead of from the delay detection circuit 108. Hereinafter, the operation will be described with reference to FIG. FIG. 12 is a waveform diagram showing how the reference waveform is corrected.

Assuming that a video signal having a degraded high-frequency characteristic as shown by a solid line in FIG.
When waveform equalization is performed by the waveform equalization circuit according to the present invention, FIG.
The frequency characteristic is corrected as shown by the dotted line in FIG. However, as for the high-frequency part, it is considered that information is already missing when input to the waveform equalization circuit, so if the waveform equalization is performed as it is to improve the high-frequency characteristics, only the noise component becomes strong. , The video may be very poor in S / N.

Therefore, the output of the first Fourier transform circuit 602 of the delay detection circuit 108 is
To enter. Since the output of the Fourier transform circuit 602 indicates the frequency characteristic of the input signal, it is possible to know how much the high-frequency information has deteriorated. Therefore, if this signal is used to correct the reference waveform for waveform equalization as shown by the solid line in FIG. 12 (b), the high frequency will not be corrected unnecessarily, and the S / N will deteriorate. There is an effect that can be prevented.

Next, a third embodiment of the present invention will be described. FIG. 13 shows a third embodiment of the present invention.
The configuration is such that the subtractor 109 in FIG. 1 is removed. In the present embodiment, the delay detection circuit 108 includes a GCR signal or a video signal output from the noise removal circuit 106,
The reference waveform output from the reference waveform generation circuit 110 is input, and distortion information is output. The output distortion information is integrated only when there is no GCR signal by the integration circuit 114, sent to the tap coefficient control circuit 111, and subjected to waveform equalization. Here, the delay detection circuit 108 will be described in detail.

FIG. 14 shows the delay detection circuit 1 in FIG.
08 is a block diagram showing an internal configuration of a reference numeral 08, where 610 is a subtractor,
Reference numeral 611 denotes a reference waveform input terminal, and the same parts as those in FIG. 6 are denoted by the same reference numerals. The signal output from the Fourier transform circuit 602 is subtracted by the subtractor 610 from the reference waveform input from the reference waveform input terminal 611. This will be described with reference to FIG.

FIG. 15A shows the reference waveform generating circuit 11.
This is a reference waveform output from 0. FIG. 15B shows a waveform in which the input signal is converted into a signal on the frequency axis by the Fourier transform circuit 602. At this time, the subtractor 610 subtracts the two input signals,
A difference signal as shown in FIG. The difference signal indicates the distortion of the input signal as it is, and the transversal filter 103 is used to eliminate the signal.
Is set by the tap coefficient control circuit 111, waveform equalization can be performed.

FIG. 13 shows a third embodiment of the present invention.
In this case, if the reference waveform generation circuit 110 corrects the reference waveform with the output of the Fourier transform circuit 602 as in the second embodiment of the present invention, the same effect as that of the second embodiment can be obtained. be able to.

Further, even in the case of a video signal into which a GCR signal has been inserted, it is conceivable that the frequency characteristic of the video content is deteriorated in a high frequency range, or conversely, is raised. In such a case, by using both the waveform equalization using the GCR signal of the present invention and the waveform equalization using the video signal, there is an effect that the waveform equalization suitable for the video content can be realized. In this case, basic waveform equalization is performed using a GCR signal.

Further, when the frequency characteristic of the input video signal is significantly different from the frequency characteristic of the GCR signal,
Fine adjustment is performed by performing waveform equalization using a video signal. Of course, the waveform equalization using the GCR signal here may be a method using the difference circuit shown in the conventional example.

[0056]

As described above, according to the waveform equalizing circuit of the present invention, even for a video signal into which a GCR signal is not inserted, the waveform equalization is performed by using the video waveform itself for waveform equalization. There are advantages that can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram of a waveform equalization circuit according to the related art.

FIG. 3 is a block diagram illustrating a configuration example of a transversal filter.

FIG. 4 is a block diagram illustrating a configuration example of a noise removal circuit.

FIG. 5 is a block diagram illustrating a configuration example of a tap coefficient control circuit.

FIG. 6 is a block diagram illustrating a configuration example of a delay detection circuit.

FIG. 7 is a block diagram illustrating a configuration example of a GCR detection circuit.

FIG. 8 is a waveform chart showing the operation of the noise removal circuit.

FIG. 9 is a schematic diagram illustrating an operation of the delay detection circuit.

FIG. 10 is a waveform diagram showing a state of waveform equalization when there is no GCR signal.

FIG. 11 is a block diagram showing another embodiment of the present invention.

FIG. 12 is a waveform chart showing how a reference waveform is corrected in another embodiment of the present invention.

FIG. 13 is a block diagram showing still another embodiment of the present invention.

FIG. 14 is a block diagram illustrating a configuration example of a delay detection circuit.

FIG. 15 is a frequency characteristic diagram for explaining the operation of still another embodiment of the present invention.

[Explanation of symbols]

101: video signal input terminal, 102: AD converter, 10
3: Transversal filter, 104: DA converter,
105: video signal output terminal, 106: noise removal circuit,
107 ... waveform memory, 108 ... delay detection circuit, 109 ...
Subtractor, 110: Reference waveform generation circuit, 111: Tap coefficient control circuit, 112: Tap coefficient memory, 113: GC
R detection circuit

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroshi Sekiya 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Image Information Systems Co., Ltd. (72) Inventor Toshiyuki Kurita 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Co., Ltd. Hitachi, Ltd. Video Media Research Laboratories (72) Inventor Toshinori Murata 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Within Hitachi Media Video Research Laboratories Co., Ltd. (56) References JP-A-1-280970 (JP, A) JP-A-3-110977 (JP, A) JP-A-3-10469 (JP, A) JP-A-63-107371 (JP, A) JP-A-2-285866 (JP, A) (58) Int.Cl. ⁶ , DB name) H04N ^5/ 14-5/217

Claims (9)

(57) [Claims] 1. A transversal filter for changing the frequency characteristic of an input video signal according to a controlled tap coefficient and outputting the output signal, and averaging the output from the transversal filter for several fields, thereby providing Noise removing means for removing and outputting included noise, first storage means for storing an output from the noise removing means,
A delay detecting means for detecting a delay time of a distortion component contained therein from an output read from the first storage means, and outputting a delay waveform of the distortion component by the delay time; A reference waveform generating means for outputting a reference waveform, a subtracting means for performing a subtraction between an output from the reference waveform generating means and an output from the delay detecting means and outputting a result; Tap coefficient control means for calculating a tap coefficient of the transversal filter, and a second storage means for storing a control output from the tap coefficient control means,
A ghost removal reference signal detecting means for detecting whether or not a ghost removal reference signal is inserted into the input video signal, and determining that the ghost removal reference signal is not inserted. Is provided with an integrating means for stopping the function of the noise removing means, removing the noise contained therein by integrating the output of the delay detecting means, and supplying the noise to the subtracting means. A waveform equalization circuit, which functions and performs waveform equalization using an arbitrary video waveform instead of a ghost removal reference signal. 2. A ghost elimination circuit according to claim 1, wherein said ghost elimination reference signal detecting means determines that a ghost elimination reference signal is inserted in the input video signal. A waveform equalizing circuit characterized in that waveform equalization is performed using a reference signal for use. 3. The waveform equalization circuit according to claim 1, wherein the ghost elimination reference signal detection unit detects an address in the first storage unit of an output read from the first storage unit. First latch means to be input and latched, first comparison means for determining whether or not the output of the first latch means is within a predetermined value range; and the first storage means. Means for receiving the output signal read from the means, and when the reference signal for ghost removal is included therein, taking the difference and outputting the result; and And a second comparing means for comparing the input and the output of the second latch means with each other, and when the former is larger than the latter, giving a latch pulse to each of the first and second latch means to perform latching. Means and said second rack. A third comparing means for determining whether or not an output of the means exceeds a predetermined value; and a determination result of the first comparing means during the output reading period from the first storage means. A gate means for outputting a signal indicating the presence / absence of the obtained ghost removal reference signal depending on a result of the determination by the comparing means. 4. The waveform equalizing circuit according to claim 1, wherein the reference waveform generating means detects that the ghost removing reference signal is not inserted into the video signal by the ghost removing reference signal detecting means. And a waveform generating means for controlling a generated waveform by an output to that effect. 5. The waveform equalizing circuit according to claim 1, wherein the delay detecting means converts a signal on a time axis, which is an input signal, into a signal on a frequency axis and outputs the converted signal. A second conversion means for performing logarithmic conversion on an output of the first conversion means and outputting the result, a third conversion means for converting an output of the second conversion means into a signal on a time axis and outputting the signal, A waveform equalizing circuit comprising: 6. The waveform equalization circuit according to claim 5, wherein the reference waveform generating means detects that the ghost removal reference signal is not inserted in the video signal, in the ghost removal reference signal detection means. A waveform generating means for controlling a generated waveform by an output of the first converting means in the delay detecting means. 7. A transversal filter for changing the frequency characteristic of an input video signal according to a controlled tap coefficient and outputting the output signal, and averaging the output from the transversal filter for several fields, thereby providing Noise removing means for removing and outputting included noise, first storage means for storing an output from the noise removing means,
Reference waveform generating means for outputting a predetermined reference waveform; delay detection for receiving an output read from the first storage means and an output from the reference waveform generating means to detect and output distortion information; Means, a required tap coefficient based on distortion information from the delay detecting means, a tap coefficient control means for controlling a tap coefficient of the transversal filter in accordance therewith, and a control output from the tap coefficient control means are stored. A ghost elimination reference signal detecting means for detecting whether or not a ghost elimination reference signal is inserted into the input video signal, wherein the ghost elimination reference signal is inserted. If it is determined that the delay has not been performed, the function of the noise removal unit is stopped, and the output of the delay detection unit is integrated. Providing an integrating means for removing noise contained therein and supplying the same to the tap coefficient control means to function, and performing waveform equalization using an arbitrary video waveform instead of the ghost removing reference signal A waveform equalizing circuit. 8. The waveform equalization circuit according to claim 7, wherein the delay detection means receives a signal on the time axis, which is an output read from the first storage means, and receives the signal on the frequency axis. First conversion means for converting the signal into a signal and outputting the signal, and subtraction means for receiving an output from the reference waveform generation means and performing a subtraction between the signal and the output of the first conversion means and outputting the result And second conversion means for performing logarithmic conversion on the output of the subtraction means and outputting the result, and third conversion means for converting the output of the second conversion means into a signal on the time axis and outputting the signal. A waveform equalization circuit characterized by the above-mentioned. 9. The waveform equalizing circuit according to claim 1, wherein said delay detecting means detects a delay with respect to the ghost removing reference signal and also performs an arbitrary video waveform in place of the ghost removing reference signal. A waveform equalizing circuit for detecting a delay and outputting both results.