JP2793396B2 - Computer status holding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a status information holding device for an electronic computer, which is capable of reliably recognizing the operation status of an operation instruction in an electronic computer performing a pipeline operation.

[0002]

2. Description of the Related Art Conventionally, there are many electronic computers which execute a pipeline operation as shown in FIG. 4 in order to further improve the operation performance.

In this pipeline operation, for example, the first operation instruction OP-1 is fetched (F), and during the next machine cycle, this operation instruction OP-1 is decoded (D), and in parallel with this. Fetches the next operation instruction OP-2, further executes (E) the first operation instruction OP-1 during the next machine cycle, and executes the operation instruction OP-2.
Is decoded, and a new operation instruction OP-3 is fetched. In the next cycle, the operation method is such that the processing result is written back (W) and the new instruction is fetched for the operation instruction OP-1 whose execution processing is completed. In other words, even if the execution stage does not end in one pipeline cycle, the subsequent instruction is sequentially fetched and executed, including the instruction using the same arithmetic unit, without stopping the instruction pipeline. .

In an electronic computer that performs such a pipeline operation, when an operation error occurs, it is difficult to specify the instruction that caused the error or the destination register of the operation to be operated during recovery. Or it was impossible. That is, even if an error accompanied by an operation error interrupt occurs during the execution of a pipeline operation, all instructions fetched before the occurrence of the error are completed so as not to cause inconsistency in operation after returning from the interrupt routine. The execution of the operation error interrupt routine is started after the execution of the operation error interrupt. As a result, at the start of the operation error interrupt, another instruction following the instruction in which the operation error has occurred has already been executed. . For this reason, conventionally, it has often been abandoned that an operation error occurrence location cannot be specified at the instruction word level.

For example, when an operation error occurs during execution (E) of the operation instruction OP-1 in FIG. 4, the operation status is written into the operation status flag, and the next operation instruction OP-2, OP-3 is executed. Is also written in the operation status flag. Thereafter, the operation status written in the operation status flag at the time of jumping into the interrupt routine is the operation instruction OP-2. Therefore, the operation status in which the operation error has occurred cannot be specified, so that error recovery becomes impossible. Sometimes.

In particular, parallel processors which can simultaneously use a plurality of different arithmetic units in the execution stage (E) are highly used, and it has not been easy to correctly recognize the order and execute an accurate recovery process.

When referring to the operation status of a floating-point operation instruction requiring a plurality of cycles for execution shown in FIG. 5, a floating-point addition instruction "A" is set in an operation status flag at the fifth pipeline cycle. Therefore, the operation status of the floating-point multiplication instruction “M” cannot be set. Therefore, the floating-point multiplication instruction “M”
When the operation status flag is referred to by the instruction "G" that refers to the operation status of the multiplication instruction "M" to be referred to during the period S, the operation status is not set. The hatched portions in the figure represent wasted time, and it was not easy to prevent a decrease in pipeline processing efficiency.

As described above, in a conventional computer that performs a pipeline operation, the possibility of error recovery is small, and reliability tends to be sacrificed to some extent for high performance. Conversely, in a computer characterized by high reliability, for example, when the execution stage of the instruction pipeline exceeds one machine cycle, the instruction pipeline is stalled and only one instruction is present in the execution stage. For example, there is a tendency that the location where an arithmetic error occurs is identified and the recovery process is enabled, even if the performance is not improved further by controlling the arithmetic pipeline by giving control such that the arithmetic error does not occur.

[0009]

As described above, in a conventional computer which performs a pipeline operation, it is extremely difficult to specify an operation error occurrence portion at an instruction word level, and the operation errors overlap. If, that is,
If another operation error occurs between the time when the first operation error occurs and the time when all fetched instructions have completed and jumped to the operation error interrupt routine, it is extremely difficult to specify the number of occurrences and the order. However, even if high performance can be achieved, there is a small possibility that accurate recovery of an operation error can be realized, and high reliability cannot be ensured.

SUMMARY OF THE INVENTION The present invention has been made to address such a conventional problem. An object of the present invention is to enable an electronic computer which performs a pipeline operation for high performance to reliably recognize the operation status of an operation instruction. To provide an operation status holding device for an electronic computer that can easily recognize an operation result of the operation instruction and can also have a highly reliable recovery function against an operation error without sacrificing operation performance. It is in.

[0011] To achieve the above object, the present invention provides:
In an operation status holding device for an electronic computer that performs a pipeline operation, an operation status holding means provided in one-to-one correspondence with each register that can be designated as a destination operand of an operation instruction, Status setting means for setting an operation status indicating a state in the operation status holding means.

In the operation status holding device for an electronic computer according to the present invention, the status setting means has a one-to-one correspondence between the operation status indicating the operation result state of the operation instruction and each register which can be specified as a destination operand of the operation status instruction. Is set in the operation status holding means provided correspondingly. Therefore, the operation result of the operation instruction can be easily recognized. In particular, when an operation error occurs, the operation instruction in which the operation error has occurred can be recognized by checking the operation status held in the operation status holding means. The recovery function can be highly reliable.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. An operation status holding device of an electronic computer according to this embodiment includes an operation unit 1 capable of executing a pipeline operation and an operation instruction A register file 3 composed of registers r0 to rn specified and used as operands, and registers r0, r1,
r2... rn, a status flag F corresponding to one-to-one
.., Fn, and has an operation status flag string 5 for storing an operation status indicating the execution result of the operation instruction in a status flag string corresponding to the operation destination register. The operation status flag string 5 constitutes the operation status holding means of the first aspect.

Further, the operation status holding device of this embodiment saves the operation status to the flags f0, f1, f2,..., Fn in the operation status flag column 5 corresponding to the destination register of the operation. It has.

Next, the operation of the operation status holding device of the computer having the above configuration will be described.

As shown in FIG. 2, the computer processes instructions in a pipeline manner, and the instruction pipeline has four stages of fetch (F), decode (D), execution (E), and write-back (W). The operation unit 1 is constituted by stages, and can perform a pipeline operation.

Here, for example, the first operation instruction OP-1
If an operation error occurs during the execution stage (E) of
The control device 7 sets the operation status of the operation instruction OP-1 in the flag f0 of the operation status flag column 5 provided on a one-to-one basis in the register file 3 of the operation destination register of the operation instruction OP-1. . Also,
The control device 7 calculates the operation status of the next operation instruction OP-2 at the execution stage (E) in the operation status flag column 5.
To the flag f3. Further, the operation status of the operation instruction OP-3 in the execution stage (E) is stored in the control device 7.
Is set to the flag f1 of the operation status flag column 5. When an operation error occurs in the operation instruction OP-1, the interrupt routine sequentially checks the flags set in the flags f0, f1,... It can be determined whether or not an operation having the destination as has occurred.

Further, a case of referring to the operation status of a floating-point operation instruction requiring a plurality of cycles for execution will be described with reference to FIG.

In the figure, the first operation instruction “A” is a floating point addition instruction (FADD),
“M” is a floating point multiplication instruction (FMULL).
“G” is an instruction (GSTAT) that refers to the operation status of “M”.

First, the first operation instruction [A] is fetched (F) and decoded (D), and at the same time, the operation instruction "M" is fetched (F). Then, in the next pipeline cycle, the operation instruction [A] is executed (E), and the operation instruction “M” is decoded (D).
The operation instruction “G” is fetched (F). In this case, the operation instruction “A” is locked to f1 of the operation status flag column 5.

In the next pipeline cycle, the operation instruction "M" is locked to the flag f7 of the operation status flag column 5. Then, in the next pipeline cycle, the operation instruction “A” ends the execution stage (E), and the operation status is set to the flag f 1 of the operation status flag column 5. At this time, the reference instruction “G” of the operation status of “M”, which is a floating-point multiplication instruction, is shifted to the execution stage (E). Further, in the next pipeline cycle, the operation instruction “A” is shifted to write back (W), and after three pipeline cycles, the operation status of the floating-point multiplication instruction “M” is changed to the operation status flag column. 5 is set to the flag f7, and the operation shifts to write-back (W) in the next pipeline cycle.
At this time, the reference instruction “G” for the floating-point multiplication is in the execution stage (E), and is shifted to write-back (W) in the next pipeline cycle.

Thus, the operation can be executed without stopping the pipeline processing, so that the efficiency of the operation processing can be improved as compared with the conventional processing shown in FIG.

As described above, since the operation status of each operation instruction is set in the operation status flag column 5, it is possible to accurately obtain operation error information at the time of execution of a pipeline operation, and to sacrifice high-speed performance. Therefore, the possibility of error recovery can be greatly improved.

The present invention is not limited to the above-described embodiment, but can be widely applied to general electronic computers that perform pipeline operations.

[0026]

As described above, according to the present invention, the operation status holding means corresponding to each register which can be specified as the destination operand of the operation instruction on a one-to-one basis is provided to indicate the state of the operation result of the operation instruction. Since the operation status is set in the operation status holding means, the operation status of the operation instruction can be reliably recognized in the computer performing the pipeline operation for high performance, and the recognition of the operation result of the operation instruction can be performed. Thus, the recovery function for the operation error can be made highly reliable without sacrificing the operation performance.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 3 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 4 is an explanatory diagram showing a conventional operation.

FIG. 5 is an explanatory diagram showing a conventional operation.

[Explanation of symbols]

 Reference Signs List 1 arithmetic unit 3 register file 5 operation status flag string 7 controller r0, r1, r2, ..., rn register f0, f1, r2, ..., rn operation status flag

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/38 G06F 11/34

Claims (1)

(57) [Claims] 1. An operation status holding device for an electronic computer that performs a pipeline operation, comprising: an operation status holding means provided in one-to-one correspondence with each register that can be specified as a destination operand of an operation instruction; And a status setting means for setting, in the operation status holding means, an operation status indicating a state of the operation result of the instruction.