JP2793386B2 - Computer error information storage device for computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic error information holding device for an electronic computer which holds arithmetic error information in an electronic computer which performs a pipeline arithmetic operation.

[0002]

2. Description of the Related Art Conventionally, there are many electronic computers which execute a pipeline operation as shown in FIG. 3 in order to further improve the operation performance.

In this pipeline operation, for example, the first operation instruction OP-1 is fetched (F), and during the next machine cycle, this operation instruction OP-1 is decoded (D), and in parallel with this. Fetches the next operation instruction OP-2, further executes (E) the first operation instruction OP-1 during the next machine cycle, and executes the operation instruction OP-2.
Is decoded, and a new operation instruction OP-3 is fetched. In the next cycle, the operation method is such that the processing result is written back (W) and the new instruction is fetched for the operation instruction OP-1 whose execution processing is completed. In other words, even if the execution stage does not end in one pipeline cycle, the subsequent instruction is sequentially fetched and executed, including the instruction using the same arithmetic unit, without stopping the instruction pipeline. .

In an electronic computer that performs such a pipeline operation, when an operation error occurs, it is difficult to specify the instruction that caused the error or the destination register of the operation to be operated during recovery. Or it was impossible. That is, even if an error accompanied by an operation error interrupt occurs during the execution of a pipeline operation, all instructions fetched before the occurrence of the error are completed so as not to cause inconsistency in operation after returning from the interrupt routine. The execution of the operation error interrupt routine is started after the execution of the operation error interrupt. As a result, at the start of the operation error interrupt, another instruction following the instruction in which the operation error has occurred has already been executed. . For this reason, conventionally, it has often been abandoned that an operation error occurrence location cannot be specified at the instruction word level.

In addition, when an operation error accompanied by an operation error interrupt occurs in an operation unit that performs a pipeline operation, in order to prevent inconsistency in the operation after the return from the interrupt, the execution and execution of all instructions fetched up to that time can be performed. In other words, there is a case where it is necessary to actually interrupt after the write-back stage (W) of the instruction pipeline is completed. At this time, an operation error interrupt is issued by a certain instruction as shown in FIG. An accompanying error (arithmetic error 1) occurs, and while waiting for the completion of execution of all the already fetched instructions OP-2, OP-3, OP-4, an arithmetic error (arithmetic error 2) also occurs in those instructions. When this occurs, a plurality of calculation errors have occurred at the point of jumping into the calculation error interrupt processing routine.

However, such second and third errors are usually overlooked, and only incomplete error information is actually obtained.

Further, when pipeline operation instructions having different numbers of execution cycles are arranged close to each other, instruction execution is completed in an order different from the fetch order as shown in OP-3 and OP-4 shown in FIG. However, in such a case, the order in which the operation error occurs may be opposite to the order of the fetch. In particular, the execution stage (E)
Therefore, the possibility is high in a parallel processing processor that can simultaneously use a plurality of different processors, and it is not easy to recognize the order correctly and to execute an accurate recovery process.

As described above, in a conventional computer that performs a pipeline operation, the possibility of error recovery is small, and reliability tends to be sacrificed to some extent for high performance. Conversely, in a computer characterized by high reliability, for example, when the execution stage of the instruction pipeline exceeds one machine cycle, the instruction pipeline is stalled and only one instruction is present in the execution stage. For example, there is a tendency that the location where an arithmetic error occurs is identified and the recovery process is enabled, even if the performance is not improved further by controlling the arithmetic pipeline by giving control such that the arithmetic error does not occur.

[0009]

As described above, in a conventional computer which performs a pipeline operation, it is extremely difficult to specify an operation error occurrence portion at an instruction word level, and the operation errors overlap. If, that is,
If another operation error occurs between the time when the first operation error occurs and the time when all fetched instructions have completed and jumped to the operation error interrupt routine, it is extremely difficult to specify the number of occurrences and the order. However, even if high performance can be achieved, there is a small possibility that accurate recovery of an operation error can be realized, and high reliability cannot be ensured.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and in an electronic computer which performs a pipeline operation for improving performance, error information of operation instructions executed in parallel is accurately recognized. It is an object of the present invention to provide an operation error information holding device for an electronic computer, which can make a recovery function for an operation error highly reliable without sacrificing the operation performance.

[0011]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to an operation error information holding device for an electronic computer which performs a pipeline operation, comprising a plurality of registers which can be designated as destination operands of an operation instruction. An operation status register provided for each operation, a destination register number holding means capable of holding a plurality of destination register numbers of operation instructions, and a register corresponding to the register for holding the operation result each time an operation is completed. An operation status holding control means for holding the operation status, and for each operation executed from the time of occurrence of the operation error to the time of occurrence of the operation error interrupt, the destination register number is sequentially changed each time the operation is completed. The data to be held by the destination register number holding means It is obtained by a destination register number retaining means.

[0012]

In the arithmetic error information holding device for an electronic computer according to the present invention, the arithmetic status holding control means holds the arithmetic status corresponding to the register holding the arithmetic result each time an arithmetic operation is completed. The destination register number holding control means sequentially changes the destination register number every time the operation is completed from the time of the occurrence of the operation error to the time of the occurrence of the operation error interrupt. It is held by the holding means.

In this way, when an operation error occurs, the destination register of the operation instruction in which the error has occurred can be directly known by the destination register number holding means, and the operation instruction held in the destination register number holding means can be obtained. Operation status can be known by the operation status holding means corresponding to the destination register. Furthermore, the presence or absence of the operation from the occurrence of the operation error to the occurrence of the interrupt, and the completion order of the operations, if any, It is also possible to know whether or not an operation error has occurred, and it is possible to increase the possibility of recovery from the operation error without sacrificing performance.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. An arithmetic error information holding device of an electronic computer according to this embodiment includes an arithmetic unit 1 capable of executing a pipeline arithmetic, and an arithmetic instruction. , And a register file 2 including registers r0 to rn to be used and registers r0 and r of the register file 2
1, r2,... Rn, each of which has a status register s0, s1, s2,..., Sn corresponding to a one-to-one correspondence, and stores a calculation status in a status register corresponding to a calculation destination register. A holding means 3 is provided.

Further, the operation error information holding device of this embodiment has the operation destination register numbers 0, 1,
Registers dn0 and dn for holding 2,..., N
1. dn6, dn2,... dn6.

When an error accompanied by an operation error interrupt occurs, the destination register number holding means 4 stores the operation result in the register file 2 until the completion of all the plurality of instructions fetched up to that point. Each time write-back is performed, the numbers of the written-back registers are stored in the registers dn0 to dn6 in order.

In the illustrated embodiment, the destination register number holding means 4 is composed of seven from 0 to 6, but this number is generally determined as shown in FIG. decide. That is, the number of registers is the maximum number of instructions that can be written back from the time of occurrence of an error accompanied by an operation error interrupt to the completion of all instructions fetched so far.

The registers dn0, dn1,..., Dn
Each of Nos. 6 includes register number fields for the maximum number of operation instructions that can simultaneously reach the write-back stage in the instruction pipeline. Then, even if the maximum number of operation instructions enter the write-back stage at the same time, all the numbers of the destination registers are simultaneously held in any one of the registers dn0, dn1,..., Dn6. In general, the maximum number, that is, the number of register number fields in each destination register number holding register is equal to the number of arithmetic units 1.

Further, the operation error information holding device of this embodiment saves the operation status in the registers s0, s1, s2,..., Sn in the operation status holding means 3 corresponding to the destination register of the operation. ,
When an error accompanied by an operation interrupt occurs and an operation error is detected based on the operation status or the like, the number of the register to be written back as the operation result is stored in the registers dn0, dn1,.
The control device 5 sequentially records data to the dn 6.

Next, the operation of the operation error information holding device of the electronic computer having the above configuration will be described.

The computer processes instructions in a pipeline manner as shown in FIG. 2, and the instruction pipeline is composed of fetch (F), decode (D), execution (E), and write-back (W). The operation unit 1 is capable of performing a pipeline operation, and an operation error occurs only in the write-back stage. In the embodiment of FIG. 1, the instruction fetched by the time the operation error occurs The operation of this embodiment will be described below, assuming that the maximum number of write-backs of the operation result that can occur until all the operations are completed is seven.

In the write back stage of the operation,
The write-back target registers, that is, the destination registers r0, r1, r2,.
n, the status holding registers s0, s1, s
The control status is written by the control device 5 to any of 2, 2,..., Sn.

When an error accompanied by an arithmetic error interrupt occurs, the destination register number is first stored in the register dn0 of the destination register number holding means 4 by the mechanism of the control device 5, as shown in FIG. Write.

After that, when performing a pipeline operation, after returning from the interrupt, fetching of a new instruction is stopped in order to continue the operation without inconsistency, and interrupt is performed after all instructions fetched so far are completed. In the meantime, each time the operation instruction of the instruction enters a write-back cycle, as shown in FIG. 2, the operation of the status registers s0 to sn constituting the status register holding means 3 is performed in the same manner as described above. The operation status is written to the destination register, that is, the register corresponding to the write-back target register, and the number of the destination register is written to the registers dn1 to dn6 of the destination register number holding means 4.

As a result, when an operation error interrupt occurs, the destination register number of the operation that caused the interrupt can be directly known from the information stored in the register dn0 of the destination register number holding means 4.
The operation status can be known at the same time.

Further, based on the information stored in the registers dn1 to dn6 of the destination register number holding means 4, for all the operation instructions executed from the time of the occurrence of the operation error to the time of the occurrence of the interrupt, the ending order and the termination order thereof are obtained. The destination register number of the instruction can be known. In addition, whether or not an error has occurred in these calculations, and if an error has occurred, the status of the calculation can be known from the status register of the corresponding calculation status holding unit 3 as in the first calculation status. it can.

As described above, operation error information at the time of execution of a pipeline operation can be accurately obtained, and the possibility of error recovery can be greatly improved without sacrificing high-speed performance.

The present invention is not limited to the above embodiment, but can be widely applied to general electronic computers that perform pipeline operations.

[0030]

As described above, according to the present invention, each time an operation is completed, the operation status is held in the operation status register of the corresponding number by the operation status holding control means. When an error accompanied by an operation error interrupt occurs, the interruption is delayed, and the destination register numbers of all the operations during the operation are sequentially stored in the destination register number holding means each time the operation is completed. Therefore, when an operation error occurs, the destination register of the operation instruction in which the error occurred can be directly known by the destination register number holding means, and the operation instruction held in the destination register number holding means can be obtained. The calculation stator Can be known by the operation status holding means corresponding to the destination register. In addition, the presence / absence of the operation from the occurrence of the operation error to the occurrence of the interrupt, the completion order of the operation if any, and the operation It is also possible to know whether or not an error has occurred, and it is possible to increase the possibility of recovery from an operation error without sacrificing performance.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 3 is an explanatory diagram illustrating a general pipeline operation operation.

FIG. 4 is a block diagram of a conventional example.

[Explanation of symbols]

Reference Signs List 1 arithmetic unit 2 register file 3 arithmetic status holding means 4 destination register number holding means 5 controller r0, r1, r2, ..., rn registers s0, s1, s2, ..., sn arithmetic status registers dn0, dn1, dn2, ... , Dn6 Destination register number register

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Ikuo Uchibori 1 Toshiba-cho, Fuchu-shi, Tokyo Toshiba Corporation Fuchu Plant (56) References JP-A-5-143338 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) G06F 9/38

Claims (1)

(57) [Claims] 1. An operation error information holding device for an electronic computer that performs a pipeline operation, comprising: an operation status register provided for each of a plurality of registers that can be specified as a destination operand of the operation instruction; A destination register number holding means capable of holding a plurality of numbers; an operation status holding control means for holding the operation status corresponding to the register for holding the operation result each time an operation is completed; Thus, for all the operations executed until the occurrence of the operation error interrupt, the destination register number holding means for holding the destination register number in the destination register number holding means sequentially every time the operation is completed. Electricity provided Calculating the error information storage device of the computer.