JP2793357B2 - Parallel processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention executes a plurality of conditional branch instructions simultaneously and in parallel, and selects an address in which subsequent instructions are set. About.

(Prior Art) In recent years, various parallel execution methods have been proposed along with an increase in the amount of computation required for a processor. As shown in FIG. 6, a conventional parallel execution type processor (parallel operation device) includes a plurality of operation units 601 to 602 and a memory divided into many banks. The connection with each memory bank can be arbitrarily made. Then, the operations performed by these arithmetic units 601 to 602 and the connection with each memory bank are controlled in parallel, and a plurality of operations are executed in parallel in the same cycle.

On the other hand, one of important operations at the time of execution of an operation by the parallel operation device is a conditional branch operation performed at the time of execution of a conditional branch instruction. This is because when the branch condition specified in the conditional branch instruction and the flag register 603 satisfy a certain relationship, the value of the instruction pointer 604 is rewritten to the address also specified in the conditional branch instruction, and as a result, The branch condition is set to the address specified in the branch instruction.
Note that the flag register 603 is rewritten according to the output result of the arithmetic unit 602, and generally includes a plurality of bits. For example, it has a bit that is rewritten to logic 1 when the output of the arithmetic unit 602 becomes zero, or a bit that is rewritten to logic 1 when the output of the arithmetic unit 602 becomes negative.

Here, in the conventional parallel operation device as shown in FIG.
Despite having a plurality of computing units 601-602, the flag register is a flag register 603 attached to one computing unit 602.
Has only one. For this reason, there has been a great restriction in setting the branch condition at the time of conditional branch.

For example, the operation represented by the flowchart shown in FIG.
That is, when variable A <constant C and modification B = constant D, processing 1
In other cases, an operation such as Execute process 2 is considered. FIG. 8 shows the contents of the instruction memory in this case. In FIG. 8, a BC instruction is set at an address which is incremented by one from the address where the AC instruction is set. The execution instruction of the process 1 is set at an address that is incremented by one from the address where the BC instruction is set. Further, an execution instruction of the process 2 is set at a certain branch destination address.

In order to test such an operation, first, AC is performed using the arithmetic unit 602, and the bits of the flag register 603 are rewritten according to the sign of the output. In the control circuit 605, A
From the value of the bit of the flag register 603 indicating the result of −C, it is determined whether or not A <C holds. A <C
Is not established, the instruction pointer 604 is rewritten to the branch destination address where the execution instruction of the process 2 is set (conditional branch is established). Accordingly, when A <C is not satisfied, the process 2 is executed. On the other hand, if the condition is satisfied, the instruction pointer 604 is incremented by 1 (conditional branch is not satisfied). Since the BC instruction is set at the address of the instruction pointer 604 which is incremented by one, the arithmetic unit 602 executes this instruction again.

According to the sign of the execution result, the bit of the flag register 603 is rewritten again, and B = C
Is determined by the control circuit 605. B
If = C is not established, branch to the branch destination address,
Process 2 is executed (conditional branch taken). If the condition is satisfied, the instruction pointer 604 is incremented by 1 and the process 1 is executed (conditional branch is not satisfied).

By executing the above procedure, the processing flow shown in FIG. 7 is realized.

Thus, in the conventional parallel operation device, one operation unit
At 602, a plurality of conditional branch instructions are sequentially executed, and it is determined whether or not the condition is satisfied each time. Therefore, the operation unit 60
While 2 was executing the conditional branch instruction, the arithmetic units 601 to 602 could not be used for the original purpose of signal processing, and the remaining arithmetic units could not execute anything during that period.

(Problems to be Solved by the Invention) As described above, in the conventional parallel operation device, execution of a program including a large number of conditional branches has a very long execution time despite the use of a plurality of operation units. Had to be spent.

Accordingly, the present invention has been made in view of the conventional circumstances, and has as its object to execute a plurality of conditional branch instructions simultaneously and in parallel by a plurality of arithmetic units, and to execute a program including a large number of conditional branches. Another object of the present invention is to provide a parallel operation device capable of improving the operation processing capacity.

[Configuration of the Invention] In order to achieve the above object, the present invention provides a plurality of arithmetic means for simultaneously executing a plurality of arithmetic operations in accordance with a plurality of conditional branch instructions in parallel, and a plurality of arithmetic means corresponding to each of the plurality of arithmetic means. A plurality of comparison means for comparing the operation result obtained by the operation means with the branch condition of the conditional branch instruction to determine whether or not the operation result satisfies the branch condition; Logic operation means for performing a logical operation in accordance with the relationship between the plurality of conditional branch instructions provided simultaneously with the comparison result, based on the plurality of comparison results obtained, and an operation result obtained by the logical operation means, Selecting means for selecting an address in which an instruction to be executed after the plurality of conditional branch instructions is set.

(Operation) With the configuration described above, the present invention allows a plurality of arithmetic units to execute a plurality of operations in accordance with a plurality of conditional branch instructions in parallel. The operation result obtained by the operation unit is output to a flag register provided corresponding to each of the plurality of operation units.

In the flag register, the bit content is rewritten to the content according to the operation result. The rewritten bit contents are
Like the flag register, the data is output to a comparison circuit provided for each of the plurality of arithmetic units.

The comparison circuit compares the bit content output from the flag register with a branch condition of a conditional branch instruction provided from the instruction memory. That is, the comparison circuit determines whether the operation result obtained by the operation unit satisfies the branch condition. The plurality of comparison circuits output respective comparison results to the logic circuit.

In this logic circuit, a logical operation is performed using a plurality of comparison results. At this time, a logical operation (for example, a logical sum, a logical product, etc.) according to a relationship between a plurality of conditional branch instructions is performed. Further, the operation result is output from the logic circuit to the selection circuit.

The selection circuit selects an address in the instruction memory in which an instruction to be executed after a plurality of conditional branch instructions is set according to the operation result.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment relating to a parallel operation device of the present invention.

The parallel operation device in FIG.
2. It is composed of flag registers 103 to 105, comparison circuits 113 to 115, logic circuit 116, instruction pointer 111, selection circuit 112, memory, and instruction memory. Flag register 10
3 to 105 and comparison circuits 113 to 115 are provided corresponding to the arithmetic units 101 to 102, respectively.

The arithmetic units 101 to 102 execute a plurality of operations in parallel according to a plurality of conditional branch instructions provided from the instruction memory.

The flag registers 103 to 105 use
This is a register for rewriting the contents according to the operation results output from 101 to 102.

The comparison circuits 113 to 115 have a function of comparing the bit contents of the flag registers 103 to 105 with the branch condition read from the instruction memory. As a result, the comparison circuit 113
To 115 determine whether or not the operation results executed by the computing units 101 to 102 satisfy the branch condition.

The logic circuit 116 will be described in detail later.
5 performs the logical operation of the plurality of comparison results output from each other. In this logical operation, a logical operation (logical product, logical sum, etc.) according to the relationship between a plurality of conditional branch instructions is performed.

The selection circuit 112 is to select an address in the instruction memory in which an instruction to be executed after a plurality of conditional branch instructions is set according to the operation result output from the logic circuit 116. Specifically, a branch destination address given from the instruction memory or an address obtained by incrementing the current value of the instruction pointer 111 by one is selected.

The instruction pointer 111 inputs the address selected by the selection circuit 112 and outputs it to the instruction memory.

The present invention is configured as described above, and the operation of the present invention will be described below.

Operation units 101 to 1 from multiple conditional branch instructions from instruction memory
When given to 02, a plurality of operations in accordance with these conditional branch instructions are executed in parallel by the arithmetic units 101 to 102 in parallel. These operation results are output from the arithmetic units 101 to 102 to the flag registers 103 to 105. As a result, the bit contents of the flag registers 103 to 105 are rewritten to contents corresponding to the operation result.

The rewritten bit contents of the flag registers 103 to 105 are supplied to comparison circuits 113 to 115 through signal lines 106 to 108.

By the comparison circuits 113 to 115, the branch condition given from the instruction memory through the signal lines 117 to 119 and the flag register 10
The outputs 106 to 108 of 3 to 105 are compared. That is, it is determined whether or not the calculation results of the calculators 101 to 102 satisfy the branch condition. The result is given to the logic circuit 116 through the signal lines 120 to 122.

To the logic circuit 116, information indicating the relationship between the plurality of conditional branch instructions is given from the instruction memory via the signal line 123 at the same time as the comparison result. In the logic circuit 116, a plurality of comparison results of the comparison circuits 113 to 115 are logically operated according to a relationship between a plurality of conditional branch instructions. From the result of this logical operation, a selection signal 125 to the selection circuit 112 is generated.

According to the selection signal 125, the selection circuit 112 selects whether the input of the instruction pointer 111 is a branch destination address given through the signal line 124 or whether the current value of the instruction pointer 111 is incremented by one. At this time, if the branch condition is satisfied, the instruction pointer 11
A branch destination address given through the signal line 124 as an input of 1 is selected. As a result, a branch operation is performed (conditional branch is established). On the other hand, if the branch condition is not satisfied, the signal line 126 obtained by incrementing the current value of the instruction pointer 111 by one is selected. As a result, the instruction pointer 111 is incremented by one instead of being rewritten to the branch destination address. (Conditional branch not taken).

FIG. 2 shows a detailed diagram of the logic circuit 116. here,
Although two examples of the flag registers 103 and 105 are given for simplicity of explanation, a similar configuration is of course possible with a plurality of flag register configurations.

Outputs 106 and 108 from the flag registers 103 and 105 are input to comparison circuits 113 and 115, respectively. A signal 117 representing a branch condition according to condition 1 set in the jump instruction is compared with a signal 119 representing a branch condition according to condition 2, and it is determined whether or not each branch condition is satisfied. The outputs 120 and 122 are input to a logic circuit 116, and a logical operation is performed in accordance with a signal 123 indicating a mutual relationship between the condition 1 and the condition 2 similarly set in the jump instruction. Then, one of the outputs is selected, and a selection signal 125 to the selection circuit 112 is generated. In this embodiment, the condition 1
And the condition 2 show four cases of a logical sum, a logical product, only the condition 1, and only the condition 2, but other logical operations can be set.

According to the generated selection signal 125, the selection circuit 112 selects either the branch destination address set in the instruction or the value obtained by incrementing the instruction pointer by one.

Next, the operation of the present invention will be described using a specific conditional branch instruction.

For example, consider a conditional branch instruction represented by a processing flow as shown in FIG.

In the case of such an instruction, the arithmetic unit 101, the flag register 103, and the comparison circuit 113 determine the condition A,
The arithmetic unit 102, the flag register 105, and the comparison circuit 115 determine the condition B. Logic circuit 116 from instruction memory
The signal 123 given to the signal represents a logical product based on the correlation between the condition A and the condition B. Thereby, the logic circuit 11
In step 6, the logical product of the signals 120 and 122 output from the comparison circuits 113 and 115 is obtained, and the result is output to the selection circuit 112. In the selection circuit 112, when it means that the selection signal 125 satisfies both the condition A and the condition B,
The branch address 124 is selected. The branch address 124 is a head address of an area in the instruction memory in which the execution program of the process 1 is set in advance. Instruction pointer 11
1 is rewritten to this start address, and processing 1 is executed (conditional branch satisfied). On the other hand, when the selection signal 125 indicates that at least one of the condition A and the condition B is not satisfied, an address in which the value of the instruction pointer 111 is incremented by one is selected. At this time, if the execution program of the process 2 is set from the instruction next to the conditional branch instruction, the process 2 is executed (the conditional branch is not taken). Thus, in the case of the conditional branch instruction shown in FIG.
If both the condition and the condition B are satisfied, the process 1 is executed, and if at least one of the conditions is not satisfied, the process 2 is executed.

Next, consider the case of executing a conditional branch instruction represented by a processing flow as shown in FIG. This means that the process 1 is executed when either the condition A or the condition is satisfied, and the process 2 is executed when both the condition A and the condition B are not satisfied. In this case, a logical sum of the condition A and the condition B is obtained in the logic circuit 116 by the signal 123 indicating the mutual relationship between the condition A and the condition B. This allows
When either the condition A or the condition B is satisfied, the conditional branch is established, and the process 1 is executed. In other cases, the processing 2 is executed when the conditional branch is not satisfied.

Further, in the case as shown in FIG. 5 (a), only the condition A is related to the conditional branch and is not related to the condition B. Therefore, the signal 123 may be made to represent only the condition A.
In the case of this instruction, if the condition A is satisfied, the conditional branch is taken, and the process 1 is executed. Otherwise, the process 2 is executed with the conditional branch not taken.

Similarly, in the case of FIG.
By expressing only the above, the process 1 is executed when the condition B is satisfied, and the process 2 is executed otherwise.

Thus, in this parallel operation device, a plurality of operation units 10
A plurality of operations according to a plurality of conditional branch instructions can be executed simultaneously and parallelly by 1 to 102. Further, the comparison circuits 113 to 115 and the logic circuit 116 can determine at once whether a plurality of branch conditions are satisfied.
As a result, it is possible to quickly select the address where the instruction following the conditional branch instruction is set.

The operation between the flag registers is not limited to the logical product and the logical sum, but may be various other logical operations.

[Effects of the Invention] As described above, according to the parallel operation device of the present invention, the comparison circuit corresponding to each of the plurality of operation units and the logic circuit that performs the logical operation according to the relationship between the plurality of conditional branch instructions are provided. Provided. Therefore, a plurality of conditional branch instructions can be executed simultaneously in parallel, and it can be instantaneously determined whether or not the condition is satisfied. As a result, even in the execution of a program including a large number of conditional branches, it is possible to perform the conditional branch operation without lowering the processing capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment relating to a parallel operation device of the present invention, FIG. 2 is a block diagram showing details of a logic circuit shown in FIG. 1, and FIGS. FIG. 6 is a block diagram showing a configuration of a conventional parallel operation device, and FIGS. 7 and 8 are diagrams for explaining a conventional parallel operation device. It is a conceptual diagram of a processing flow and an instruction memory. 101-102 arithmetic unit 103-105 flag register 113-115 comparison circuit 116 logic circuit 111 instruction pointer 112 selection circuit

Claims (1)

(57) [Claims] A plurality of operation means for simultaneously executing a plurality of operations in accordance with a plurality of conditional branch instructions in parallel; and an operation result provided by the operation means provided for each of the plurality of operation means. A plurality of comparing means for comparing a branch condition of the conditional branch instruction and determining whether an operation result satisfies the branch condition; and a plurality of comparison results obtained by the plurality of comparing means, Logic operation means for performing a logical operation in accordance with the relationship between the plurality of conditional branch instructions provided simultaneously with the comparison result of the above, and performing the operation after the plurality of conditional branch instructions in accordance with the operation result obtained by the logical operation means Selecting means for selecting an address in which a power instruction is set.