JP2785280B2 - Fuzzy inference device and information processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuzzy inference apparatus connected to a microcomputer and an information processing apparatus in which the microcomputer is connected to a fuzzy inference apparatus.

<Prior Art> Conventionally, there are a fuzzy computer that performs fuzzy inference using a digital computer and a fuzzy computer that performs fuzzy inference using an analog circuit. The former has a low inference speed,
The latter has the disadvantage of lacking versatility.

<Problems to be Solved by the Invention> An object of the present invention is to provide a fuzzy inference apparatus and an information processing apparatus which have a high inference speed of fuzzy inference and are highly versatile.

<Means for Solving the Problems> First Solution: A fuzzy inference device configured to be connected to a microcomputer via a digital bus, wherein a storage unit for storing a fuzzy rule and a membership function; When a micro computer is accessed by a predetermined address via the storage unit, a selection unit that selects a group of fuzzy rules corresponding to the address from the storage unit, and a fuzzy rule group selected by the selection unit and a membership function stored in the storage unit are selected. A fuzzy inference unit for executing a fuzzy inference by using the fuzzy inference unit, and an interface unit for returning the definite value generated by the fuzzy inference unit to the microcomputer via the digital bus. Features.

Second solution means: an information processing device comprising the fuzzy inference device of the first solution means and a microcomputer.

<Operation> The operation of the first solving means is as follows. That is, when the micro computer accesses the interface section at a predetermined address, the selecting means selects a fuzzy rule group corresponding to the address from the storage section, and the fuzzy inference section stores the fuzzy rule group and the filing rule selected by the selecting means. A fuzzy inference is performed using the membership function to generate a definite value, and the definite value generated in the fuzzy inference unit is returned to the microcomputer via a digital bus.

The operation of the second solving means is as follows. That is, an information processing apparatus is constituted by the first solving means and the microcomputer.

<Effect> According to the first solving means, the fuzzy rule used for the fuzzy inference can be switched by changing the address given to the fuzzy inference device from the microcomputer, and an appropriate inference result according to the situation can be obtained. . Moreover, transmission of the switching command of the fuzzy rule group,
The three processes of starting the fuzzy inference and reading the result of the fuzzy inference can be executed by one instruction of accessing a specific address from the micro computer. Therefore, the hardware of the interface is simplified, and the program of the microcomputer using the fuzzy inference device is also simplified.

According to the second solution, the hardware configuration of the information processing apparatus can be simplified, or the hardware configuration can be simplified and the inference result can be made appropriate.

<Example> An example is described below with reference to the drawings. FIG. 1 is a system configuration diagram of the present embodiment apparatus. In this system, a fuzzy computer (hereinafter, abbreviated as FC, if necessary) 2, 3, 4, 5, which will be described in detail later, is arranged under the top 1 mainly composed of a micro digital computer, a so-called micro computer. Controlled. Then, for example, with respect to the first fuzzy computer 2,
Is characterized in that it has a multi-layered structure such as the connection of the fuzzy computer 3. Note that this system can be configured by separating the top 1 and the fuzzy inference device consisting of FC2, 3, 4, 5 and as an information processing device consisting of top 1 and FC2, 3, 4, 5 You can also.

That is, FC2 has a structure in which, in addition to the inference based on the outputs from the plurality of sensors 6, 6,.

Here, the reasoning executed by the present system will be briefly described based on the processing schematic diagram of FIG. 2 in order to facilitate understanding later. Suppose that the execution of inference regarding a certain proposition from the top 1 is instructed to the top FCa. This command will require a differential output. In response to this command, FCa activates FCb to c when the information necessary for inferring this proposition is obtained in lower order FCb to c. In response to this activation, FCa to c execute inference based on the outputs of the separately arranged sensors 6, 6 and transmit the result to FCa. FCa receives the result, executes the inference, and transmits the result to the top one. The final inference result obtained in this way is displayed on the display unit in the top 1 or output as a control signal to another system.

As described above, it is advantageous to analyze and infer a large and complex problem if the upper FC can treat the inference result obtained by the lower FC in the same manner as the sensor output.

In addition, a portion enclosed by a dotted line in FIG. 2 will be additionally described. In other words, the lower FCc executes inference according to the sensor output and transmits the result to the upper FCa, but the signal form is formed equivalent to the signal form that the sensors 6 and 6 input to themselves. ing. Therefore, the top FCa
From the viewpoint, it is not possible to distinguish whether it is the direct output from the sensor 6 or the inference result, or it is not necessary to distinguish. This means that the whole portion 7 surrounded by the dotted line forms a certain sensor, that is, a fuzzy sensor.

Next, the relationship between the fuzzy computer and the upper (hereinafter referred to as MPU) 1 will be described with reference to FIG. The FC2 typically shown in FIG. 3 is connected to the MPU 1 by the upper bus 8. The MPU 1 previously stores the fuzzy production rules in the fuzzy rule memory 9 via the bus 8.

When executing a certain proposition, the MPU 1 transfers information indicating the proposition to the rule controller 10 via the bus 8. As a result, the rule controller 10 selects a rule to be activated and sets it in the fuzzy rule register section 11 from the fuzzy rule memory 9.

The rule set in the fuzzy rule register section 11 determines whether the input control section 12 should take in an external input as a fuzzy variable or a fuzzy conclusion memory section 13 to be described later. The fuzzy variables selected based on this judgment are added to the fuzzy inference unit together with the rules.
And the inference is performed. The inferred result is stored in the fuzzy conclusion memory unit 13. This inference result is transferred to the MPU 1 via the conclusion memory controller 15 and the upper bus 8.

That is, the MPU 1 can freely access the fuzzy rule memory 9, the rule controller 10, and the conclusion memory controller 15, thereby executing and completing a desired inference.

Next, the specific configuration and operation of the fuzzy computer shown in FIG. 3 will be described.

Therefore, returning to FIG. 2, the inference operation in the present system will be described. FC for MPU1 to make inferences about Z1
Transfer this to a. That is, the MPU 1 issues a request for the differential output Z1. This is the FCa production rule “ifx1 = A1 · y1 = B1 then z1
= C1 ”(ie, if“ x1 is A1 and y1 is B1, then z1 is
Suppose that it is expanded into the if-then format of C1 ").

In response to this, FCa searches for where the x1 or y1 which is the fuzzy variable in the antecedent of the rule is obtained. The details of this search will be described later, but in short,
When it is obtained as a definite value from the sensor 6, it is the same as a conventional fuzzy computer. However, when it is obtained as an inference result of another FC, all rules with x1 or y1 as a consequent in the above example Is executed in a specific FC, and the overall inference result obtained from the
b or transmitted from FCc to FCa.

In FIG. 2, a two-layer structure such as FCa and FCb or FCc has been described, but the present invention is not limited to this. In other words, if the antecedent part of the rule executed by the FC located at a certain level includes a fuzzy variable that is not a sensor output, the FC that outputs the fuzzy variable (ie, the lower FC) is sequentially activated. There is a feature of this system in the point.

The fuzzy rule memory 9 stores a plurality of if-then fuzzy production rules. As shown in detail in FIG. 4, each rule is composed of an antecedent part 16 and a consequent part 17. The fuzzy production rules (hereinafter also referred to as fuzzy rules) are written in the fuzzy rule memory 9 by the MPU 1 in advance.

Further, the MPU 1 previously writes data for determining a fuzzy rule to be started in the rule controller 10, and details thereof are shown in FIG.

In FIG. 5, the stad of the rule control memory 18 is shown.
dr (i) and endaddr (i) are used to indicate which address in the rule memory 9 has a rule that makes the same fuzzy variable in the consequent part the head address.
staddr (i), and the final address is indicated by endaddr (i).

FIG. 6 shows the relationship between the rule memory 9 and the rule control memory 18 on the memory.

As described above, the MPU 1 writes the fuzzy rule and the rule control data to all FCs, so that the present system is initialized to a state where inference can be performed.

Accordingly, the MPU 1 instructs inference disclosure of a predetermined item. This instruction is given to the conclusion memory controller 15 in FIG. Conclusion memory controller
The details of No. 15 are shown in FIG. Also, the fuzzy conclusion memory unit 13
8 is shown in FIG. 8, and the details of the fuzzy conclusion memory are shown in FIG.

Now, the MPU 1 applies an address signal i to the conclusion memory controller 15 via the upper bus 8 in order to infer an event r. This address signal is sent to the command register
Set to 21 (FIG. 7). In response, the conclusion memory access unit 22 supplies the address signal ead and
The corresponding fuzzy variable value edat from interface 22
Read via 3.

The fuzzy conclusion memory 20 is a memory for storing the inference result as shown in detail in FIG. 9, and the fuzzy inference unit 14 in FIG.
As the inference is completed, the inference result, which is the fuzzy variable value, is set in the conclusion part 23, and "1" is set in the flag part 24 located at the highest position. Therefore, if "1" is not set in the flag section 24, it means that the corresponding fuzzy variable is not valid.

Therefore, if the most significant bit of the data edat read from the conclusion memory 20 is “1”, this data is validated,
Conclusion This is set in the memory data register 25 (FIG. 7).

If the most significant bit of the read data edat is "0", the rule activation request signal erul is sent to the fuzzy variable address.
Along with faddr, it is applied to the rule control memory accessor 26 of the rule controller 10 (FIG. 5).

Accordingly, the rule controller 10 generates a rule group having a fuzzy variable address faddr in the consequent part (this is now called i
Is detected by reading the rule control memory 18. Now this is i, so the start address staddr of the i-th rule group sharing the consequent part
(I) and the end address (endaddr (i)) are set in buffer registers 27 and 28, respectively.

The buffer register 27 also has a counter function,
The output of the register 27 is stored in the fuzzy rule memory 9 (FIG. 3,
This signal is applied to the rule memory 9 as a signal (ruladdr) for making a read access to the corresponding rule in FIG. 6). As a result, inference is performed. When the inference for one rule in the rule group is completed, a count-off signal is output from the synchronization circuit 29, the counter buffer 27 is incremented, and the output (ruladdr) is used to infer the next rule. Be started. When the execution of all the rules in the rule group is completed in this way, the counter buffer 27
Comparator for comparing the output of the buffer with the final address buffer 28
The output is output from 30 and the running stops. As a result, the inference of all the rules in the rule group having a common consequent part is completed.

Next, how the repetitive inference is performed will be described.

The aforementioned rule address signal, ruladdr, is applied to the fuzzy rule memory 9 (FIG. 3), and the corresponding rule is read out to the fuzzy rule register section 11.

 The details of the fuzzy rule register section 11 are shown in FIG.

It is now assumed that the rule read by the rule address signal ruladdr is as shown in the following equation (1).

if x = A · y = B · z = C then r = D (1) In this equation (1), x, y, z, and r are fuzzy variables, and as will be described later, It takes the form of an address signal.

Equation (1) read from the rule memory 9
Are stored in the latch circuits 31 to 38 (FIG. 10) of the fuzzy rule register section 11 for each variable.

The address on the latch circuit 31 is used as a write address for the fuzzy conclusion memory 20 (FIG. 8) via the write interface unit 22. The addresses on the latch circuits x, y, and z are time-sequentially converted by a fuzzy variable read control unit 39, and the input control unit 12 shown in FIG.
(See FIG. 3).

The signal related to the antecedent part of the rule given to the input control unit 12 in this manner is decoded by the pair of decoders 40 and 41. That is, assuming that rad and rcode relating to the first fuzzy variable x are given, the register code rcode is decoded by the decoder 41 and the input latch 44 is selected. The read address rad is decoded by a decoder, and it is determined whether the read address rad is information obtained from its own, that is, information obtained from the fuzzy conclusion memory 20, or information obtained from the outside, that is, information obtained from a sensor or a lower FC. Either the external input interface 45 or the fuzzy conclusion memory interface 46 is selected according to the determination result, and the fuzzy variable x
Is output.

That is, depending on whether the predetermined bit of rad is "0" or "1", either the fuzzy conclusion memory interface 46 or the external input interface 45 is selected. Conclusion When the memory interface 46 is selected, the address signal fmad for the fuzzy variable x is set to the conclusion memory interface.
Output from 46, the input control interface of FIG.
The fuzzy conclusion memory 20 is accessed via 225 and data is read from the fuzzy conclusion memory 20. The read data is output as a signal fdat via an input control unit interface 225 as a fuzzy conclusion memory interface.
Entered in 46.

On the other hand, when the external input interface 45 is selected, the external input interface 45 outputs the selection signal sensad of the sensor 6 or the lower FC. The selected sensor or FC signals status signal or fuzzy inference result sdat
Is returned to the external input interface 45.

The data input to the memory interface 46 or returned to the external input interface 45 is set on the input latch 42 as dx via line 47. The same process is performed for y and z, and the fuzzy variable values dy and dz are set in the input latches 43 and 44.

Next, inference is performed using the fuzzy variable values dx, dy, dz and another signal, a membership function. A mechanism for generating the membership function will be described.

Returning to FIG. 10, the labels A, B, C, and D of the membership rules of the fuzzy rule are latch circuits 35, 36, and 3, respectively.
As described above, the information is latched at 7,38. The labels A, B, C, and D thus latched are input to the waveform creation unit 50 as a part of the address. And
A signal indicating a time-dependent membership function is output from the waveform creation unit 50, which will be described below.

This waveform generation unit 50 generates a fuzzy membership function as described above. Normally, as shown in FIG. 12, this membership function is represented by a continuous function with the horizontal axis taking the fuzzy variable and the vertical axis taking the degree of membership. On the other hand, in this fuzzy computer, when generating the membership function, the fuzzy variable x is discretely taken as shown in FIG. (Pulse width). This is hereinafter referred to as PWM (Pulse Width Modulation) expression of the membership function. Here, the end points of the pulses are set at the same time, but the starting points may be set at the same time.

Based on the above understanding, the waveform creation unit 50 shown in detail in FIG. 14 will be described.

The waveform creation unit 50 stores function waveforms of a plurality of types of membership functions, and selects a corresponding function based on a label (A, B, C, D,...) Which is one of the inputs. 53 and 54, and a counter 55 for controlling the read timing of the selected function.

That is, in the waveform memories 51 to 54, referring to FIG. 13, "0" and "1" are assigned to each lattice, and a plurality of PWM-expressed membership functions are stored in the order of labels. Accordingly, when the membership function is designated by the label and the count value obtained by counting the clock is applied from the counter 55, the waveform memory 51 and the like are accessed in the order of t0, t1, t2,... Shown in FIG. Then, as shown in FIG. 15, a membership function expressed by the length of the pulse length is output on lines h0, h1, h2,.

In this way, the fuzzy inference is executed by aligning the fuzzy variable values dx, dy, dz and the membership functions (mA, mB, mC, mD). This is shown in FIG. A description will be given based on the block diagram of FIG.

In the fuzzy inference unit 14, the antecedent of the fuzzy rule is processed. That is, the input membership function (mA, mA, PWM) expressed on a plurality of lines h0, h1, h2.
mB, mC) are connected to multiplexers 61, 62, 63, respectively.

The functions of the multiplexers 61, 62 and 63 are
One of the lines h0, h1, h2,... is selected according to the size of dx, dy, dz, and the degree of belonging ex, ey, ez is output.
This is equivalent to evaluating the input signal input from a sensor or the like with a membership function and outputting a belonging value in a known or ordinary fuzzy computer. Just
The difference is that a normal fuzzy computer is characterized in that the belonging value is represented by the magnitude of an electric signal such as a voltage or a current, whereas the present fuzzy computer is characterized by a pulse length.

The affiliation values ex, ey and ez expressed in the pulse width in this way are
The MIN operation is performed in the min circuit 64. The actual state of the min circuit 64 is a simple AND circuit shown in FIG. That is, in this fuzzy computer, the degree of affiliation ex, ey, ez is PW
Since it is expressed in M, a pulse (affiliation) having the shortest pulse width is easily selected by an AND circuit, MIN operation is performed, and an output g is output.

When the processing of the antecedent part is completed in this way, the process proceeds to the processing of the consequent part. Processing of the consequent part is the truncation part 65
Made in.

That is, the truncation unit 65 is composed of a group of AND circuits arranged in parallel as shown in FIG. 18, and one input terminal of each AND circuit is commonly connected to the output terminal of the min circuit 64, The output g, which is the pulse width signal of

The other input of the truncation section 65 is a membership function mD2 of the consequent part, and this function mD is expressed by a plurality of lines h0, h1, h2... By applying such pulse signals (g and mD), the truncation section 65 selects one of the two signals having a shorter pulse width and outputs the output mD '. This output mD 'is represented by n lines corresponding to mD. Such a process is equivalent to a process called “head truncation” in a normal fuzzy computer.

When the processing of the antecedent part and the processing of the consequent part are completed in this way, one processing is completed. Accordingly, the fuzzy computer transitions to processing the next rule. In this way, rules are executed one after another, and finally inference is completed. Next, synthesis of execution results of each rule will be described.

As described above, when the execution of the first rule is completed, the execution result mD 'is initially shifted to the reset state via the C-max circuit 66 and the bus 67 composed of n lines. The data is read into the register group 68. The shift register group 68 is composed of n sets of shift registers provided for each line, and stores the above-described PWM-expressed pulse width signal in a reproducible manner.

The C-max circuit 66, as shown in FIG.
N sets of input OR circuits are arranged in parallel corresponding to the number of lines. Therefore, after execution of the first rule, each pulse signal of the output mD 'is stored in the shift register group 68 as it is.

When the execution of the second rule is completed, the output mD ′ becomes C
The execution result according to the first rule is reproduced and applied from the shift register group 68 in synchronization with the timing applied to the -max circuit 66, and the pulse width of the longer pulse width is increased every n lines by the operation of the OR circuit. The signal is selected and stored in the shift register group 68 as before. Such an operation is performed by a so-called “MA” in a known and ordinary fuzzy computer.
X operation ".

In this way, at the end of each rule execution, the combined result of the rules executed so far is stored in the shift register group 68 in the form of a PWM expression. After the execution of the final rule, the final inference result is stored in the shift register group 68 in a reproducible form in PWM expression.

Next, a description will be given of a so-called “define-file” process for converting the inference result obtained as described above into definite value information.

FIG. 20 shows details of the differential adhesive 69 for performing the differential treatment. The operation of the differential door 69 is shown in the flowchart of FIG.

When the execution of all the rules is completed, the execution results stored in the shift register group 68 (FIG. 16) are transmitted via the bus 67 to the n shift registers 70 of the differential register.
The data is read for each line from 0 to 70n-1. As a result, in each of these shift registers 70, the execution result represented by PWM is stored in a transcribed form. This storage state is schematically shown in FIG.

These shift registers 70 read data in the serial mode as described above, and output parallel signals as outputs, and the parallel signals are used to execute the PWM-expressed execution results; that is, only in FIG. 22. For example, the height of the waveform 73 is output.

In this fuzzy computer, the waveform shown in FIG.
The point 73 (or line) which divides the area on the left and right into two equal parts is defined as a definite value. Then, the outline of the differential processing will be outlined beforehand. In FIG. 22, the waveform height is added (integrated) in the a direction from the left, and the left partial area of the waveform is sequentially obtained. Similarly, the right partial area of the waveform is calculated from the right in the direction b. Then, the respective partial areas are compared to detect whether or not they match. If they do not match, the addition is performed for the smaller one, and the comparison is performed on the result of the addition. By repeating the addition (integration) and comparison in this way, a differential output 74 is finally obtained.

Now, first, the left and right counters 75 and 76 are “0” and “n”.
-1 ", and the leftmost shift register 700 and the rightmost shift register 70n-1 are designated (addressed). With this, the accumulator 77,78
Is reset. As a result, the leftmost shift register 700 is addressed via the read controller 71, and its data f (0) is output to the data bus 79. This output data is added to the contents of the accumulator 77,
The result is stored in the accumulator 77.

Next, the rightmost shift register 70n-1 is addressed via the read controller 72, and its data f (n-
1) is output to the data bus 79. The output data is added to the contents of the accumulator 78, and the result is stored in the accumulator 78.

Then, the comparator 300 compares the value 1 of the accumulator 77 with the value r of the accumulator 78. The comparator 300 drives the accumulation controller 301 when 1 ≦ r, and
If> r, the accumulation controller 302 is driven. When driven, the accumulation controllers 301 and 302 respectively operate the up counter 75 and the down counter 7.
6 is given an enable signal.

When the up counter 75 receives the enable signal,
The read controller 71 is driven by adding “1” to the stored value a. The read controller 71 specifies a shift register corresponding to the value a of the up counter 75. The data of the designated shift register is added to the accumulator 77.

Upon receiving the enable signal, the down counter 76
The read controller 72 is driven by subtracting “1” from the stored value b. The read controller 72 has a down counter 76
Is specified for the shift register corresponding to the value b. The data of the designated shift register is added to the accumulator 78.

Hereinafter, in the same manner, the acquisition controller 30
One of a set of 1, a counter 75, a read controller 71, and an accumulator 77, or a set of an accumulation controller 302, a counter 76, a read controller 72, and an accumulator 78 is selected and driven by the comparator 300. .

By repeating the above operation, the comparator 303 receiving the outputs of the counters 75 and 76 makes the value of the counter 75
Is detected, the gate 305 is opened. When the gate 305 is opened, the data stored in the counter 76 is output as the fixed value dr. When the gate 305 is opened, the accumulated value of the accumulator 77 and the accumulated value of the accumulator 78 are approximately equal within the range of the error.

The definite value, that is, the conclusion value dr of the inference is obtained via the write interface unit 224 in FIG.
Store to 0. At this time, the address given from the MPU 1 and stored in the r latch circuit 31 is used.

The determined value stored in the fuzzy conclusion memory 20 is read out from the fuzzy conclusion memory 20 to the conclusion data register 251 via the conclusion memory data register 25 and used when the same request for the differential output is subsequently made (23rd time). See figure). Alternatively, when the value stored in the fuzzy conclusion memory 20 appears as a variable in the antecedent part of the subsequent inference,
The value is used to make inferences about the antecedent part (No. 24).
Figure).

[Brief description of the drawings]

FIG. 1 is a system configuration diagram for multi-stage fuzzy inference, and FIG. 2 is a schematic diagram of an example of an inference process.
FIG. 3 is a block diagram of a fuzzy computer, and FIG. 4 is a memory map showing a fuzzy rule memory.
The figure is a block diagram of the rule controller, and FIG. 6 is a diagram showing the relationship between the rule memory and the rule memory on the memory. FIG. 7 is a block diagram of the conclusion memory controller, FIG. 8 is a block diagram of the fuzzy conclusion memory section, and FIG. 9 is a memory map showing the structure of the fuzzy conclusion memory. FIG. 10 is a block diagram of the fuzzy rule register unit, and FIG. 11 is a block diagram of the input control unit. Fig. 12 shows the membership function.
The figure shows the membership function decomposed for each line.
FIG. 14 is a block diagram of the waveform creation unit, and FIG. 15 is a waveform diagram of the membership function. FIG. 16 is a block diagram of the fuzzy inference unit, and FIG. 17 is a block diagram of the MIN circuit.
Fig. 19 is a block diagram of the truncation section. Fig. 19 is a block diagram of the Correspondence-Mux circuit (C-MAX circuit).
FIG. 20 is a block diagram of the differential adhesive, FIG. 21 is a flowchart showing the processing of the differential adhesive, and FIG. 22 is a schematic diagram showing the inference result. FIG. 23 is a diagram showing an example in which the same inference is performed as in the past, and FIG. 24 is a diagram showing an example in which the past result is used for inference of the antecedent part. (A) in Fig. 23 and Fig. 24 show past inferences, and (b)
Shows this inference. 1: MPU, 2 to 5: Fujii computer, 6: Sensor, 9: Fujii rule memory, 10: Rule controller, 13: Fujii conclusion memory unit, 14: Fujii inference unit, 15: Conclusion memory controller

Claims (2)

(57) [Claims] 1. A fuzzy inference device configured to be coupled to a microcomputer via a digital bus, comprising: a storage unit for storing a fuzzy rule and a membership function; and a microcomputer according to a predetermined address via the digital bus. When the access is received from the storage unit, the selection unit for selecting the group of fuzzy rules corresponding to the address from the storage unit, and the fuzzy inference is executed using the group of fuzzy rules selected by the selection unit and the membership function stored in the storage unit to be determined. A fuzzy inference apparatus comprising: a fuzzy inference unit for generating a value; and an interface unit for returning a definite value generated by the fuzzy inference unit to the microcomputer via the digital bus. 2. An information processing apparatus comprising the fuzzy inference apparatus according to claim 1 and a micro computer.