JP2776707B2 - Cell flow monitoring circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell flow monitoring circuit in a switching / transmission system, and more particularly, to a switching / transmission system using an asynchronous transfer mode (ATM). .

[0002]

2. Description of the Related Art In an ATM switching / transmission system, information is transferred by fixed-length / short packets called cells, and the logical information transfer speed is defined by the number of cells transmitted per predetermined time for all phases. The network user makes a traffic contract with the network operator and can freely transmit information as long as the number of cells transmitted per prescribed time T according to the contract is within the maximum number X of cells allowed by the contract. . Such a traffic contract is made using both the time stipulated value T and the allowable maximum number of cells X as parameters, and differs for each network user (channel).

However, the physical interface speed installed between the network user and the network operator usually has a speed higher than the traffic contract speed (X / T). It is possible to send a cell flow over the contract to the network. For this reason, in the ATM switching and transmission system, the network operator monitors the cell flow transmitted by the network user, determines whether the cell flow violates the traffic contract, and violates the contract. In such a case, in order to protect network resources, measures such as discarding illegal cells that violate the contract are taken.

Conventionally, a cell flow monitoring circuit that monitors a cell flow to determine whether the cell flow complies with a traffic contract and controls the cell flow in accordance with the result of the determination is disclosed in the following document. There are things to be done.

Literature, "Michio Kusanagi, Hiroshi Takeo, Takao Ogura, Kazuo Iguchi, Kazuo Yamaguchi," A Method for Implementing Policing Function in ATM Subscriber Circuits ", Proc. -247] FIG. 2 shows a cell flow rate monitoring circuit described in this document.
With reference to FIG. 2, a conventional cell flow rate monitoring circuit described in the above document will be described. FIG. 2 shows a case where the number of channels handled is four.

This conventional cell flow rate monitoring circuit also controls whether or not the number of cells arriving within the specified time value T exceeds the allowable maximum cell number X. However, the conventional cell flow rate monitoring circuit counts the number of cells arriving within the time stipulated value T and determines whether the number of cells arriving within the time stipulated value T exceeds the allowable maximum cell number X. not,
It is determined whether the number of cells arriving within the time stipulated value T exceeds the allowable maximum cell number X, and (X
Focusing on the fact that it is equivalent to determining whether or not a previous cell of the same channel has arrived within the specified time value T, and performing the violation determination using the latter determination method And

In FIG. 2, the conventional cell flow monitoring circuit comprises a bridge memory 21, a cell counter 22, an X pointer 23, an N pointer 24, a current time counter 25, and a violation determination circuit 26.

[0008] Cell arriving (cell targeted for violation determination processing)
From a header extraction circuit (not shown), only the channel number of the header portion is extracted, and the extracted channel number CH
j (j specifies the channel of the arrival cell and is 1
To 4) are given to the bridge memory 21 and the cell counter 22.

The bridge memory 21 is a memory having a size corresponding to the maximum value Tmax of the time stipulated value T for which a traffic contract can be made, and stores the channel number information of the arriving cell and the cell having the same channel number arriving next. Pointer information to an area in the bridge memory 21 in which the channel number information is stored, as a pair, and
It operates as a kind of first-in first-out memory (FIFO memory) that delays by a period corresponding to the maximum value Tmax of the time stipulated value T that can be contracted for traffic.

The architectural bridge limits the total weight of arriving persons and vehicles to a predetermined weight, which is similar to the function of this memory 21 and is therefore not described in the art. The memory 21 is called a bridge memory.

The current time counter 25 is a counter that increments by one when one cell time slot elapses. The count value of the current time counter 25 is used to record the cell arrival time in the N pointer 24, and is used as a pointer indicating a position for writing the information of the arrival cell in the bridge memory 21.

The cell counter 22 comprises a plurality of counters CC1 to CC4 corresponding to the number of channels (four channels in FIG. 2) handled by the cell flow monitoring circuit.
Each time a cell arrives, the counter CCj corresponding to the channel number CHj of the arriving cell is incremented by one. Each time cell information is discharged from the bridge memory 21, the discharged channel number CHm (m is The counter CCm corresponding to any one of 1 to 4 which defines the channel of the discharge cell is decremented by one. As a result, the cell counter 22 reads the bridge memory 2
1, each channel number CHi (i is 1 to
4) indicates the number of cells.

X pointer (including a configuration for updating a value) 23
Are calculated from the latest arrival cell for each channel number CHi (Xi
-1) A pointer indicating the position in the bridge memory 21 of the cell arriving immediately before, and a plurality of pointers Xp1 corresponding to the number of channels handled by this cell flow monitoring circuit,
.., Xp4.

Xi represents the maximum allowable number of cells per the prescribed time value Ti contracted for the channel number CHi.

For example, when a cell arrives, the X pointer 23 first determines a count value CCj (before updating) corresponding to the channel number CHj of the arriving cell of the cell counter 22, a maximum allowable cell number Xj -1 in the traffic contract, and the like. Compare. Then, the count value CCj of the cell counter 22 is calculated.
Is smaller, no processing is performed on the channel number CHj. On the other hand, if the cell count value CCj is equal to or greater than the allowable maximum cell number Xj-1, the X pointer Xp
From the address of the bridge memory 21 indicated by j, pointer information indicating the position of the cell that has arrived next (arriving (Xi -1) cells before this arrival cell) is read, and the pointer value read from the bridge memory 21 is read. Is newly set to the X pointer Xpj.

The value of the X pointer Xpm is controlled to be updated for the channel number CHm of the cell discharged from the bridge memory 21 upon arrival at this time in a manner similar to that described above.

As described above, each X pointer Xpi always indicates the position of the cell arriving before (Xi -1) when information on Xi or more cells is stored in the bridge memory 21. Become like

N pointer (including a configuration for updating a value) 24
Is a pointer indicating the position in the bridge memory 21 of the information of the cell arriving immediately before for each channel, and is composed of a plurality of pointers Np1 to Np4 corresponding to the number of channels handled by the cell flow monitoring circuit. When a cell arrives, the value of the current time counter 25 is written in the pointer information section of the address of the bridge memory 21 indicated by the pointer Npj corresponding to the channel number CHj of the arriving cell in the N pointer 24.

The violation judging circuit 26 first compares the value of the cell counter CCj corresponding to the channel number CHj of the arriving cell with the allowable maximum cell number Xj-1 according to the traffic contract. If the value of the cell counter CCj is less than the maximum number Xj-1 of cells allowed by the traffic contract, a signal indicating that the traffic contract is not violated is output to, for example, a discard control circuit (not shown). That is, for the channel number CHj of the arriving cell, (Xj−
1) Since the preceding cell arrives at least before the maximum time Tmax (≧ Tj) during which the traffic contract can be made, the traffic contract is not violated.

If the value of the cell counter CCj corresponding to the channel number CHj of the arriving cell is equal to or greater than the allowable maximum number of cells Xj -1 according to the traffic contract, the current time value output from the current time counter 25 and the X pointer Xpj The difference value is calculated, and the calculated difference value is compared with the specified time value Tj in the traffic contract. If the difference value is equal to or greater than Tj, it is determined that no violation has occurred. A signal indicating non-violation is output to, for example, a discard control circuit (not shown). That is, based on the value of the current time counter 25 and the value of the X pointer Xpj, the contracted allowable maximum cell number Xj
The time required for the arrival of the cells (the above-described difference value) is obtained and compared with the specified time value Tj to determine the traffic contract violation with respect to the cell flow rate.

As described above, the conventional cell flow monitoring circuit uses the same channel C (Xj -1) prior to the current arrival.
The determination principle is to determine whether the cell of Hj has arrived within the specified time value Tj, and the processing of various pointers and counters is performed by the channel number CHj of the arriving cell and the data discharged from the bridge memory 21. The processing is only for the two types of channels with the channel number CHm of the cell,
Since this cell flow rate monitoring circuit does not depend on the total number of channels handled and the types of parameters Ti and Xi relating to traffic contracts, problems such as the number of accesses to the bridge memory 21 and the like increase with the number of channels and traffic contract types. It did not occur.

[0022]

However, in practice, in an ATM switching / transmission system, multiplexing processing or the like may be performed in units of cells upstream of a point where a cell flow rate monitoring circuit is installed. For example, the multiplexing process is based on the fact that cells of a plurality of channels are temporarily stored in a buffer memory, then taken out and multiplexed, and the delay time from when a certain cell is stored in the buffer memory until it is read out is not constant. That is, the cell flow transmitted by the network user may fluctuate (cell delay fluctuation: CDV) through multiplexing processing and the like, and the cell transmission pattern may change. In some cases, the cell flow affected by the above may arrive at the cell flow monitoring circuit.

As described above, the conventional cell flow rate monitoring circuit does not consider cell delay fluctuation due to cell multiplexing or the like.
For this reason, there has been a problem that the network user may determine that the contract is breached even though the cell is transmitted in compliance with the traffic contract.

In order to solve such inconvenience, a parameter margin for compensating for cell delay fluctuation is set for the values of the traffic contract parameters Ti and Xi, and a contract parameter having a margin is applied. It is also conceivable to operate the cell flow rate monitoring circuit of FIG. However, in this case, a part of the cell flow more than the traffic contract is allowed, and a new problem that the network resources cannot be effectively used arises.

The present invention has been made in consideration of the above points, and it is possible to appropriately determine whether or not a cell flow violates a traffic contract even if cell delay fluctuation occurs through cell multiplexing processing or the like. It is intended to provide a cell flow monitoring circuit.

[0026]

In order to solve such a problem, the present invention provides a method for determining whether or not an actual cell flow violates a traffic contract defined by a maximum number X of cells that can be allowed per time T. A cell flow monitoring circuit that constantly monitors and controls using a prescribed cell delay fluctuation tolerance,
It was configured to have the following means.

That is, the cell arrival history information holding means for holding the cell arrival history information, and the cell to be processed which is determined to be a violation at the present time is determined by using the contents held by the cell arrival history information holding means. From the time required for the X-th cell to arrive, the cell to be processed is (X-1)
An arrival time interval calculating means for obtaining an arrival time interval obtained by subtracting a time offset value associated with a cell which has arrived immediately before; and an arrival time interval obtained by the arrival time interval calculating means, which is a cell delay fluctuation tolerance from time T. Violation determining means for determining a violation only when the value is smaller than
When the arrival time interval obtained by the arrival time interval calculation means is less than the time T and is equal to or greater than a value obtained by subtracting the allowable value of the cell delay fluctuation from the time T, a value obtained by subtracting the arrival time interval from the time T is calculated. And a time offset calculating means for storing the time offset value associated with the processing target cell in the cell arrival history information holding means.

[0028]

In the present invention, the cell arrival history information holding means holds the cell arrival history information, and the arrival time interval calculation means uses the contents held by the cell arrival history information holding means to make a violation at the present time. The time offset associated with the cell arriving (X-1) cells before the cell to be processed, from the time required for the X cells to arrive at the X-th cell to be processed to be determined Find the arrival time interval with the value subtracted. Then, the violation determining means determines that the violation is present only when the calculated arrival time interval is smaller than the value obtained by subtracting the allowable value of the cell delay fluctuation from the time T. For example, if the number of arriving cells is less than X, it is naturally determined that there is no violation. The time offset calculating means determines the arrival time interval from the time T when the arrival time interval obtained by the arrival time interval calculating means is less than the time T and is equal to or greater than a value obtained by subtracting the allowable value of the cell delay fluctuation from the time T. The reduced value is calculated and held in the cell arrival history information holding means as an offset value associated with the processing target cell.

The present invention is based on the following concept. If the time required for the X cells, the processing target cell of which is the X-th cell, to arrive is shorter than the contract time T, the cell outflow speed is larger than the contract speed (X / T), which is considered to be a breach of the contract. Considering the delay fluctuation of the cell, it cannot be said that the contract is breached. Therefore, the time obtained by subtracting the allowable value of the cell delay fluctuation from the contracted time T is set as the threshold value for the violation determination. However, when the time required for the X cells including the cell to be processed to arrive to arrive is simply compared with the time obtained by subtracting the allowable value of the cell delay fluctuation from the contracted time T, the violation determination is performed. However, in many cases, it is determined that there is no violation in spite of the fact that the violation has occurred. Therefore, the time offset value based on the state of the cell flow at the time of the cell arriving (X-1) cells before the cell to be processed is used for the determination. That is, from the time required for X cells including the processing target cell to arrive, (X−
1) The arrival time interval obtained by subtracting the time offset value associated with the cell arriving immediately before is determined, and the arrival time interval is determined based on the arrival time interval. If the delay fluctuation allowable value is equal to or larger than the value obtained by subtracting the allowable value (that is, if there is a possibility that the contract is actually a breach of the contract), a value obtained by subtracting the arrival time interval from the time T is calculated and the time associated with the processing target cell is calculated. It was decided to be an offset value.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the cell flow monitoring circuit according to the present invention will be described below in detail with reference to the drawings. Here, FIG. 1 shows the configuration of this embodiment.

In FIG. 1, the cell flow monitoring circuit 10 of this embodiment includes a header extraction circuit 11, a delay circuit 12, a discard control circuit 13, a first bridge memory 14, a second bridge memory 15, a control / judgment circuit. 16, a current time counter 17, an arithmetic circuit 18, and a management table 19.

The arriving cell (cell to be processed for violation determination) CEL input to the input terminal is supplied to the delay circuit 12 and the header extraction circuit 11.

The delay circuit 12 is for compensating for a processing delay associated with a process of determining a violation of an arrival cell, which will be described later.
After a certain delay time is given to the arrival cell CEL, it is output to the discard control circuit 13.

The discard control circuit 13 includes a control / judgment circuit 16
In accordance with the instruction of the discard control signal DIS output from the delay circuit 12, the delay arrival cell DCEL output from the delay circuit 12 is discarded or passed.

The header extracting circuit 11 analyzes the header part of the input arrival cell CEL and obtains the channel number CHNO.
And outputs it to the control / judgment circuit 16.

FIG. 3 shows an example of the cell format. The cell of this format example includes channel number information VPI / VCI, cell type PT, priority indication bit CLP, header error control HEC, and information PAYLO.
The header extraction circuit 11 extracts the channel number information VPI / VCI.

The current time counter 17 is a counter that increments by one for each cell time slot, and uses the count value as the current time pointer value Cp to control and determine the circuit 16.
And outputs it to the arithmetic circuit 18.

The management table 19 stores the control / judgment circuit 16
The management information of the channel number specified by the address signal A19 output from the control circuit 20 is transmitted and received to and from the control / determination circuit 16 via the bus B19.

FIG. 4 shows each channel C in the management table 19.
Hi (i is a code for identifying a channel, the same applies hereinafter) and shows an example of management information stored at an address corresponding to Hi. First and second management information
The number of cells CNTi of the channel number whose information is stored in the bridge memories 14 and 15, and the pointer Xpi to the cell arriving immediately before the channel number in the first and second bridge memories 14 and 15. 1 cell is defined as a time specified value T1i obtained by standardizing the time specified value Ti given at the time of traffic contract with one cell time slot time, and a value obtained by subtracting the allowable value of cell delay fluctuation from the time specified value Ti given at the time of traffic contract. A time specification value T2i standardized by the time slot time and a value X1i obtained by subtracting 1 from the maximum allowable cell number Xi according to the traffic contract are stored.

It should be noted that the allowable value of the cell delay fluctuation for determining the specified time value T2i may be fixedly determined according to the number of cell multiplexing configurations upstream of the cell flow rate monitoring circuit 10, and the like. , May be determined by simulation or the like.

The information related to the same channel stored in the management table 19 is to be accessed simultaneously as a whole, but in the description of the processing by the control / judgment circuit 16 to be described later, information that is meaningful for access will be described. Mention change and retrieval.

The first bridge memory 14 is a memory having an address space corresponding to the maximum value Tmax that can be contracted as the time specified value Ti, and the address specified by the address signal A14 output from the control / judgment circuit 16 Is exchanged with the control / judgment circuit 16 via the bus B14. One address stores information about one arriving cell.

FIG. 5 shows the contents stored at one address n of the first bridge memory 14.
One address n includes a channel number (arrived channel number) CHPn of a cell arriving in the past, a time offset OFn representing a delay time added for compensating cell delay fluctuation for the cell, The cell has its channel (q) in the first and second bridge memories 14 and 15
), An excess cell flag OVn indicating whether the cell has arrived before the allowable maximum cell number Xq, and a valid display flag ENn indicating whether the content of the address is invalid or valid.

The second bridge memory 15 has the same address space as the first bridge memory 14, and stores the contents of the address A14 output from the control / judgment circuit 16 via the bus B15. 16 is exchanged.

FIG. 6 shows information stored in the second bridge memory 15. The second bridge memory 15 has a first bridge memory 14 having the same address n.
The next cell pointer value Nxn, which is pointer information to the position of the first bridge memory 14 that stores the information of the cell arriving immediately after the cell at the address n having the channel number CHPn stored in Stored.

Here, unlike the conventional circuit, information about the same cell arrival is stored in the first bridge memory 14.
And the second bridge memory 15 are stored in two parts because the number of memory accesses is reduced.

A plurality of types of information at the same address stored in the first bridge memory 14 are all accessed simultaneously.
In the description of the processing by, only the change or retrieval of information meaningful for access will be mentioned.

The arithmetic circuit 18 supplies the current time pointer value Cp output from the current time counter 17 and (Xj−) for the channel (j) of the current arrival cell output from the control / determination circuit 16. 1) A pointer value Xpj indicating the arrival time of the cell arriving immediately before, a time offset value OFj for the cell arriving before (Xj -1) times, and a time stipulated value T1j not considering the cell delay fluctuation are given. The circuit 18 performs a predetermined operation using these values, and outputs a difference value D and a CDV correction offset OFCDV, which are the operation results, to the control / determination circuit 16.

FIG. 7 shows a specific configuration example of the arithmetic circuit 18. The arithmetic circuit 18 calculates the current time pointer value Cp
Subtractor 71 subtracting a pointer value Xpj representing the arrival time of the cell arriving (Xj -1) times earlier from the current value, and a time offset value for the cell arriving (Xj -1) times earlier from the subtracted output Cp-Xpj Subtractor 72 for subtracting OFj
And a subtractor 7 for subtracting the subtraction output Cp-Xpj-OFj from a specified time value T1j which does not take cell delay fluctuation into account.
And 3. Then, the output Cp-Xpj-OFj from the subtractor 72 is output to the control / judgment circuit 16 as the difference value D, and the output T1j from the subtractor 73 is output.
− (Cp−Xpj−OFj) is output to the control / judgment circuit 16 as the CDV correction offset value OFCDV.

The control / judgment circuit 16 performs a violation judging process on the currently arriving cell while accessing the bridge memories 14 and 15 and the management table 19 and the like, or as a specified time value Ti in the bridge memories 14 and 15. For example, a process of discharging cell information having passed the maximum value Tmax that can be taken is performed. The ATM switching / transmission system handles a high-speed cell flow and is realized by hardware, but may be realized by software.

FIG. 8 and FIG. 9 are flow charts showing the violation judging process executed by the control / judgment circuit 16. Even if the control / judgment circuit 16 is realized by hardware, such a flow is generally described. Is processed. FIG. 10 is an explanatory diagram showing addresses of both bridge memories 14 and 15 which are accessed in a violation determination process and a cell information discharge process described later.

When the violation judging process is started, first, the channel number CHNO extracted by the header extracting circuit 11 is used.
(Referred to as channel j) as the address signal A19 to access the management table 19, and the management information CNTj, Xpj, Npj, T1j, T2j corresponding to the channel number.
, X1j via the bus B19 (step 1).
00). Then, the control / determination circuit 16 takes out (X
j -1) a pointer value Xpj indicating the arrival time of the cell that has arrived the last time, and a time specification value T that does not consider the cell delay fluctuation.
1j is output to the arithmetic circuit 18 (step 101).

Next, the control / judgment circuit 16 uses the extracted pointer value Xpj as an address signal A14 (address n: see FIG. 10) for both bridge memories 14 and 1.
5 and accesses the stored information CHPn via the bus B14.
, OFn, OVn and Nxn via bus B15.
Is read (step 102). Then, the control / judgment circuit 106 outputs the time offset value OFn read from the first bridge memory 14 to the arithmetic circuit 18 (Step 103).

After performing the above pre-processing, control and
The determination circuit 16 performs a specific violation determination process as described below.

The control / judgment circuit 16 first judges whether or not the number of cells CNTj in the memory relating to the channel j of the currently arriving cell is 0 (step 104).

If the number of cells CNTj in the memory is 0, it is the first cell for the channel j, so it is determined that there is no violation, the various information is updated, and the discard control signal DIS instructing the passage is discarded. This is output to the circuit 13 to end a series of violation determination processing (steps 105 and 10).
6).

The process of updating various information in step 105 is as follows. The first bridge memory 14 is accessed by using the current time pointer value Cp (specific value is s: see FIG. 10) as the address signal A14, and the channel number CHNO (=
j) is written in the arriving channel number CHPs, 0 is written in the time offset value OFs, 0 (0 represents no excess) is written in the excess cell flag OVs, and 1 (1 represents valid) is written in the valid display flag ENs. Further, the management table 19 is accessed by using the channel number CHNO (= j) extracted by the header extraction circuit 11 as the address signal A19, and the number of cells CNTj in the memory is incremented by one, and (Xj -1)
Pointer value Xpj indicating the arrival time of the cell that arrived immediately before
Is updated to the current time pointer value Cp, and the pointer value Npj to the cell that has just arrived is updated to the current time pointer value Cp.

If the number of cells in memory CNTj is not 0 (negative result in step 104), the number of cells in memory CNTj
It is determined whether j is not less than 1 and less than a value X1j obtained by subtracting 1 from the contracted maximum allowable cell arrival number Xj (step 107). That is, it is determined whether or not the number of cells that have counted the cells that have arrived this time is less than the contracted maximum allowable cell number Xj.

If an affirmative result is obtained in this judgment, a time T equal to or more than the contracted time stipulated value Tj for the channel j is obtained.
Since the number of cells arriving within max is less than the contracted allowable maximum number of cells Xj, it is determined that there is no violation, update processing of various information is performed, and a discard control signal DIS instructing passage is output to the discard control circuit 13. A series of violation determination processing ends (steps 108 and 106).

The process of updating various information in step 108 is as follows. The first bridge memory 14 is accessed using the current time pointer value Cp (= s) as the address signal A14, and the channel number CHNO (= j) extracted by the header extraction circuit 11 is set to the arriving channel number CH
In Ps, 0 is written in the time offset value OFs, 0 is written in the excess cell flag OVs, and 1 is written in the valid display flag ENs.
Further, the second bridge memory 15 is accessed by using the pointer value Npj (specific value is t: see FIG. 10) to the immediately preceding arriving cell as the address signal A14, and the next cell pointer Nxt is set via the bus B15. Current time pointer value Cp
Update to Further, the channel number CHNO (= j) extracted by the header extraction circuit 11 is stored in the address signal A.
In step 19, the management table 19 is accessed, the number of cells in memory CNTj is incremented by 1, and the pointer value Npj to the immediately preceding cell is updated to the current time pointer value Cp.

If the number of cells CNTj in the memory is equal to or larger than the contracted maximum allowable cell number Xj minus 1 (No at step 107), the difference value D output from the arithmetic circuit 18 and the cell A comparison is made with a specified time value T1j that does not consider delay fluctuations (step 109).

As a result, when the difference value D is equal to or greater than the specified time value T1j not considering the cell delay fluctuation, it is determined that there is no violation, the various information is updated, and the discard control signal DIS instructing the passage is discarded. The data is output to the control circuit 13 and a series of violation determination processing ends (steps 110 and 10).
6).

The process of updating various information in step 110 is as follows. The first bridge memory 14 is accessed using the current time pointer value Cp (= s) as the address signal A14, and the channel number CHNO (= j) extracted by the header extraction circuit 11 is set to the arriving channel number CH
In Ps, 0 is written in the time offset value OFs, 0 is written in the excess cell flag OVs, and 1 is written in the valid display flag ENs. Further, a pointer value Xpj (= n) representing the arrival time of the cell arriving (Xj -1) cells before is given by the address signal A14.
To access the first bridge memory 14 and write 1 to the excess cell flag OVn. Further, the second bridge memory 15 is accessed by using the pointer value Npj (= t) to the immediately preceding cell as the address signal A14, and the bus B1
5, the next cell pointer Nxt is updated to the current time pointer value Cp. Furthermore, the management table 19 is accessed by using the channel number CHNO (= j) extracted by the header extraction circuit 11 as the address signal A19, and the number of cells CNTj in the memory is incremented by one, and (Xj−
1) Pointer value X indicating the arrival time of the cell that arrived immediately before
pj is updated to the next cell pointer value Nxn, and the pointer value Npj to the immediately preceding cell is updated to the current time pointer value Cp.

If the difference value D is less than the time stipulated value T1j that does not take cell delay fluctuation into account (negative result in step 109), the difference value D is compared with the time stipulated value T2j that takes cell delay fluctuation into account (step S1). 111).

If the difference value D is equal to or greater than the specified time value T2j in consideration of the cell delay fluctuation, it is determined that there is no violation, the various information is updated, and the discard control signal DIS instructing the passage is transmitted to the discard control circuit 13. To terminate the series of violation determination processing (steps 112 and 106).

Steps 109 and 11 described above
The reason why 1 is included in the violation determination processing is that the cell delay fluctuation is considered as follows.

As described above, the difference value D is, as described above, a pointer value Xpj representing the arrival time of the cell arriving (Xj -1) before the current time pointer value Cp, and a pointer value Xpj arriving (Xj -1) before Cp-Xpj-OFj obtained by subtracting the time offset value OFj for the calculated cell. Here, the value Cp−
Xpj is the time required for arrival of the contracted maximum allowable cell number Xj cells including the currently arriving cell for channel j. Therefore, simply, if the required time Cp-Xpj is longer than the contracted time specified value T1j, it can be said that the cell flow speed is lower than the contract and there is no problem. However, even if the network subscriber complies with the traffic contract due to the cell delay fluctuation, the time Cp-Xpj at which Xj cells arrive at the cell flow rate monitoring circuit 10 is less than the contracted time specified value T1j (from the contracted speed). High speed). Therefore, in such a case, the relief is made by comparing the magnitude with the specified time value T2j in consideration of the cell delay fluctuation. However, the time Cp-Xp required for the maximum number of contracted cells Xj to arrive is Cp-Xp
If j is simply compared in magnitude with the specified time value T2j in consideration of the cell delay fluctuation, the violation will be missed even when a certain degree of speed violation occurs due to the cell delay fluctuation. Therefore, the time offset value OFj, which is information reflecting the amount of cell delay fluctuation, is introduced into the violation determination.

The process of updating various information in step 112 is as follows. The first bridge memory 14 is accessed using the current time pointer value Cp (= s) as the address signal A14, and the channel number CHNO (= j) extracted by the header extraction circuit 11 is set to the arriving channel number CH
Ps, the CDV correction offset value OFCDV output from the arithmetic circuit 18 is set to the time offset value OFs, 0 is set to the time offset value OFs, and 0 is set to the excess cell flag OVs.
Is written into the valid display flag ENs. Also, (X
j-1) The first bridge memory 14 is accessed using the pointer value Xpj (= n) representing the arrival time of the cell that arrived the previous time as the address signal A14, and 1 is set as the excess cell flag O
Write to Vn. Further, the second bridge memory 15 is accessed using the pointer value Npj (= t) to the immediately preceding arrival cell as the address signal A14, and the next cell pointer Nxt is updated to the current time pointer value Cp via the bus B15. Furthermore, the channel number CHNO (= j) extracted by the header extraction circuit 11 is stored in the address signal A19.
, The number of cells CNTj in the memory is incremented by one, the pointer value Xpj representing the arrival time of the cell arriving (Xj -1) before is set to the next cell pointer value Nxn, and Pointer value Np
j is updated to the current time pointer value Cp.

According to the determination at step 111 described above,
The difference value D is a specified time value T2j in consideration of the cell delay fluctuation.
If a result of less than is obtained, it is determined that the current cell arrival is a violation even in consideration of the cell delay fluctuation, and the first bridge memory 14 is accessed using the current time pointer value Cp (= s) as the address signal A14. , 0 valid display flag EN
s, and outputs a discard control signal DIS instructing discard to the discard control circuit 13 to end a series of violation determination processes (steps 113 and 114).

FIG. 10 is a flow chart showing the process of discharging cell information from the memory executed by the control / judgment circuit 16. Even when the control / judgment circuit 16 is realized by hardware, this processing is almost completed. Such processing is performed. The cell information discharging process is for discharging the arriving cell information stored in the first and second bridge memories 14 and 15 when the storage time has exceeded the maximum time Tmax that can be the specified time value Ti. This is executed following the above-described violation determination processing.

When the cell information discharging process is started, first, a value Lp obtained by adding the current time pointer value Cp and the maximum time Tmax that can be the specified time value Ti is obtained, and this added value Lp
(Specify a specific value v: see FIG. 10).
14, the first bridge memory 14 and the second bridge memory 15 are accessed, the arriving channel number CHPv, the excess cell flag OVv, and the valid display flag ENv are read out via the bus B14, and the next cell is read out via the bus B15. The pointer Nxv is read (steps 120 and 12).
1).

Then, the read valid display flag EN is read out.
It is determined whether or not v is 0 (step 122).

If the read valid display flag ENv is 0, it is determined that the read arrival cell information is invalid, and the series of cell information discharge processing ends without performing any processing.

On the other hand, if the valid display flag ENv is 1, it is further determined whether or not the read excess cell flag OVv is 0 (step 123). If the excess cell flag OVv is 1, the already-arrived channel number CHPv (referred to as channel w) that has been read is used as the address signal A19.
Then, the management table 19 is accessed, the number of cells in memory CNTw is decremented by 1, and a series of cell information discharge processing ends (step 124). Excess cell flag OVv
Is 0, the management table 19 is accessed using the already-arrived channel number CHPv as the address signal A19, and the number of cells CNTw in the memory is decremented by one, and (X
(w-1) The pointer value Xpw representing the arrival time of the cell that has arrived the previous cell is set to the next cell pointer value Nxv (specific value is y: see FIG. 10), and a series of cell information discharge processing is completed (step). 125).

In the process of updating the management table 19, the number of cells in the first and second bridge memories 14 and 15 is correctly counted, and the pointer value Xpw is also correctly determined by the process of discharging the cell information. This is performed to indicate the position of (Xw-1) previous valid cell information (or the oldest valid cell information).

Next, the network user (channel j) outputs a cell at the maximum speed that complies with the contract, and the speed of this cell flow is
An operation in the case of arriving at the cell flow rate monitoring circuit 10 according to the embodiment while oscillating in the increasing direction under the influence of the cell delay fluctuation generated in the cell multiplexing configuration upstream of the cell flow rate monitoring circuit 10 according to the embodiment will be described.

When the first cell arrives, the control / judgment circuit 16 passes this cell without any violation (steps 100 to 106). Also, from the second cell, Xj−
Even before the first cell arrives, the control / judgment circuit 16 passes this cell without any violation (step 100).
To 104, 107, 108, 106). In such a state, the information updating process in step 105 or 108 described above is executed, and the pointer value Xpj indicating the arrival time of the cell arriving before (Xj -1) is set to the current time counter 17 when the first cell arrives. Is maintained.

When the Xj-th cell arrives, the determination in step 109 is made for the first time. Since the time offset value OFn taken out at this time is for the first cell and is 0, the difference value D remains the time required for Xj cells to arrive. Specified time T without considering delay fluctuation
1j. Therefore, in this case, the difference value D is also compared with the time specification value T2j taking cell delay fluctuation into consideration (step 111). However, since the cell transmission this time is in compliance with the contract, the cell transmission is naturally larger than the time stipulated value T2j in consideration of the cell delay fluctuation, and the control / determination circuit 16 passes this cell without any violation (step 112). , 106). Note that, by the information updating operation performed at this time, a time stipulated value T1j (contract time) that does not take cell delay fluctuation into consideration and a difference value D (in this case, the time itself required for Xj cells to arrive) are obtained. Is set as the time offset value OFs for the Xj-th arriving cell.

Such an operation is repeated until the Xj-th arriving cell becomes a cell arriving (Xj -1) before the cell arriving at the present time.

When the Xj-th arriving cell becomes the cell arriving (Xj -1) cells before the cell arriving at the present time, the difference value D is calculated from the time required for the Xj cells to arrive. This is a value obtained by subtracting the offset value OFn. Therefore, the determination in step 111 is strict, excluding the provision of the tolerance (T1j-T2j) due to the cell delay fluctuation. However, since the current cell flow is transmitted by the network user (channel j) in compliance with the contract, the time offset value OFn may be larger than the allowable value of cell delay fluctuation (T1j-T2j). Few occur and it is unlikely that cells will be discarded.

The case where the traffic contract is complied with at the full contract speed has been described above. As can be inferred from the above explanation, if the contract is slightly violated to the extent that it is smaller than the allowable value of the cell delay fluctuation, the speed or
No discard occurs in the cell flow portion where the speed is reduced, but cell discard frequently occurs in the cell flow portion where the speed is increased due to fluctuation. Further, when the contract is violated beyond the allowable value of the cell delay fluctuation, the cell is frequently discarded throughout even if there is a cell flow part whose speed is slightly reduced due to the cell delay fluctuation.

Therefore, according to the above embodiment, not only the allowable time for the cell delay fluctuation is set, but also the time offset value is calculated and the information of the cell delay fluctuation is reflected in the subsequent violation determination. Therefore, even if a cell delay fluctuation occurs in the cell flow in the upstream device, it is possible to realize a cell flow monitoring circuit that can accurately determine a violation and that can effectively use network resources.

In the above embodiment, since the bridge memory holding the cell arrival history information is composed of two bridge memories, the number of accesses to the bridge memory can be reduced, and a memory having a low access speed can be used. It is possible to do.

The present invention is not limited to the above embodiments, but can be variously modified. For example, one or three bridge memories that hold the arrival history of cells, one in which the history information stored in the bridge memory is arranged for each channel, or one in which the storage information of the bridge memory or the management table is changed And the like.

The present invention is not limited to a system applied to an ATM switching / transmission system, but can be widely applied to a switching / transmission system using cells (fixed length packets).

[0086]

As described above, according to the present invention, the time T
A cell flow monitoring circuit that constantly monitors and controls whether or not an actual cell flow violates a traffic contract defined by the maximum number X of cells that can be allowed per unit by using a specified allowable value of cell delay fluctuation. A cell arrival history information holding means for holding cell arrival history information, and an X-th cell to be processed which is determined to be a violation at the present time by using the contents held by the cell arrival history information holding means. (X-1) from the processing target cell based on the time required for the X cells to arrive.
An arrival time interval calculating means for obtaining an arrival time interval obtained by subtracting a time offset value associated with a cell which has arrived immediately before; and an arrival time interval obtained by the arrival time interval calculating means, which is a cell delay fluctuation tolerance from time T. Violation determining means for determining a violation only when the value is smaller than
When the arrival time interval obtained by the arrival time interval calculation means is less than the time T and is equal to or greater than a value obtained by subtracting the allowable value of the cell delay fluctuation from the time T, a value obtained by subtracting the arrival time interval from the time T is calculated. And the time offset calculating means for holding the cell arrival history information holding means as an offset value associated with the cell to be processed, so that even if a cell delay fluctuation occurs in the cell flow in the upstream device, it can be accurately performed. Violation determination can be performed, and network resources can be used effectively.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment.

FIG. 2 is a block diagram showing a conventional configuration.

FIG. 3 is a cell format diagram for explaining channel number information extracted from an arrival cell according to the embodiment;

FIG. 4 is an explanatory diagram illustrating a configuration of a management table according to the embodiment.

FIG. 5 is an explanatory diagram illustrating a configuration of a first bridge memory according to the embodiment;

FIG. 6 is an explanatory diagram illustrating a configuration of a second bridge memory according to the embodiment;

FIG. 7 is a block diagram illustrating a detailed configuration of an arithmetic circuit according to the embodiment.

FIG. 8 is a flowchart (part 1) illustrating a violation determination process according to the embodiment;

FIG. 9 is a flowchart (part 2) illustrating a violation determination process of the embodiment.

FIG. 10 is an explanatory diagram illustrating a relationship between an address of a bridge memory and a process according to the embodiment;

FIG. 11 is a flowchart illustrating a cell information discharging process according to the embodiment.

[Explanation of symbols]

10: cell flow rate monitoring circuit, 11: header extraction circuit, 14
... first bridge memory, 15 ... second bridge memory, 16 ... control / judgment circuit, 17 ... current time counter, 1
8 arithmetic circuit, 19 management table, Cp current pointer value, Xpj pointer value to the cell arriving (Xj -1) before channel j, OFj time offset value, T1j cell delay fluctuation A specified time value that does not consider (CDV).

Continuation of the front page (56) References JP-A-4-259143 (JP, A) JP-A-5-191428 (JP, A) JP-A-5-207051 (JP, A) JP-A-5-260072 (JP) , A) JP-A-5-284173 (JP, A) JP-A-5-327756 (JP, A) Proceedings of the IEICE Spring National Convention, B-674 (1992-3-15), p. −241 Proceedings of the IEICE Autumn National Convention, B-478 (1992-9-15), P. 3-144 IEICE Technical Report, SS E93-40 (1993-9-30), . 7-12 IEICE Technical Report, SSE 93-39 (1993-9-30), p. 1-6 (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 12/28 H04L 12/56

Claims (1)

(57) [Claims] 1. The maximum number of cells X permissible per time T
A cell flow monitoring circuit that constantly monitors and controls whether or not an actual cell flow violates a traffic contract specified in, using a specified cell delay fluctuation allowable value; Cell arrival history information holding means for holding the cell arrival history information holding means,
Attach to the cell arriving (X-1) cells ahead of the cell to be processed from the time it took for the X cells to arrive at the X-th cell to be processed for which it is determined at this time whether or not it is a violation. An arrival time interval calculating means for calculating an arrival time interval obtained by subtracting a time offset value to be calculated; and an arrival time interval obtained by the arrival time interval calculating means, wherein the arrival time interval is smaller than a value obtained by subtracting a cell delay fluctuation allowable value from the time T. Only when the arrival time interval obtained by the arrival time interval calculation means is less than the time T and is equal to or greater than a value obtained by subtracting the permissible cell delay fluctuation value from the time T, Time offset calculating means for calculating a value obtained by subtracting the arrival time interval from the time T and holding the calculated value as a time offset value associated with the processing target cell in the cell arrival history information holding means. Cell flow monitoring circuit characterized.