JP2751941B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to a fault-tolerant computer.

[0002]

2. Description of the Related Art Conventionally, this type of information processing apparatus employs the following method as a method for keeping the system operating without a failure even when a failure occurs.

1: Hot decision system in which a sub system operates when one system goes down.

[0004]

The prior art has the disadvantage that if two parts fail, the system goes down.

It is an object of the present invention to provide an information processing apparatus which keeps operating even if multiple failures occur without the system going down.

[0006]

An information processing apparatus according to the present invention has N processor modules that execute the same processing in synchronization with each other. The processor module includes a processor and (N-1) other than the processor. A switching device that switches and outputs the outputs of the processors, a comparator that compares the output of the processor with the output of the switching device, a counter that is counted by a comparison result of the comparator, and an output result of the counter. Switching means for instructing the switching device to perform switching in response to the control signal, and means for disconnecting the processor in accordance with the output result of the counter.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a system capable of withstanding a double failure by a four-processor configuration. First, the configuration of FIG. 1 will be described.

The processors 110 to 113 execute the same processing in synchronization with each other, and data output from the processors is input to comparators 130 to 133 corresponding to the data buses 170 to 173, respectively. Each data is also input to the corresponding driver 140 to 143 at the same time.

The data to be input to each of the comparators 130 to 133 as a comparison target is uniquely determined by using the switching devices 120 to 123 and becomes comparison target data. The condition of the data input to each of the switching devices 120 to 123 is that the data is from a processor other than the data from the processor to be compared. Next, each counter 150 ~
Of the 153, only the counter corresponding to the comparator whose comparison result does not match is incremented. The output of the counter is input to the switching devices 120 to 123 to switch the data to be compared. Further, each of the comparators 130 to 133
From the corresponding drivers 140 to 143, respectively.
It is connected to the.

If the comparison results of the comparators 130 to 133 do not match, it is assumed that the processor outputting the data to be compared outputs erroneous data, that is, that the processor has failed. Disable the driver so that data does not flow.

The signal from the comparison result is OR gate 1
If any one of the comparators outputs an inconsistent result when input to the signal lines 60 to 163, the signal lines 180 to 183
And instruct each processor 110-113 to re-execute.

Switching devices 120-1 for deciding a comparison object
The connection order of the 23 inputs is connected in order from the number next to the processor number to be compared. Therefore, for example, the order of the switching device 122 is the data of the processor 113 first, then the data of 110, and then the data of 111.

If any of the counters 150 to 153 is counted three times, the data to be compared cannot obtain a result equal to any of the data to be compared, and a signal indicating a failure of the processor is output. Is output from the counter.

Next, an operation example will be described.

While all the processors are operating normally, the data of each processor is transmitted on data buses 170 to 17 respectively.
3 and written into the memory 190 via the drivers 140 to 143.

Here, for example, when the processor 111 fails, the comparison results of the comparators 130 and 131 do not match each other. Also, the comparison results of the comparators 132 and 133 remain equal. Therefore, from this result, the processors 110 to 11
3 can be assumed to be faulty, at which time all processors are notified of re-run instructions via OR gates 160-163 and re-run. The counters 150 and 1 connected to the comparators 130 and 131 that have resulted in a mismatch at the same time
51 is incremented. By switching the data input to the switching devices 120 and 121, the comparator 130 compares the data of the processors 110 and 112, and the comparator 131 compares the data of the processors 111 and 113. As a result of the change of the comparison target data, the comparison result of the comparator 130 becomes equal, and the comparison result of the comparator 131 remains inconsistent. So this time counter 15
Only 1 is incremented. Then, the data of the processor which is inputted to the switching device and compared is changed, and the comparator 131
Then, the comparison between the processors 111 and 110 is performed. Since the result is also inconsistent, the value of the counter 151 is incremented. Then, since the counter 151 has counted 3 times, a stop instruction of the processor 111 occurs, and the processor 1
11 stops. Then, the processor 111 is disconnected because it is determined that it is faulty.

Next, for example, even if the processor 112 is still faulty and the processor 112 is faulty, the above-described processing is repeated.
Obviously, two faults can be detected. At this time, the remaining normal processors 110 and 113 are performing normal processing. And a new processor 1
Connecting 11 or 112 resets all counters and returns to normal processing with four processors running.

The above is an embodiment of the present invention. In the above embodiment, only the case of four processors has been described.
Even in the case of N processors, by repeating the above processing, it is possible to withstand up to (N−2) failures and keep the whole system operating.

Therefore, it can be said that the system can withstand multiple failures that cannot be realized by the conventional device.
Further, a processor, a switching device, a comparator, a counter,
By forming the driver, the OR gate, and the signal line connecting them as one module on a board, it is possible to easily replace each module.

[0021]

As described above, the present invention has an effect that the system continues to operate without down even if multiple failures occur by connecting a plurality of processors performing the same processing in synchronization. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

[Explanation of symbols]

 110-113 Processor 120-123 Switching device 130-133 Comparator 140-143 Driver 150-153 Counter 160-163 OR gate 170-173 Data bus 180-183 Signal line 190 Memory

Claims (1)

(57) [Claims] 1. An apparatus comprising: N processor modules that execute the same processing in synchronization with each other, wherein the processor modules switch the processor and the output of (N−1) processors other than the processor as an input. A device, a comparator for comparing the output of the processor and the output of the switching device, a counter counted based on the comparison result of the comparator, and a switch for instructing the switching device to switch according to the output result of the counter. An information processing apparatus comprising: an instruction unit; and a unit that disconnects the processor according to an output result of the counter.