JP2719280B2 - Computer system and high-speed I / O data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory incorporated in a processor of a computer system, a main memory, an I / O.
A computer system suitable for satisfying high throughput and high responsiveness and a high-speed I / O
O relates to a data transfer method.

[0002]

2. Description of the Related Art In recent years, distributed systems have become mainstream in the field of information processing, and I / O systems such as networks and file systems have been widely used.
The performance of the I / O device is an important factor that affects the performance of the entire system including the network. In addition, multimedia has been promoted with an emphasis on an interface between a human and a computer, and high responsiveness (real-time property) has been emphasized in a file, network, and graphics system. In order to fulfill these requirements, the data transfer between the processor, the main memory and the I / O device must be
Both high throughput and high responsiveness are required.

[0003] In networks and file systems,
To be able to transfer large amounts of data quickly,
High throughput is required. On the other hand, in data transfer requiring real-time characteristics such as images and sounds, high responsiveness is required. In graphics, it is required to transfer a large amount of data between the main memory and the frame memory for graphics in a short time for three-dimensionalization and colorization.
High throughput is required. On the other hand, when it is required to immediately respond to human input, high responsiveness is required.

Conventionally, as a data transfer method between a main memory and an I / O device, a DMA method and a direct I / O
The / O access method is the mainstream. In the DMA system, I /
A data transfer device independent of the processor is provided on the O device side.

[0005] Data on the main memory is I / O by DMA method.
The procedure for transferring data to the device is shown below. (1) Create a DMA control block containing data and control information and connect it to a software queue for requesting DMA to perform processing. The software queue is placed on main memory. (2) DMA is started on the I / O device by writing to a specific I / O space address by direct I / O access means.

(3) The DMA reads the control block on the main memory and identifies the requested processing content. (4) If the transfer is from the main memory to the I / O device, the data in the main memory is read and transferred to the local memory of the I / O device.

In general, the size of data that can be transferred by one operation can be selected from 16 bytes to 32 bytes, and block transfer is possible. Therefore, high transfer throughput can be realized for large-capacity data transfer. Another feature is that a large amount of data can be transferred without placing a burden on the processor. Generally, the file system and the network system mainly use the DMA system.

In the direct I / O access method by the processor, data is directly transferred to the I / O device by executing an instruction by the processor. Direct I / O of data on main memory
The procedure for transferring data to the I / O device by the access method will be described below. (1) The data on the main memory or the data on the local memory in the I / O device is read into a register in the processor by a load instruction. (2) Write the contents of the register in the processor to the local memory or main memory in the I / O device by a store instruction.

Generally, the data size that can be transferred at one time is limited to the data size that can be handled by an instruction, and is 4 bytes or 8 bytes.

Japanese Patent Application Laid-Open No. 63-20 / 1988 relates to data transfer between the main memory and the I / O memory.
No. 4352.

[0011]

[Problems to be solved by the invention]

1. Problems in file and network systems:
In file systems and network systems, it has been important to transfer large amounts of data in a short period of time, and responsiveness has not been particularly emphasized in the past. For this reason, the DMA transfer method is mainly applied. In the DMA system, block transfer of 16 to 32 bytes is possible in one operation, and a high transfer throughput can be obtained. However, with the advancement of multimedia in computer systems, demands for handling voice and image data in file and network systems are increasing. I / O for audio and image data
When transferring to a device, it is required to repeatedly transfer a large amount of data according to a predetermined cycle. For example, in the case of an image, 30 frames of image data per second must be transferred to the I / O device at the same interval.

In such an application, there is a problem that the response is poor in the DMA transfer method and the real-time property cannot be guaranteed. That is, in order to perform the DMA transfer, the DM
A procedure for preparing the A control block and activating the DMA is required, so that it takes time until the DMA device is activated, resulting in poor responsiveness.

On the other hand, if the I / O direct transfer method is used, data can be transferred directly from the processor to the I / O device, so that immediacy can be easily guaranteed. However, since the size that can be transferred at one time is limited, there is a problem in that transfer throughput is insufficient when transferring large-capacity data such as images and sounds.

2. Problems in the graphics system: In the graphics display system, high responsiveness such that the display is changed immediately according to the input by the user is required. For this reason, an I / O direct transfer system with high responsiveness is desirable. In the I / O direct access method, data in a register in the CPU can be directly transferred to the I / O space by an instruction executed by the processor. Therefore, compared with the DMA system, a procedure for creating a control block is not required, and the responsiveness seen from the processor is high.

However, in a three-dimensional or more complicated graphics display system, a large amount of data transfer is required in addition to high responsiveness. The I / O direct transfer method has high responsiveness, but has a limitation in data transfer throughput, and is not suitable for such use. This is
This is because in the / O direct transfer method, the data size that can be transferred at one time is limited to 4 bytes or 8 bytes that can be handled by the instruction. For this reason, the known example “CM
OS / PIA RISC Processor for a New Family of Workstations "COM
PCON91, February 25-March 1, 1991 ("CM
OS PA-RISC PROCESSOR FOR A NEW FAMILY OF WORKSTATI
ONS "), a store instruction capable of 16-byte data transfer is also realized. However, there is a limit to the transfer throughput in data transfer by an instruction via a register in the processor.

3. Issues in the cluster computer system: A cluster computer system in which computers are connected by an I / O bus or a high-speed network, or a multi-computer system has attracted attention. In such a system, communication means that enables high responsiveness and high throughput, such as synchronization between computers or transfer of shared data, is required. The I / O direct transfer method has high responsiveness but has a limit in data transfer throughput, and is not suitable for such use. On the other hand, the DMA transfer method has a problem that the transfer throughput is high but the response is poor.

In a computer system in which a processor has a cache memory, in addition to the problem of the conventional data transfer method described above, a problem that data in the cache memory must be transferred to the main memory and then transferred to the I / O device. However, there is a problem that responsiveness is further deteriorated.

An object of the present invention is to provide a high-speed I / O data transfer method that satisfies both high throughput and high responsiveness in data transfer from a cache memory to a main memory and an I / O device.

Another object of the present invention is to provide a high-speed I / O data transfer method and the like which can transfer large-size block data directly to an I / O device with one instruction executed by a processor.

It is another object of the present invention to provide a high-speed I / O data transfer method and the like that enables block data to be transferred to both a main memory and an I / O device with one instruction executed by a processor. It is in.

Another object of the present invention is to provide a high-speed I / O bus or a high-speed I / O bus capable of directly transferring block data to another computer by an instruction executed by a processor as a communication means between computers connected by a high-speed network. An object of the present invention is to provide an I / O data transfer method and the like.

Another object of the present invention is to transfer block data directly to a graphics frame memory by one instruction executed by a processor, thereby enabling high-speed I / O capable of displaying a large amount of graphics data immediately. It is to provide a data transfer method and the like.

Another object of the present invention is to provide a high-speed I / O data transfer method capable of transferring block data to different I / O devices by switching an operation target address of an instruction executed by a processor. is there.

[0024]

It is an object of the present invention to provide a data transfer instruction for forcibly writing block data (32 bytes to 128 bytes) in a cache memory to a main memory and an I / O space by an instruction executed by a processor. An interface unit for connecting a processor, a main memory, and an I / O device with identification means for identifying a transaction according to the block transfer command sent by the processor; This is achieved by providing a function of transmitting data to both the I / O device and the I / O device, and providing a function of converting the address of the transaction in the interface unit and converting it into a transaction to the I / O device.

Another object of the present invention is to forcibly block data (32 bytes to 128 bytes) in a cache memory with a main memory and an I / O by an instruction executed by a processor.
A data transfer instruction for writing to a space; an interface unit for connecting the processor with the main memory and the I / O device; an identification unit for identifying a transaction based on the block transfer instruction sent by the processor; A function for transmitting the received transaction to both the main memory and the I / O device according to the result; a function for converting the address of the transaction to the interface unit and converting the transaction to a transaction for the I / O device; O
This is achieved by providing a function of receiving block data and transferring the block data to another computer via an I / O bus or a high-speed network.

Another object of the present invention is to forcibly block data (32 bytes to 128 bytes) in a cache memory with an instruction executed by a processor and to forcibly store data in a main memory and an I / O.
A data transfer instruction for writing to the space; an interface unit for connecting the processor with the main memory and the I / O device; and an identification unit for identifying a transaction based on the block transfer instruction sent by the processor. A function for transmitting the received transaction to both the main memory and the I / O device according to the result; a function for converting the address of the transaction to the interface unit and converting the transaction to a transaction for the I / O device;
This is achieved by providing the O device with a function of receiving block data and writing the block data to the graphics display frame memory.

Another object of the present invention is to forcibly block data (32 bytes to 128 bytes) in a cache memory with an instruction executed by a processor and to forcibly store data in a main memory and I / O.
A data transfer instruction for writing to the space; an interface unit for connecting the processor with the main memory and the I / O device; and an identification unit for identifying a transaction based on the block transfer instruction sent by the processor. A function of transmitting a received transaction according to the result to both the main memory and the I / O device is provided.
This is achieved by converting the address to the / O device.

Another object of the present invention is to forcibly block data (32 bytes to 128 bytes) in a cache memory with an instruction executed by a processor and to store the block data in a main memory and an I / O.
A data transfer instruction for writing to the space; an interface unit for connecting the processor with the main memory and the I / O device; and an identification unit for identifying a transaction based on the block transfer instruction sent by the processor. According to the result, a function for transmitting the received transaction to both the main memory and the I / O device is provided, and an I / O device is provided with an address conversion function for converting the address of the received transaction into an address for the own I / O device. That is achieved.

[0029]

According to a data transfer instruction for forcibly writing block data in the cache memory to the main memory and the I / O space, a block containing data to be transferred to the I / O device is transferred from the processor to the main memory and the I / O device. To the interface unit that connects At this time, this identification is facilitated by adding to the block transaction an identifier indicating data to be transferred to both the main memory and the I / O device. When recognizing the identifier of the transaction, the interface unit writes the transaction to the main memory and, at the same time, converts the address of the transaction into the address of the I / O device and transmits the address to the I / O device. If the I / O device receiving the block data of the transaction is an I / O device for inter-computer communication, the I / O device transfers the block data to the I / O device.
The data is transferred to another computer via the O bus or a high-speed network. In the case of a graphics I / O device, block data is written to a frame memory. This makes it possible to directly transfer block data of a large size to an I / O device by executing an instruction by a processor without creating a transmission control block in advance as in the DMA transfer method.

The address translation table used for the address translation is composed of a plurality of entries. The address of the block data received from the processor is verified for which I / O device is the transaction, and the target I / O device is verified. The address is converted to the address of the O device and transferred to the I / O device.
Thus, by switching the address, it is possible to simultaneously transfer the block data to a plurality of I / O devices.

An address translation mechanism provided on the I / O device verifies whether the address of the received block data is an address to the own I / O device, and if the address is to the own I / O device. If this is accepted. Thus, by switching the address, it is possible to simultaneously transfer the block data to a plurality of I / O devices.

[0032]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is an overall configuration diagram of a computer system according to one embodiment of the present invention. The processor 100 is connected to the system control device 200 via the processor shared bus 1400. The system control device 200 is connected to the main memory 300 via the main memory bus 1600. Also, the system controller 200
Are connected to an input / output control device 400, a network control device 500, a file control device 600, and a graphics control device 700 via an input / output bus 1500. An access request to the main memory from the processor 100 is sent to the system controller once.
Accepted for 200. The system control device 200 verifies the access destination from the accepted access address. If the access is to the memory space, an access request is issued to the main memory 300. If the processor 100 accesses the I / O device (hereinafter, referred to as I / O direct access by the processor), the system controller 200 controls the I / O bus 1500
Issue an access request above. Each I / O device 400, 500,
Each of 600 and 700 accepts an access request on the I / O bus 1500 and verifies whether or not the address is an access to its own device. If the access request is for the own device, the requested processing (setting of a register, control of an I / O device, etc.) is performed.

The file control device 600 controls data transfer between the fixed disk device 1100 and the main memory 300.
The network control device 500 controls data transfer between the main memory 300 and a network such as FDDI or Ethernet. The graphics controller 700 controls data transfer between the display frame memory 800 and the main memory 300. The data in the frame memory 800 is stored in the graphics controller 700
Is displayed on the display device 1200. Also, the I / O control device 400 is a floppy disk device 900 or a printer device 1000.
And the main memory 300 to control data transfer.

Each I / O control device is provided with a DMA (Direct Memo).
ry Access) function. The DMA function allows each I / O device to load the I / O bus 1 without imposing a load on the processor 100.
Data can be transferred to and from the main memory 300 via the interface 500. Data transfer unit of DMA access is 4, 8, 1
Various transfer sizes such as 6, 32 bytes can be selected. The data transfer procedure using the DMA function will be described below.

(1) The processor stores D in the main memory 300.
A DMA control block for instructing the operation of the MA is created and connected to the instruction queue. (2) The I / O direct access activates the DMA function of the target I / O device. (3) The activated DMA reads the instruction from the instruction queue on the main memory 300, and according to the contents, reads the instruction.
And data transfer between the I / O device. (4) When the execution of one instruction is completed, the completion is reported to the processor 100 by the interrupt function. FIG. 3 is an internal configuration diagram of the processor 100. The instruction fetch unit 101 reads an instruction necessary for executing a program from the main memory 300. The read instruction is transferred to the instruction execution unit 102. The instruction execution unit 102 interprets the meaning of the instruction and stores data necessary for executing the instruction in the main memory.
Execute the read operation from 300. The instruction address conversion buffer 103 and the data address conversion buffer 104 are provided to realize a virtual storage system. Instruction fetch unit 101 and instruction execution unit 1 respectively
02 converts a virtual address issued when reading the main memory 300 into an actual main memory address (hereinafter, a real address). The instruction cache memory 105 is a high-speed memory that copies and holds a part of the instruction on the main memory 300.
If the instruction requested by the instruction fetch unit 101 exists in the instruction cache memory 105, data can be read immediately without accessing the main memory 300. If the requested instruction does not exist in the cache memory, the instruction cache memory 105
Request data from the main memory 300 via the.

The data cache memory 106 is the main memory 3
It is a high-speed memory that holds a part of the data of 00. The data requested by the instruction execution unit 102 is stored in the cache memory 106.
If it exists, the data can be provided immediately without accessing the main memory 300. If the requested data does not exist in the cache memory, the data cache memory 106 requests the data from the main memory 300 via the main memory interface 107. Cache memory 106
The data transfer between the cache memory and the main memory 300 generally improves the hit rate of the cache memory by using a block of about 32 to 128 bytes as a transfer unit.

Data cache memory in this embodiment
In 106, the main memory write processing from the instruction execution unit 102 is accelerated by the store-in method. In the store-in method, if data to be written exists in the data cache memory 106, writing is performed only to the data cache memory and not performed to the main memory 300. The block in the data cache where the writing has been performed is called a dirty block. The dirty block is written back to the main memory 300 when the data cache memory 106 overflows.

The instruction execution unit 102 can execute an instruction for forcibly writing back any dirty block in the data cache memory 106 to the main memory. The dirty blocks flushed from the data cache memory 106 are transferred to the system control device 200 via the memory interface 107. At this time, if necessary, the instruction executed by the instruction execution unit 102 can specify that the dirty block be transferred to both the main memory and the I / O device. At this time, an identifier indicating data transfer to both the main memory and the I / O device is added to the dirty block to be written back.

The I / O direct access executed by the instruction operation unit 102 is transferred to the system controller 200 via the direct memory interface 107 without accessing the data cache memory 106. Therefore, the data transfer unit in the I / O direct access is 4 bytes.

FIG. 1 is an internal configuration diagram of the system control device 200. The system control device 200 includes a processor interface unit 2000, an I / O bus interface unit 3000, and a main memory interface unit 4000. The processor interface unit 2000 is connected to the plurality of processors 100 via the processor shared bus 1400, and controls data transfer with the processor 100. The access request from the processor 100 is received by the address / data reception register 2020 and the associated information register 2010. Then, according to the contents of the accompanying information register 2010, if the request is to read a block from the main memory, a read block address buffer 2040 including a plurality of entries
It is stored in the read block accompanying information buffer 2030. In the case of a block write request, the address is a write block address buffer 20 composed of a plurality of entries.
60, stored in the write block accompanying information register 2050,
The write data is stored in the write block data buffer 2070.

Since the main memory write request from the processor is issued in block units, the write block data buffer 2070 can hold a plurality of blocks. In the case of an I / O direct access request, the address is an I / O address buffer consisting of a plurality of entries.
2090, stored in the I / O associated information buffer 2080. Data is stored in the I / O data buffer 2100.

If the access request received from the processor shared bus 1400 is a block data transfer request to both the main memory and the I / O device (hereinafter, I / O direct block transfer request), the address is a write consisting of a plurality of entries. The data is stored in the block address buffer 2060 and the write block associated information register 2050, and at the same time, is also stored in the I / O address buffer 2090 and the I / O associated information buffer 2080 having a plurality of entries. The transfer data is stored in the write block data buffer 2070 and at the same time,
Also stored in the / O data buffer 2100.

The main memory read access request stored in the read block address buffer 2040 and the read block associated information buffer 2030 is sent to the main memory interface unit 4000. That is, the data is transferred to the main memory via the selector 4040 and the main memory address register 4020. The block read from the main memory is stored in the read block data buffer 2130 and the read block associated information register 2120 from the main memory bus 1600 via the main memory bus reception register 4010. Then, the processor is transmitted via the processor shared bus transmission registers 2150 and 2140.
Transferred to 100.

The main memory write access request stored in the write block address buffer 2060, the write block associated information register 2050, and the write block data buffer 2070 is sent to the main memory interface unit 4000. That is, the address is transferred to the main memory via the selector 4040 and the main memory address register 4020. The write data is sent to the main memory via the selector 4050 and the main memory data transmission register 4030.

The I / O direct access requests stored in the I / O address buffer 2090, the I / O associated information buffer 2080, and the I / O data buffer 2100 are sent to the I / O bus interface unit 3000. That is, address 2090,
Data 2100 is set in I / O bus transmission registers 3090 and 3080 via selectors 2160 and 3110, and then transmitted to I / O bus 1500. The data read from the I / O device is transmitted from the I / O bus 1500 to the I / O bus reception register 302.
0, stored in the read block data buffer 2130 and the read block accompanying information register 2120 via the I / O bus accompanying information receiving register 3010. Then, the processor 10 is transmitted via the processor shared bus transmission registers 2150 and 2140.
Transferred to 0.

An I / O address buffer 2090, an I / O ancillary information buffer 2080, and an I / O data buffer 2100 are also received as block data transfer requests to both the main memory and the I / O device. Direct block transfer requests. It is sent to the I / O bus interface unit 3000. That is, the address 2090 is stored in the address conversion unit 21.
According to 10, the address from the main memory space is converted to the address to the I / O device. Then, the selectors 2160, 3110
After being set in the I / O bus transmission registers 3090 and 3080 via the I / O bus 1500, it is transmitted to the I / O bus 1500. The block data stored in the I / O data buffer 2100 also passes through the I / O bus transmission registers 3090,
After being set to 3080, it is transmitted to the I / O bus 1500.

I / O bus interface unit 3000
Is connected to a plurality of I / O devices via an I / O bus 1500, and controls data transfer with the I / O devices. The DMA request from the I / O device is sent to the I / O bus reception register 3020,
It is received by the O bus accompanying information reception register 3010. Then, the address is stored in the DMA address register 3040 and the DMA accompanying information register 3030. The write data is stored in the DMA write data buffer 3050. D
In the MA access, various block data transfer sizes such as 4, 8, 16, and 32 bytes can be designated. For this reason D
The MA write data buffer 3050 can hold a plurality of block data.

The DMA access requests stored in the DMA address register 3040, the DMA associated information register 3030, and the DMA write data buffer 3050 are sent to the main memory interface unit 4000. That is, the address is transferred to the main memory via the selector 4040 and the main memory address register 4020. The write data is sent to the main memory via the selector 4050 and the main memory data transmission register 4030. The block data read from the main memory is transferred from the main memory bus 1600 to the DMA read data buffer via the main memory bus reception register 4010.
3070, stored in the DMA read data accompanying information register 3060. Then, the data is transferred to the I / O device via the I / O bus transmission registers 3090 and 3080.

FIG. 4 is a detailed block diagram of the address conversion unit 2110 used for I / O direct block transfer. I
In the I / O device target address 2113, the address of the I / O device to be subjected to I / O direct block transfer is registered. The address conversion control unit 2111 determines whether the target I / O bus access request is
/ O Identifies whether direct block transfer. If the request is an I / O direct block transfer request, the selector 2112 controls the selector 2112 to select the registered address register 2113 of the I / O device, and generates addresses 2118 and 2119 corresponding to the I / O device.

FIG. 5 is another configuration diagram of the address conversion unit 2110 used for I / O direct block transfer. I
In the I / O device detection address tag 2113 and the I / O device target address 2114, a plurality of identification addresses of I / O devices and I / O device addresses to be subjected to I / O direct block transfer can be registered. ing. The address conversion control unit 2111 identifies whether or not the target I / O bus access request is an I / O direct block transfer from the contents of the I / O associated information buffer 2080. If the request is an I / O direct block transfer request, the selector 2112 is controlled to control the registered I / O
Select the address of the O device. I / O address buffer
A part of 2090 is compared with the I / O device detection address tag 2113, and the I / O device target address 21 of the matched entry is compared.
14 is used to complete the address translation.

Next, a second embodiment of the present invention will be described. In the above-described first embodiment of the present invention, when a block data transfer request is issued from the processor to both the main memory and the I / O device, the address conversion unit 2110 in the system controller 200 changes the access address to the main memory. The address is converted to an address for the I / O device. The first embodiment is characterized in that a function of converting an access address to a main memory into an address to an I / O device is provided on the I / O device side.
Different from the embodiment. The operation in this case is defined by the main memory and the I / O
The description is limited to block data transfer requests to both O devices.

When the processor 100 executes an instruction to transfer a dirty block in the data cache memory 106 to both the main memory and the I / O device, the system controller 200 issues a block data transfer request (hereinafter referred to as I / O).
O direct block transfer request). The address is a write block address buffer 2060 composed of a plurality of entries, and a write block associated information register 2050.
I / O consisting of multiple entries at the same time
It is also stored in the address buffer 2090 and the I / O associated information buffer 2080. The transfer data is stored in the I / O data buffer 2100 at the same time as being stored in the write block data buffer 2070.

The I / O direct block transfer request stored in the buffer is sent to the I / O bus interface unit 3000.
Sent to That is, the address 2090 is stored in the selectors 2160, 3110
After being set in the I / O bus transmission registers 3090 and 3080 via the I / O bus 1500, it is transmitted to the I / O bus 1500. The block data stored in the I / O data buffer 2100 also passes through the I / O bus transmission registers 3090,
After being set to 3080, it is transmitted to the I / O bus 1500. At this time, unlike the first embodiment, the system controller
At 200, the process of converting the access address to the main memory into the address to the I / O device by the address conversion unit 2110 is not performed.

FIG. 6 shows the internal configuration of the I / O control device, taking the file control device 600 as an example. I
The I / O direct block transfer request issued to the / O bus 1500 is received by all I / O devices. File control unit 60
At 0, it is received by the I / O bus reception register 641 and the I / O bus associated information register 640. The address received here is still the main memory address. The address conversion unit 610 converts a main memory address into an I / O device address. The upper limit address register 605 and the lower limit address register 606 store the I
The range of the main memory address to be subjected to the / O direct block transfer can be registered. The address conversion control unit 604 identifies whether the target I / O bus access request is an I / O direct block transfer from the contents of the I / O associated information buffer 640. If the request is an I / O direct block transfer request, the upper limit address register 605, the lower limit address register 606, and the range verification logic 607 are used to verify whether the received access request is for the file control device. When the file control device is targeted, the selector 609 is controlled to select the registered address 608 of the I / O device. The generated address is processed as a data transfer request to the I / O device.

[0055]

According to the present invention, an address translation mechanism is added to the block transfer function of the cache memory of the processor so that block data can be directly transferred from the processor to the I / O device. In this data transfer, it is possible to achieve both high responsiveness and high data transfer throughput. In addition, a plurality of computers are
In a cluster computer system connected by an O bus or a high-speed network, it is possible to achieve both high responsiveness and high data transfer throughput as communication means during a calculation period. Further, in a graphics display I / O system, an I / O
In / O data transfer, both high data transfer throughput and high responsiveness can be achieved.

[Brief description of the drawings]

FIG. 1 is an internal configuration diagram of a system control device of a computer system according to an embodiment of the present invention.

FIG. 2 is an overall configuration diagram of a computer system according to an embodiment of the present invention.

FIG. 3 is an internal configuration diagram of the processor shown in FIG. 2;

FIG. 4 is a configuration diagram of an address translation mechanism in the system control device shown in FIG. 2;

FIG. 5 is another configuration diagram of the address translation mechanism.

FIG. 6 is an internal configuration diagram of the file control device.

[Explanation of symbols]

100: Processor, 105, 106: Cache memory, 200: System controller, 300: Main memory, 4
00, 500, 600, 700... I / O device, 2110
... address translation mechanism.

Claims (11)

(57) [Claims] 1. A plurality of processor devices having a built-in cache memory, a main storage device for storing instructions and data to be executed by the processor devices, and an I / O device such as the processor device and a file system or a network system. A plurality of I / O control devices for controlling communication of the plurality of processors, the plurality of processor devices, the main storage device, and the plurality of I / O controllers.
In a computer system comprising a system controller connected to a / O control device via a bus and controlling data transfer between the devices, a block data registered in the cache memory is forcibly transmitted by an instruction executed by the processor device. A block data transfer command to be transferred to both the main storage device and the I / O control device, and the system control device includes an identification means for identifying a transaction of the block transfer command sent by the processor device. And a function of transmitting the transaction received according to the result of the identification means to both the main storage device and the I / O control device, and converting the address of the transaction into an address to the I / O control device. A computer system characterized by comprising an address translation mechanism. 2. A plurality of processor devices having a built-in cache memory, a main storage device for storing instructions and data to be executed by the processor devices, and an I / O device such as the processor device and a file system or a network system. A plurality of I / O control devices for controlling communication of the plurality of processors, the plurality of processor devices, the main storage device, and the plurality of I / O controllers.
A system controller connected to the I / O controller via a bus and controlling data transfer between the devices; and a system controller connected to the system controller and connected to another computer system via an inter-computer I / O bus or a high-speed network. In a cluster computer system including an inter-computer communication control device, a block data registered on the cache memory is forcibly transmitted to both the main storage device and the inter-computer communication control device by an instruction executed by the processor device. A block data transfer command for transferring the block transfer command, and the system control device includes identification means for identifying a transaction of the block transfer command sent from the processor device. The data is transmitted to both the main storage device and the inter-computer communication control device. An address conversion mechanism for converting the address of the transaction into an address for the inter-computer communication control device, wherein the inter-computer communication control device stores the block data received from the system control device in the A computer system having a mechanism for transmitting data to another computer system via an inter-computer I / O bus or a high-speed network. 3. A plurality of processor devices having a built-in cache memory, a main storage device for storing instructions and data executed by the processor devices, and an I / O device such as the processor device and a file system or a network system. A plurality of I / O control devices for controlling communication of the plurality of processors, the plurality of processor devices, the main storage device, and the plurality of I / O controllers.
A system control device connected to the I / O control device via a bus to control data transfer between the devices, a graphics control device connected to the system control device and controlling a graphics display system, and the graphics control device In a computer system including a frame memory that stores display data and a display device that displays the contents of the frame memory, a block data registered on the cache memory is executed by an instruction executed by the processor device. A block data transfer command for forcibly transferring the data to both the main storage device and the graphics control device; and the system control device includes: identification means for identifying a transaction of the block transfer command transmitted from the processor device. Before receiving according to the result of the identification means. A function of transmitting a transaction to both the main storage device and the graphics control device is provided, and an address conversion mechanism for converting an address of the transaction to an address to the graphics control device is provided, wherein the graphics control device has And a means for writing the block data received from the system control device into the frame memory. 4. The address translation mechanism according to claim 1, wherein said address translation mechanism comprises an address match verification tag section comprising a plurality of entries, and an I / O device corresponding to said address match verification tag section. An address registration unit, a comparator for comparing the received address with the address match verification tag unit, and the I / O device address registration unit for the entry whose address match verification tag unit matched according to the result of the comparator. A computer system, comprising: a mechanism for performing address conversion by using the computer system. 5. A plurality of processor devices having a built-in cache memory, a main storage device for storing instructions and data executed by the processor devices, and an I / O device such as a processor device, a file system, and a network system. A plurality of I / O control devices for controlling communication of the plurality of processors, the plurality of processor devices, the main storage device, and the plurality of I / O controllers.
In a computer system comprising a system controller connected to a / O control device via a bus and controlling data transfer between the devices, a block data registered in the cache memory is forcibly transmitted by an instruction executed by the processor device. A block data transfer command to be transferred to both the main storage device and the I / O control device, and the system control device includes an identification means for identifying a transaction of the block transfer command sent by the processor device. A function of transmitting the transaction received in accordance with the result of the identification means to both the main storage device and the I / O control device. The I / O control device stores the address of the received transaction in the I / O control device. Own I
Means for identifying whether or not the address is to the / O control device;
A computer system having an address conversion function for converting a block transfer request to its own I / O control device to an address of a corresponding I / O control device. 6. The I / O control device according to claim 5, wherein the I / O control device includes a register for holding an upper limit value and a lower limit value of an address to be accepted by the self-control device, and an I / O control device for determining whether the arriving address is the upper limit register and the lower limit register. A computer system comprising: a function of verifying whether or not an address is within a range; and a mechanism for converting the arrival address into an address of the I / O control device according to a result of the verification function. 7. The block data transfer command for forcibly transferring data to both the main storage device and the I / O control device according to claim 1, A computer system for transferring data to an O control device. 8. A processor device having a built-in cache memory, a main storage device storing instructions and data executed by the processor device, and a processor device and an I / O device such as a file system and a network system. A plurality of I / O control devices for controlling communication, and a system control device connected to the processor device, the main storage device, and the plurality of I / O control devices via a bus and controlling data transfer between the devices. In the high-speed I / O data transfer method for a computer system, the processor device forcibly transfers block data registered in the cache memory to both the main storage device and the I / O control device. When a data transfer instruction is issued,
The system control device identifies a transaction of the block transfer instruction sent by the processor device,
Transmitting the transaction received in accordance with the identification result to both the main storage device and the I / O control device, and converting an address of the transaction into an address for the I / O control device. I /
O Data transfer method. 9. A processor device having a built-in cache memory, a main storage device for storing instructions and data executed by the processor device, and communication between the processor device and an I / O device such as a file system or a network system. A plurality of I / O control devices for controlling data transfer, a system control device connected to the processor device, the main storage device, and the plurality of I / O control devices via a bus to control data transfer between the devices; In a high-speed I / O data transfer method for a cluster computer system which is connected to a system control device and comprises an inter-computer communication control device connected to another computer system via an inter-computer I / O bus or a high-speed network, the processor device includes: The block data registered on the cache memory is forcibly stored in the main storage device and the computer. When issuing a block data transfer command to be transferred to both of the inter-communication control devices, the system control device identifies the transaction of the block transfer command transmitted by the processor device, and receives the transaction according to the identification result. Is transmitted to both the main storage device and the inter-computer communication control device, and the address of the transaction is converted into an address to the inter-computer communication control device, and the inter-computer communication control device is A high-speed I / O data transfer method, wherein the received block data is transmitted to another computer system via the inter-computer I / O bus or a high-speed network. 10. A processor device having a built-in cache memory, a main storage device for storing instructions and data executed by the processor device, and communication between the processor device and an I / O device such as a file system or a network system. A plurality of I / O control devices for controlling data transfer, a system control device connected to the processor device, the main storage device, and the plurality of I / O control devices via a bus to control data transfer between the devices; A graphics controller connected to the system controller and controlling the graphics display system, and connected to the graphics controller;
In a high-speed I / O data transfer method for a computer system including a frame memory for storing display data and a display device for displaying the contents of the frame memory, the processor device forcibly deletes block data registered in the cache memory. Issue a block data transfer command to transfer to both the main storage device and the graphics control device, the system control device identifies the transaction of the block transfer command sent by the processor device, While transmitting the transaction received according to the identification result to both the main storage device and the graphics control device, and converting the address of the transaction to an address to the graphics control device, the graphics control device, From the system controller Only the block data taken, high-speed and writes in the frame memory I /
O Data transfer method. 11. A processor device having a built-in cache memory, a main storage device for storing instructions and data to be executed by the processor device, and communication between the processor device and an I / O device such as a file system or a network system. Computer comprising: a plurality of I / O control devices for controlling data transfer; and a system control device connected to the processor device, the main storage device, and the plurality of I / O control devices via a bus and controlling data transfer between the devices. In the system, the processor device forcibly stores the block data registered on the cache memory into the main storage device and the I / O device.
When issuing a block data transfer command to be transferred to both the I / O control device, the system control device identifies the transaction of the block transfer command sent from the processor device, and receives the transaction according to the identification result. Is transmitted to both the main storage device and the I / O control device, and the I / O control device identifies whether the received address of the transaction is an address to the own I / O control device, and A high-speed I / O characterized by converting a block transfer request to an I / O control device to an address of a corresponding I / O control device.
Data transfer method.