JP2712606B2 - Initialization processing method for multi-CPU system - Google Patents

Description

The present invention relates to a method of setting control parameters of a slave CPU during initialization processing in a master / slave type multi-CPU (central processing unit) configuration system. .

B. Summary of the Invention In the present invention, in a processing system of a master / slave type multi-CPU configuration, a RAM with a power failure protection function is used as a main memory instead of an external storage device or a ROM, and this RAM is used for a slave CPU. After allocating the data area and assigning the control parameters stored in this data area in advance to the power supply, the master CPU
Transfer to

In order to determine the validity of the data transfer and to determine the timing of the transition to the main processing of the slave CPU, the RAM of the slave CPU is assumed to be accessible to both the master and slave CPUs. The last part of the area is data of a specific pattern.

That is, the master CPU transfers the data from the data area of the main memory to the RAM of the slave CPU after turning on the power, and then transfers the data when the last part of the data transferred to the RAM of the slave CPU has a specific pattern. Is correct, the initialization process is completed, and the process proceeds to the main process.
If it is not the specific pattern, there is an error in the data transfer, so that error processing such as setting an error flag is performed, the initialization processing is completed, and the processing shifts to the main processing.

After turning on the power, the slave CPU clears the area to which the specific pattern is transferred from its own RAM, and then when the data in this area becomes the specific pattern, the control parameters are set correctly and the initialization process ends. Then, the processing shifts to the main processing.

C. Conventional technology In a master / slave-type multi-CPU system, it is necessary to set data such as control parameters necessary for the operation of the slave CPU in addition to resetting analog output and resetting digital display during initialization processing. Conventionally, the following method (1) or (2) has been adopted. The control parameter is, for example, data such as a gain of a control system and an engineering conversion constant of a physical quantity.

(1) Various data of control parameters are stored in an external storage device such as a magnetic disk, and the master
The CPU retrieves data from the external storage device, and the slave CPU
To transfer the data to a random access memory (RAM). In this case, the timing between the data transfer to the slave CPU after the power is turned on and the main processing of the slave CPU itself is determined by setting a time in advance by a timer.

(2) ROM (read-only memory) of the slave CPU itself
A method in which data is written in the ROM and the slave CPU retrieves the data from this ROM.

D. Problems to be Solved by the Invention First, in the conventional method (1) in which the master CPU transfers control parameters to the RAM of the slave CPU, an external storage device such as a magnetic disk is required, and a timer is used. Therefore, there is a disadvantage that the timing of data transfer to the slave CPU and the timing of the main processing of the slave CPU may not be synchronized.

Further, the conventional method (2) using a ROM has a disadvantage that the ROM needs to be converted every time a control parameter is changed.

An object of the present invention is to provide an initialization processing method which has solved the above-mentioned disadvantages of the prior art.

E. Means for Solving the Problems The initialization processing method according to the present invention uses a master / slave type multi-CPU processing system in which a RAM having a power failure protection function is used as a main memory and a slave C
RA that allows both master and slave CPUs to access PU RAM
M, a data area for the slave CPU is allocated to the RAM of the main memory, and data having a specific pattern at the end is stored in this data area. Transfer data from the area to the RAM of the slave CPU, and then determine whether or not the last part of the data transferred to the RAM of the slave CPU is the specific pattern; if it is the specific pattern, shift to main processing; If it is not a specific pattern, after error processing, it shifts to main processing.After turning on the power, the slave CPU clears the area to which the specific pattern is transferred in its own RAM, and then specifies the data in this area. The method is characterized in that the process waits until a pattern is formed, and shifts to a main process when a specific pattern is formed.

F. Operation In the above configuration, the main memory using the RAM with the power failure protection function replaces the conventional external storage device or ROM, and after the power is turned on, the master CPU transfers the control parameters and the like from the main memory to the RAM of the slave CPU. Initialization processing is performed by transferring data. In this case, since the RAM of the main memory is provided with a power failure protection function, data is retained even after a power failure, and data can be freely changed unlike ROM.

Then, the RAM of the slave CPU is used for both the master and slave CPUs.
Can be accessed, and the data and
The validity of the data transfer is determined by setting the last part of the area as the data of the specific pattern, and the timing of transition to the main processing of the slave CPU is taken.

In other words, after data transfer, the master CPU
When M is accessed and the last part of the transferred data is a specific pattern, the data transfer is correct, so that the initialization processing is completed and the processing shifts to the main processing. If it is not the specific pattern, there is an error in the data transfer, so that error processing such as setting an error flag is performed, the initialization processing is completed, and the processing shifts to the main processing.

After turning on the power, the slave CPU clears the area to which a specific pattern is transferred in its own RAM to check the pattern.After that, when the data in this area becomes a specific pattern, the control parameters are set correctly. It is assumed that the initialization processing has been completed, and the processing shifts to the main processing. Thus, the data transfer and the main processing of the slave CPU are executed with good timing.

G. Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a flow of the initialization processing,
FIG. 2 shows a configuration of a multi-CPU system, and FIG. 3 shows a memory configuration.

As shown in FIG. 2, in the system of this embodiment, one main memory board 2, one master CPU board 4, and N slave CPU boards 7-1 to -1 are provided by the multibus 1.
7-N.

The main memory board 2 has a RAM 3 with a battery backup for power failure protection, and this RAM 3 is used for storing and updating data such as control parameters.

The master CPU board 4 has a master CPU (master CP
U) and its associated RAM5 and ROM6, the master CPU
Manages N slave CPUs.

If i = 1 to N, the slave CPU board 7-
i has a slave CPU #i and an associated RAM 8-i and ROM 9-i.

Each of the RAMs 8-i is one that can be accessed by both the master CPU and the slave CPU #i, for example, a RAM called a two-port memory or a dual-port memory. The same is used for RAM5. However, these
The RAMs 5, 8-i are not provided with a power failure protection function.

RAM3 of main memory board 2, RAM5,8- of each CPU board
i and ROM6, 8-i are appropriate semiconductor memories.

As shown in FIG. 3, the RAM 3 of the main memory board 2 has
Data area # 0 for master CPU and each master C
A data area #i (i = 1 to N) is assigned to the PU #i, and data such as control parameters required for each CPU is stored in the corresponding data area in advance.

However, the data of the last part is stored in a specific pattern, such as adding data of a specific pattern to each data area of the RAM 3. Also, each slave CPU @ i
The specific pattern at the end of the data is transferred to the last area of the RAM 8-i.

Next, the initialization process will be described with reference to FIG. After turning on the power, the master CPU initializes such as turning off the digital display, setting the analog output to zero, and transferring data from the data area # 0 of RAM3 of the main memory to its own RAM5 (Fig. 1, symbol After performing 11), the data to be set in each slave CPU #i is taken out from the corresponding data area #i of the main memory, and each slave CPU #i
(FIG. 1, symbol 12).

After the data transfer, the master CPU
-I, reads the data of the last area (symbol 13 in FIG. 1), and checks whether or not the read data matches the specific pattern (symbol 1 in FIG. 1).
Four). If they match, it is determined that the data transfer has been performed correctly, the control parameters and the like have been set securely, the initialization is completed, and the process moves to the next main processing of the master CPU itself (symbol 16 in FIG. 1). . If they do not match, the data transfer has not been performed correctly, so that error processing, for example, air information (error flag) for the corresponding slave CPU is set, initialization is terminated, and the process proceeds to the main processing (FIG. 1). , Symbols 15, 16).

On the other hand, after the power is turned on, each slave CPU #i firstly resets the contents of the last area of the RAMs 8-i to which the data of the specific pattern is transferred from the master CPU to zero (FIG. 1, symbol 21). ). Next, data is read from the last area, compared with the specific pattern, and waits for a match (FIG. 1, symbols 22, 23). If they match,
It is assumed that the setting of the control parameters and the like in the initialization has been securely performed, and the slave CPU #i shifts to its own main process (symbol 24 in FIG. 1), and calculates the torque control using the set data. Performs engineering conversion of physical quantities.

When the control parameters need to be changed during the control, there are two methods, a temporary method and a final method.
In the temporary method, while the control is stopped, the data in the RAM 8-i of the slave CPU #i to be changed is directly changed from the outside, and the control is restarted. In the final method, the data of the desired data area #i of the RAM 3 of the main memory board 2 is externally changed, and the system restart processing is performed to change the data of the desired slave CPU #i.

H. Effects of the Invention According to the present invention, the following effects are obtained.

(1) Since the RAM with the power failure protection function is used as the main memory, the data is stored even after the power failure, so that the initialization process can be easily performed.

(2) Since RAM is used for both the main memory and the slave CPU, data can be freely changed by rewriting any of the RAMs.

(3) Since the master CPU can access the RAM of the slave CPU, it is easy to check the data transferred to the slave CPU.

(4) After the power is turned on, the master CPU checks whether or not the data setting of the slave CPU has been securely performed, and then shifts to the main processing for the first time. Further, after turning on the power, the slave CPU confirms that the data setting has been securely performed from the master CPU, and then shifts to the main processing for the first time. Thereby, the timing between the data transfer and the main processing can be automatically and reliably taken.

[Brief description of the drawings]

FIG. 1 is a diagram showing a flow of an initialization process according to an embodiment of the present invention, FIG. 2 is a diagram showing a system configuration, and FIG.
The figure shows the memory configuration. In the drawing, 1 is a multi-bus, 2 is a main memory board, 3 is a battery
RAM with backup, 4 is master CPU board, 7-1
7-N are slave CPU boards, and 8-1 to 8-N are R
AM.

Claims (1)

(57) [Claims] A processing system having a master / slave type multi-CPU configuration, wherein a RAM with a power failure protection function is used as a main memory, and a slave CPU is provided.
RAM that can be accessed by both master and slave CPUs
A data area for the slave CPU is allocated to the RAM of the main memory, and data having a specific pattern at the end is stored in this data area. Transfer data from the area to the RAM of the slave CPU, and then
It is determined whether or not the last part of the data transferred to the RAM of the slave CPU is the specific pattern.If it is the specific pattern, the process proceeds to the main process. After turning on the power, the slave CPU clears an area of its own RAM to which the specific pattern is transferred, and thereafter,
Wait until the data in this area becomes a specific pattern,
A multi-CPU system initialization processing method characterized by shifting to main processing when a specific pattern is reached.