JP2692344B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JP2692344B2
JP2692344B2 JP2159123A JP15912390A JP2692344B2 JP 2692344 B2 JP2692344 B2 JP 2692344B2 JP 2159123 A JP2159123 A JP 2159123A JP 15912390 A JP15912390 A JP 15912390A JP 2692344 B2 JP2692344 B2 JP 2692344B2
Authority
JP
Japan
Prior art keywords
bump
bumps
film
semiconductor device
side wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2159123A
Other languages
Japanese (ja)
Other versions
JPH0453138A (en
Inventor
龍一 岡村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2159123A priority Critical patent/JP2692344B2/en
Publication of JPH0453138A publication Critical patent/JPH0453138A/en
Application granted granted Critical
Publication of JP2692344B2 publication Critical patent/JP2692344B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125Reinforcing structures
    • H01L2224/10126Bump collar

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置およびその製造方法に関し、特に
垂直な側壁を持つバンプを有する半導体装置およびその
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having bumps with vertical sidewalls and a method for manufacturing the same.

〔従来の技術〕[Conventional technology]

従来の垂直な側壁を有するバンプが設けられた半導体
装置の製造方法について図面を用いて説明する。
A conventional method for manufacturing a semiconductor device provided with bumps having vertical sidewalls will be described with reference to the drawings.

まず第3図(a)に示すように、素子及びメッキ用電
流路が形成された半導体基板1上に厚さ15〜20μmのフ
ォトレジストを塗布したのちパターニングし、開口部を
有するマスク2を形成する。次でメッキ法により、金や
銅等のメッキを行ない開口部内にバンプ3を形成する。
バンプ3は、マスク2の厚さ以下の厚さに形成すること
により、垂直な側壁を持った形状に形成される。
First, as shown in FIG. 3 (a), a photoresist having a thickness of 15 to 20 μm is applied on a semiconductor substrate 1 on which an element and a current path for plating are formed and then patterned to form a mask 2 having an opening. To do. Next, gold or copper is plated by a plating method to form the bumps 3 in the openings.
The bumps 3 are formed to have a vertical side wall by forming the bumps 3 to have a thickness equal to or smaller than that of the mask 2.

次に第3図(b)に示すように、マスク2を剥離した
のち全面にカバー膜4を形成する。このカバー膜4は、
例えばポリイミド等の有機系、あるいは酸化シリコン膜
や窒化シリコン膜等の無機膜であってもよい。次でこの
カバー膜4上にフォトレジスト膜5Aを形成する。
Next, as shown in FIG. 3B, the mask 2 is peeled off, and then the cover film 4 is formed on the entire surface. This cover film 4 is
For example, it may be an organic film such as polyimide or an inorganic film such as a silicon oxide film or a silicon nitride film. Next, a photoresist film 5A is formed on the cover film 4.

次に第3図(c)に示すように、バンプ3上のフォト
レジスト膜5Aをパターニングしたのち、このフォトレジ
スト膜5Aをマスクとしてカバー膜4をエッチングする。
カバー膜4がポリイミド等の有機膜の場合は、フォトレ
ジスト膜は環化ゴム系のネガタイプを用い、ヒドラジン
とエチレンジアミンの混合液でエッチングするのが一般
的である。このネガタイプのフォトレジスト膜を用いる
場合は、寸法精度及び目合せ精度が良くないため、バン
プ3の表面にカバー膜4をエッチングし、バンプ3の表
面にカバー膜4が残るのを防ぐ必要がある。
Next, as shown in FIG. 3C, after patterning the photoresist film 5A on the bumps 3, the cover film 4 is etched using the photoresist film 5A as a mask.
When the cover film 4 is an organic film such as polyimide, the photoresist film is generally a cyclized rubber-based negative type, and is generally etched with a mixed solution of hydrazine and ethylenediamine. When this negative type photoresist film is used, since the dimensional accuracy and the alignment accuracy are not good, it is necessary to etch the cover film 4 on the surface of the bump 3 to prevent the cover film 4 from remaining on the surface of the bump 3. .

次で第3図(d)に示すように、フォトレジスト膜5A
を剥離して除去する。
Next, as shown in FIG. 3D, the photoresist film 5A
Peel off and remove.

このようにして形成されたバンプ3にTABテープのイ
ンナーリード10をボンディングした場合は第4図に示す
ように、バンプ3はつぶれて横方向に広がる。尚、バン
プ3を形成後、カバー膜4を設けない場合もある。
When the inner leads 10 of the TAB tape are bonded to the bumps 3 thus formed, the bumps 3 are crushed and spread laterally as shown in FIG. The cover film 4 may not be provided after the bumps 3 are formed.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

最近の半導体装置は高集積化に伴ない、入出力パッド
数が増加し、バンプ形状も側壁が垂直なバンプを用いて
パッドサイズの微細化及びパッドピッチの縮小化が行わ
れているが、従来の半導体装置のバンプは、カバー膜を
形成しないか、あるいは形成されていても垂直な側壁を
持つバンプの側壁部には形成されていなかったために、
インナーリードボンディング(以下ILBと記す)時のバ
ンプの広がりにより、バンプ間のショートの危険があ
る。このためバンプ間隔を大きくとる必要があるため、
パッドピッチの縮小が困難であり、半導体装置の高集積
化の妨げとなっていた。
In recent semiconductor devices, the number of input / output pads has increased along with higher integration, and the bump shape has also been made smaller by reducing the pad size and the pad pitch by using bumps with vertical sidewalls. The bump of the semiconductor device of No. 1 does not have the cover film formed, or even if it is formed, it is not formed on the side wall portion of the bump having the vertical side wall.
There is a risk of shorts between bumps due to the spread of the bumps during inner lead bonding (hereinafter referred to as ILB). Therefore, it is necessary to set a large bump interval,
It is difficult to reduce the pad pitch, which hinders high integration of semiconductor devices.

〔課題を解決するための手段〕[Means for solving the problem]

第1の発明の半導体装置は、半導体基板上に形成され
た垂直な側壁を有するバンプを備えた半導体装置におい
て、前記半導体装置表面及び前記バンプの側壁部に連続
した同じ厚さの絶縁脂を側壁の途中まで形成したもので
ある。
A semiconductor device according to a first aspect of the present invention is a semiconductor device including a bump having a vertical side wall formed on a semiconductor substrate, wherein an insulating resin having the same thickness is continuously formed on the semiconductor device surface and the side wall portion of the bump. It was formed part way through.

第2の発明の半導体装置の製造方法は、半導体基板上
にメッキ法により、側面全体が垂直な側壁を有するバン
プを形成する工程と、前記バンプを含む全面に絶縁性の
有機膜を形成する工程と、前記有機膜をパターニングし
バンプの上面及び一部側壁を露出する工程とを含んで構
成される。
A method of manufacturing a semiconductor device according to a second aspect of the present invention includes a step of forming a bump having side walls whose entire side surfaces are vertical on a semiconductor substrate by a plating method, and a step of forming an insulating organic film on the entire surface including the bump. And a step of patterning the organic film to expose upper surfaces and a part of sidewalls of the bumps.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明す
る。
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)〜(d)は本発明の第1の実施例を説明
するための半導体チップの断面図である。
FIGS. 1A to 1D are sectional views of a semiconductor chip for explaining the first embodiment of the present invention.

まず第1図(a)に示すように、従来と同様にして、
素子及びメッキ用電流路が形成された半導体基板1上に
厚さ15〜20μmのフォトレジスト膜を形成し、パターニ
ングしてマスク2を形成する。次で金,銅等のメッキを
行ない、垂直な側壁を有するバンプ3を形成する。
First, as shown in FIG.
A photoresist film having a thickness of 15 to 20 μm is formed on the semiconductor substrate 1 on which the elements and the current path for plating are formed, and patterned to form the mask 2. Next, gold, copper or the like is plated to form bumps 3 having vertical side walls.

次に第1図(b)に示すように、バンプ3を含む全面
にポリイミド等の有機溶液を回転塗布法により塗布し、
130〜150℃,30〜60分間の熱処理を行ないカバー膜4を
形成する。この時のポリイミド膜のイミド化率は5〜30
%となり、アルカリ溶液に可溶となる。次でこのカバー
膜上にポジ型のフォトレジスト膜5を形成する。
Next, as shown in FIG. 1 (b), an organic solution such as polyimide is applied to the entire surface including the bumps 3 by spin coating,
Heat treatment is performed at 130 to 150 ° C. for 30 to 60 minutes to form the cover film 4. At this time, the imidization ratio of the polyimide film is 5 to 30.
% And becomes soluble in an alkaline solution. Next, a positive photoresist film 5 is formed on this cover film.

次に第1図(c)に示すように、バンプ3の形成時に
用いたパターンと同一形状のパターンを有するマスクを
用いて露光したのち、ポジ型レジストの現像液として、
例えばテトラメチルアンモニウムハイドライド(T.M.A.
H)の2〜3%の水溶液を用い、150〜300秒間現像を行
なう。この時、フォトレジスト膜5のパターニングと同
時に、ポリイミドからなるカバー膜4もパターニングさ
れ、更にカバー膜4は現像液によりサイドエッチングさ
れてバンプ3の垂直な壁の途中までエッチングされる。
Next, as shown in FIG. 1 (c), after exposing using a mask having a pattern having the same shape as the pattern used when forming the bumps 3, as a developer for a positive resist,
For example, tetramethylammonium hydride (TMA
Development is performed for 150 to 300 seconds using a 2-3% aqueous solution of H). At this time, at the same time as the patterning of the photoresist film 5, the cover film 4 made of polyimide is also patterned, and the cover film 4 is side-etched by the developing solution to be etched halfway along the vertical wall of the bump 3.

次に第1図(d)に示すように、メチルエチルケトン
あるいは酢酸ブチル等でフォトレジスト膜5を除去した
のち、250〜300℃、60分間程度の熱処理を行ない、ポリ
イミド膜を完全にイミド化させる。
Next, as shown in FIG. 1 (d), after removing the photoresist film 5 with methyl ethyl ketone, butyl acetate or the like, heat treatment is carried out at 250 to 300 ° C. for about 60 minutes to completely imidize the polyimide film.

このようにして形成された半導体装置のバンプ3に、
TABテープのインナーリード10をボンディングした場合
を第2図に示す。
On the bumps 3 of the semiconductor device thus formed,
FIG. 2 shows a case where the inner lead 10 of the TAB tape is bonded.

インナーリードボンディングでは、30〜60kg/cm2程度
の圧力を加えるが、バンプ3の側壁部及び半導体基板1
上に連続してカバー膜4が形成されているため、バンプ
3のつぶれは小さく、横広がりも少ない。従ってパッド
ピッチを小さくすることができる。
In the inner lead bonding, a pressure of about 30 to 60 kg / cm 2 is applied, but the side wall of the bump 3 and the semiconductor substrate 1
Since the cover film 4 is continuously formed on the upper side, the bumps 3 are less crushed and less laterally spread. Therefore, the pad pitch can be reduced.

〔発明の効果〕〔The invention's effect〕

以上説明した様に本発明は、半導体基板表面及び垂直
な側壁を持つバンプの側壁部に連続したほぼ同程度の厚
さのカバー膜を側壁の途中まで形成することにより、イ
ンナーリードボンディング時のバンプのつぶれや横広が
りを抑制できるため、パッドサイズの微細化及びパッド
ピッチの縮小を図ることができる。このため、集積度の
より向上した半導体装置が得られるという効果がある。
As described above, according to the present invention, by forming a cover film having substantially the same thickness and continuous on the side wall portion of a bump having a semiconductor substrate surface and a vertical side wall up to the middle of the side wall, bumps for inner lead bonding are formed. Since it is possible to suppress the collapse and lateral spread of the pad, it is possible to reduce the pad size and the pad pitch. Therefore, there is an effect that a semiconductor device having a higher degree of integration can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(d)は本発明の第1の実施例を説明す
るための半導体チップの断面図、第2図は実施例により
形成されたバンプにインナーリードをボンディングした
場合の断面図、第3図(a)〜(d)は従来例を説明す
るための半導体チップの断面図、第4図は従来例のバン
プにインナーリードをボンディングした場合の断面図で
ある。 1…半導体基板、2…マスク、3…バンプ、4…カバー
膜、5,5A…フォトレジスト膜、10…インナーリード。
1 (a) to 1 (d) are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention, and FIG. 2 is a cross-section when an inner lead is bonded to a bump formed by the embodiment. FIGS. 3A to 3D are sectional views of a semiconductor chip for explaining a conventional example, and FIG. 4 is a sectional view of a conventional example in which an inner lead is bonded to a bump. 1 ... Semiconductor substrate, 2 ... Mask, 3 ... Bump, 4 ... Cover film, 5,5A ... Photoresist film, 10 ... Inner leads.

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板上に形成された垂直な側壁を有
するバンプを備えた半導体装置において、前記基板表面
と前記バンプの側壁の途中迄同じ厚さの絶縁膜を形成し
たことを特徴とする半導体装置。
1. A semiconductor device having a bump having a vertical side wall formed on a semiconductor substrate, wherein an insulating film having the same thickness is formed halfway between the substrate surface and the side wall of the bump. Semiconductor device.
【請求項2】半導体基板上にメッキ法により、側面全体
が垂直な側壁を有するバンプを形成する工程と、前記バ
ンプを含む全面に絶縁性の有機膜を形成する工程と、前
記有機膜をパターニングしバンプの上面及び側壁の上部
を露出する工程とを含むことを特徴とする半導体装置の
製造方法。
2. A step of forming on a semiconductor substrate a bump having a side wall whose entire side surface is vertical, a step of forming an insulating organic film on the entire surface including the bump, and patterning of the organic film. And a step of exposing the upper surface of the bump and the upper portion of the side wall of the bump.
JP2159123A 1990-06-18 1990-06-18 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2692344B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2159123A JP2692344B2 (en) 1990-06-18 1990-06-18 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2159123A JP2692344B2 (en) 1990-06-18 1990-06-18 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0453138A JPH0453138A (en) 1992-02-20
JP2692344B2 true JP2692344B2 (en) 1997-12-17

Family

ID=15686740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2159123A Expired - Fee Related JP2692344B2 (en) 1990-06-18 1990-06-18 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2692344B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3383329B2 (en) 1992-08-27 2003-03-04 株式会社東芝 Method for manufacturing semiconductor device
US6042953A (en) * 1996-03-21 2000-03-28 Matsushita Electric Industrial Co., Ltd. Substrate on which bumps are formed and method of forming the same
US7137775B2 (en) 2003-03-20 2006-11-21 Huntair Inc. Fan array fan section in air-handling systems

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58143554A (en) * 1982-02-22 1983-08-26 Nippon Denso Co Ltd Manufacture of semiconductor device
JPS6336548A (en) * 1986-07-31 1988-02-17 Nec Corp Semiconductor device and manufacture thereof
JPS6412553A (en) * 1987-07-07 1989-01-17 Nec Corp Manufacture of semiconductor device
JPH0228932A (en) * 1988-07-19 1990-01-31 Fujitsu Ltd Semiconductor device

Also Published As

Publication number Publication date
JPH0453138A (en) 1992-02-20

Similar Documents

Publication Publication Date Title
JP3630777B2 (en) Multi-chip module manufacturing method
KR100389314B1 (en) Making method of PCB
JPH03148856A (en) Manufacture of lead frame
JPS63104425A (en) Method of forming via-hole
JP2692344B2 (en) Semiconductor device and manufacturing method thereof
JP2861841B2 (en) Lead frame manufacturing method
JP2597396B2 (en) Method of forming pattern of silicone rubber film
JP3916348B2 (en) Semiconductor device and manufacturing method thereof
JP2003218151A (en) Method for forming electroless plated bump, semiconductor device, and its manufacturing method
US7772699B2 (en) Semiconductor device and method of manufacturing the same
JPH03198342A (en) Manufacture of semiconductor device
JP4161754B2 (en) Manufacturing method of semiconductor device
JP2001332577A (en) Method of manufacturing semiconductor device
JP3526529B2 (en) Method for manufacturing semiconductor device
JP3036086B2 (en) Method for manufacturing semiconductor device
JPS6179261A (en) Manufacture of semiconductor device
JP2992171B2 (en) Method for manufacturing semiconductor device
JPS605543A (en) Manufacture of semiconductor device
JPH04250628A (en) Manufacture of semiconductor device
JPS5843520A (en) Semiconductor device
JPH05121617A (en) Manufacture of lead frame
KR19980026851A (en) Separation Device Separation Method
JPS63122125A (en) Manufacture of semiconductor device
JPS58122750A (en) Preparation of semiconductor device
JPS59104125A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees