JP2690745B2 - Image processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to image display control for displaying a plurality of images in display priority order.

[Prior Art] For example, when displaying a first screen displaying mountains and a second screen displaying clouds and the sun, for example, when displaying the first screen, The first screen displayed on the front side has the second screen displayed on the color CRT simultaneously as the second screen displayed on the back side of the first screen. There are times when you want to obtain an image that will be lost.

In the above example, one of the two screens is preferentially displayed, but there may be a case where three or more screens are weighted and displayed on the color CRT.

As a device that selects screens in this order of priority,
Conventionally, a circuit as shown in FIG. 6 has been used. Sixth
In the figure, while inputting the image data of the two screens SC1 and SC2 to the switches 101 and 102, turning on or off the switches 101 and 102 with a signal indicating the priority order outputs the image data of the higher priority order. It is adapted to be obtained at the terminal 104. Incidentally, 103 is an inverter.

[Problems to be Solved by the Invention] In this conventional circuit, only two screens can be prioritized, and there is a problem that control is complicated to display in order of priority on three or more screens. there were.

An object of the present invention is to solve the above-mentioned problems and to provide an image processing apparatus which can obtain a desired screen with relatively simple control even when three or more screens are displayed in a predetermined priority order.

[Means for Solving the Problems] In order to achieve the above-mentioned object, an image processing apparatus according to the present invention is turned on based on on / off data input for each of a plurality of input image data. And output the corresponding image data input as it is, while outputting the image data that is transparent data instead of the corresponding image data input when it is OFF, and for each of the plurality of image data Storage means for temporarily storing the display priority setting data, and a plurality of image data output from the selecting means are provided for each screen corresponding to the display priority, the storage means being provided corresponding to the display priority. A plurality of image data stored in the storage element are sequentially read according to the display priority setting data stored in the storage means. Characterized in that a priority circuit for outputting.

[Operation] In the image processing circuit of the present invention, the selection means is
Based on the ON / OFF data input to each of the plurality of input image data, the corresponding image data input when ON is directly output, while the corresponding image data input when OFF is input Instead of this, image data that is transparent data is output. The storage means temporarily stores the display priority setting data for each of the plurality of input image data. On the other hand, as the priority circuit, for example, when there are four screens, first to fourth priority circuits are provided, and a storage element for temporarily storing the image data of each screen from the selection means for each priority circuit. Is provided.

Then, when data indicating that the first screen has the first priority is output from the storage means, the first screen is output.
The priority circuit is designated, the image data of the first screen is read from the storage element for storing the image data of the first screen in the first priority circuit, sent to the image display processing circuit, and displayed on the television screen. . Further, when data indicating the second priority of the second screen is output from the storage means, the second priority circuit is designated and the image data of the second screen of the second priority circuit is stored. Image data is output from the element and sent to the display processing circuit to be displayed on the television screen. further,
When data indicating that the second screen has the third highest priority is output from the storage means, the third priority circuit is designated, and the image data of the third screen of the third priority circuit is stored in the storage element. The image data is output, sent to the display processing circuit, and displayed on the television screen. Finally, when data indicating the fourth priority of the fourth screen is output from the storage means, the fourth priority circuit is designated and the image data of the fourth screen of the fourth priority circuit is stored. Image data is output from the storage element and sent to the display processing circuit and displayed on the television screen.

In this way, the display of the plurality of input image data is turned on or off, and the first screen of the first priority order is apparently displayed on the front of the TV screen.
A second screen of second priority is displayed behind the first screen on the television screen. Similarly, the third and fourth screens are displayed behind the first and second screens in the order of the third screen of the third priority and the fourth priority.

[Embodiment] In the following embodiment, a case will be described in which four screens SC1, SC2, SC3, SC4 are displayed on the CRT screen with a predetermined priority setting as shown in FIG.

In FIG. 1, 1, 2, 3, and 4 are screens SC1 to SC4, respectively.
Is a selector provided corresponding to, and temporarily stores the image data of each screen as dot unit data of the CRT display screen, and selectively outputs data indicating pixels or data indicating transparency. To do.

Reference numerals 10, 20, 30, and 40 are first to fourth priority circuits each using a 3-state buffer memory, and each priority circuit is a buffer memory 11 to 14, 2 corresponding to each screen SC1 to SC4.
1 to 24, 31 to 34, 41 to 44, buffer memory 11, 21, 31,
41 is connected to the output terminal of the selector 1, and similarly, the buffer memories 12, 22, 32 and 42 are connected to the output terminal of the selector 2. Other buffer memory 13,21,33,43,14,24,34,4
Similarly to the above, 4 is connected to the output terminals of the selectors 3 and 4.

A radius circuit 51, 52, 53, 54 for discriminating between image data and transparent data in a display data determination unit is respectively an output terminal of the buffer memories 11 to 44 of the priority circuits 10, 20, 30, 40. Each of the determination circuits 51 to 54 connected thereto outputs 1 when the data output from the respective buffer memories 11 to 44 is image data, and outputs 0 when the data is transparent data.

Reference numerals 61 to 65 denote D-type flip-flops with a 3-state buffer memory (hereinafter referred to as flip-flops), and the respective flip-flops 62 to 64 output data from the respective buffer memories of the first to fourth priority circuits 10 to 40. In response, the image data is sequentially output according to the clock signal and output according to the priority order.

A screen control register 70 controls each priority circuit 10, 20, 30, 40 according to the data indicating the priority output from the priority setting register 80 (see FIG. 3).

The priority setting register 80 has 12 bits D0 to D11 as shown in FIG. 3, and D0 to D3 are screens SC1 to SC4.
The data indicating ON / OFF of the display of
Stores pairs of 2 bits each and stores data indicating the priority of each screen. That is, bits D4 and D5 correspond to the fourth priority (lowest priority), bits D6 and D7 correspond to the third priority, bits D8 and D9 correspond to the second priority, and bits D10 and D11 correspond to the first priority (the highest priority). To do.

On the other hand, codes are assigned to the respective screens SC1, SC2, SC3, SC4 as shown below and in FIG.

 Code 00 for SC1, Code 01 for SC2, Code 10 for SC3, Code 11 for SC4.

Then, for example, when 00 is written in the bits D10 and D11, it indicates that the screen SC1 is displayed in the foreground on the screen of the CRT with the first priority, that is, apparently.

The output terminals 5Q to 8Q and 1Q 'to 4Q' corresponding to the input bits D4 to D11 of the screen control register 70 are 2 to 4 respectively, and the input terminals 1A, 1B, 2A, 2B, 3 of the multiplexers 71, 72 are respectively.
Connected to A, 3B, 4A, 4B and output terminals (multiplexers 71, 7
2 (16 terminals consisting of Y0, Y1, Y2, Y3) control the buffer memories 11 to 14, 21 to 24, 31 to 34, 41 to 44 of the priority circuits 10, 20, 30, and 40, respectively. Connected to the input terminal.

In the above configuration, the priority setting register 80
To screen control register 70 bits D10, D1
When code 01 indicating the second screen SC2 is stored in 1, terminal 4
The data “01” is applied to A and 4B, an H level output is generated at the output terminal Y5 corresponding to the second screen SC2 of the multiplexer 72, and this output is applied to the buffer memory 12 and the image data of the buffer memory 12 is output. Are read with the first priority. The connection relationship between the output terminals of the multiplexers 71 and 72 and the buffer memories 11 to 44 is indicated by 1 to 16 on the signal line in FIG.

Screen control register 70 bits D0 through D3
The output terminals corresponding to are connected to the selection inputs of the selectors 1-4.

In the device having the above configuration, if the data shown in FIG. 4 is set in the screen control register 70 from the priority setting register 80,
Screen SC2 display data in the priority circuit 10, SC3 display data in the second priority circuit 20, transparent data in the third priority circuit 30 (Because bit D0 in the screen control register 70 is data "0", transparent data is Selected), fourth priority circuit
SC4 display data flows to 40.

The respective display data passed through the priority circuits 10, 20, 30, 40 are input to the determination circuits 51-54 and the flip-flops 62-65 shown in FIG. The determination circuits 51 to 54 determine whether the display data that has flowed is color data or transparent data, and input the result to the register 60.

The register 60 determines which priority circuit has data to be displayed in the order of the first priority, the second priority, the third priority, and the fourth priority, and finally, four flip-flops 62 in FIG.
Enable one of ~ 65 and 61. The enabled display data is sent to the display circuit as the display data in FIG.

When all the data from the first priority to the fourth priority is transparent data (for example, when "0" is set in all D0 to D3 of the control register), the flip-flop shown in FIG.
61 is selected by the register 60, and transparent data is sent to the display circuit as display data.

Details of the display data determination circuit 50 shown in FIG. 1 are shown in FIG. FIG. 2 shows an example when the color data and the transparent data are 4 bits.

In the setting of the priority setting register 80 shown in FIG. 4, the image of the second screen SC2 has the highest priority, that is, is displayed on the TV screen in the foreground without being hidden by other screens, and then the third screen. The screen SC3 is displayed in the second priority, that is, immediately after the second screen SC2, and immediately after that, the screen S3 is displayed.
C4 is displayed. Here, the screen SC1 is not displayed.

Now, as shown in FIG. 7, there are display screens SC1 to SC4,
These four display screens SC1 to SC4 are displayed as SC1>SC2> SC3
＞ SC4 priority setting to superimpose (here, SC1> SC
2 indicates that SC1 has a higher display priority than SC2. )
When it is displayed, it becomes as shown in FIG. 8, and the data contents of the priority setting register 80 at this time are shown in FIG.

In this state, set bit D ₀ of priority setting register 80 to 0.
Change to, the screen of SC1 disappears completely from the overlay screen, that is, the display data of screen SC1 is changed to transparent data by switching the selector 1 to the transparent data A side, and the overlay screen of FIG. Like The data contents of the priority setting register 80 at this time are shown in FIG. That is, each bit of D _{0 to} D ₃ of the priority setting register 80 is turned on for each display screen of SC1, SC2, SC3, SC4.
It is a bit for controlling the OFF, and all the display screen data corresponding to the bit in which the data “0” is set changes to a transparent code, and as a result, it is not displayed (display OFF).

[Effects of the Invention] As described in detail above, according to the image processing device of the present invention, when the image processing device is ON based on the ON / OFF data input to each of the plurality of input image data. Selecting means for outputting the image data that is transparent data instead of the corresponding image data that is input when the input corresponding image data is output as it is, and a display priority for each of the plurality of image data A storage unit for temporarily storing the setting data and a plurality of image data output from the selecting unit, which are provided corresponding to the display priority order, are temporarily stored for each screen corresponding to the display priority order. A priority which has a storage element and sequentially reads out and outputs a plurality of image data stored in the storage element according to the display priority setting data stored in the storage means. And a road.

 Therefore, the present invention has the following unique effects.

(A) Since the selection means is provided, based on the on / off data input to each of the plurality of image data,
It is possible to freely turn on / off the display of the screen of each of the above-mentioned image data, so that the image is rich in variety and effective as an image effect.

(B) Since the storage means and the priority circuit are provided, it is possible to easily display a plurality of screens in order of priority by arbitrarily assigning priority to the display priority data input to the storage means. it can. Further, since a plurality of screens can be handled independently, it is possible to give a stereoscopic effect to the screen (video).

(C) Since the storage means can store the display priority setting data for each of the plurality of input image data, it is very easy to specify the display priority for each image data of each screen. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a priority circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing details of a display data decision unit 50 of the circuit shown in FIG. 1, and FIGS. FIG. 5 is a diagram showing a specific setting example of the rank setting register 80, FIG. 5 is a front view showing an example of a display screen, FIG. 6 is a circuit diagram showing an example of a conventional priority circuit, and FIG. 7 is an example of each screen. 3A is a front view showing an example of screen SC1, (b) is a front view showing an example of screen SC2, (c) is a front view showing an example of screen SC3, and (d) is a front view showing an example of screen SC3. FIG. 8 is a front view showing an example of a screen SC4, FIG. 8 is a front view showing an overlay screen in which the screens shown in FIGS. 7A to 7D are superposed according to the setting of the priority setting register 80 of FIG. FIG. 9 is a diagram showing a setting example of the priority setting register 80, and FIG. 10 shows the screens shown in FIGS. 7 (a) to 7 (d).
The front view showing the overlay screen when the setting of the priority setting register 80 in the figure is changed to the setting of the priority setting register 80 in FIG. 11, and FIG. 11 is an example of the setting of the priority setting register 80 in FIG. It is a figure which shows the example of a setting when a part is changed from. 1 to 4 ... selector, 10, 20, 30, 40 ... priority circuit, 11 to 14, 21 to 24, 31 to 34, 41 to 44 ... buffer memory, 50 ... display data decision unit, 51 to 54 …… Judgment circuit, 61 to 65 …… D-type flip-flop with 3-state buffer memory, 70 …… Screen control register, 80 …… Priority setting register.

Claims (1)

(57) [Claims] 1. Based on ON / OFF data input to each of a plurality of input image data, corresponding image data input when ON is output as it is, while input when OFF. Selecting means for outputting image data which is transparent data in place of the corresponding image data, storage means for temporarily storing the display priority setting data for each of the plurality of image data, and corresponding to the display priority. Display priority setting data stored in the storage means, which has a storage element for temporarily storing a plurality of image data output from the selection means for each screen corresponding to the display priority. And a priority circuit for sequentially reading and outputting a plurality of image data stored in the storage element.