JP2679391B2 - Horizontal sync signal generator - Google Patents

Description

The present invention relates to a horizontal synchronizing signal generating circuit for television signals, and more particularly to a horizontal synchronizing signal generating circuit for a television signal, which is incorporated in a servo control circuit of a VTR device and horizontally synchronized with a pseudo vertical synchronizing signal during special reproduction. The present invention relates to a horizontal synchronizing signal generating circuit suitable for the purpose of superimposing signals.

[Conventional technology]

The conventional horizontal sync signal generation circuit is typically an AFC (automatic frequency control) circuit used in a television receiver. The principle is to compare the phase of the signal obtained by differentiating the composite synchronizing signal and the output of the horizontal synchronizing signal generating circuit, and adjust the frequency of the horizontal synchronizing signal generating circuit by the integrated value of the comparison result. Since a large amount of impulse-like noise is included in the composite synchronizing signal, the noise is absorbed by integration, and the phase-locked loop configuration prevents loss of synchronization due to noise.

The AFC circuit is composed of analog circuits such as an integration circuit, phase discrimination circuit, and oscillation circuit, and is not suitable for integration.

On the other hand, the VTR servo control circuit may include a horizontal synchronizing signal generation circuit, and the same one as that used in a television receiver is used. The vertical sync signal plays an important role in VTR applications, but the horizontal sync signal is only used as a supplement during special playback (such as slow motion). That is, it is used only when a pseudo sync signal is output from the servo control circuit of the VTR so that the synchronization of the television receiver is not disturbed when the tape feed speed of the video tape is set to a speed different from the standard playback speed. In this application, the horizontal sync signal only needs to be output during the period of the pseudo vertical sync signal (several lines after the vertical sync signal), so use a circuit that keeps the horizontal sync signal synchronized, such as the AFC circuit. Is an excessive specification and is useless. Recent VTR servo control circuit is digitized, 1
There is a tendency for chips. It is technically difficult to embed an analog circuit such as an AFC circuit in a digital integrated circuit, and the price increases because the degree of integration is reduced and the chip size is increased.

[Problems to be solved by the invention]

The conventional horizontal sync signal generation circuit has a structure in which many analog circuits such as an integration circuit and a phase discrimination circuit are combined in order to always synchronize with the input composite sync signal. Therefore VT
Built into the R servo control circuit and trying to integrate it,
There were problems such as technical difficulties and an increase in chip size.

[Means for solving the problem]

A horizontal synchronizing signal generating circuit for a television signal according to the present invention includes a vertical synchronizing signal separating circuit that inputs a composite synchronizing signal and outputs a vertical synchronizing signal delayed by a predetermined time, a timer circuit that generates a horizontal synchronizing signal, and a vertical synchronizing signal. An edge detection circuit that detects the leading edge or the trailing edge of the signal and an initialization circuit that initializes the timer circuit are provided.

A vertical sync signal is separated from the composite sync signal, and the horizontal sync signal generating circuit is synchronized with the separated vertical sync signal. Since the impulse-like noise included in the composite sync signal is removed by the vertical sync signal separation circuit, the horizontal sync signal generator circuit uses a simple timer circuit to synchronize the horizontal sync signal by the method of initializing the timer circuit with the vertical sync signal. Turn into The timer circuit is suitable for integration and can be easily incorporated in the VTR servo control circuit. In addition, the vertical sync signal separation circuit and other circuits that are already built into the VTR servo control circuit are used for configuration, so the horizontal sync signal generation circuit can be configured with small-scale hardware.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. Television system shall be NTSC system. The composite sync signal 1 is a signal line for inputting the composite sync signal. The vertical synchronizing signal separation circuit 2 creates a vertical synchronizing signal delayed by 15 [μS] from the composite synchronizing signal and outputs it to the vertical synchronizing signal line 3. The vertical synchronizing signal line 3 transmits a vertical synchronizing signal. The edge detection circuit 4 detects the rising edge of the vertical synchronizing signal, creates a synchronizing pulse, and outputs it to the synchronizing pulse signal line 5. The synchronization pulse signal line 5 transmits a synchronization pulse. Initialization circuit 6
Resets the timer circuit 7 to the state of the count value "30" at the time when the synchronizing pulse comes in. Here, “30” is a value obtained by dividing the delay time 15 [μS] of the vertical synchronizing signal separation circuit 2 by the count clock cycle 0.5 [μS] of the timer circuit 7. The timer circuit 7 counts up a count clock having a cycle of 0.5 [μS], and when the count value reaches “126”, clears itself to “0” and outputs a horizontal synchronizing signal to the horizontal synchronizing signal line 8. The timer circuit 7 is composed of a count clock generation circuit and a 7-bit count circuit, and can be initialized to an arbitrary count value of 127 or less. The horizontal synchronizing signal line 8 is a signal line for outputting a horizontal synchronizing signal.

Next, the operation will be described with reference to the timing chart of FIG. FIG. 2 shows an example of a case where the horizontal synchronizing signal preceding the vertical synchronizing signal is out of synchronization.

In the period before the vertical synchronizing signal, the timer circuit 7 has a cycle of 0.
The count clock of 5 [μS] is counted from “0” to “126”, and when it is “0”, the horizontal synchronizing signal is output. Therefore, the horizontal sync signal line 8 has (126-0 + 1) × 0.5
A pulse signal is output every = 63.5 [μS] = 1H (H: horizontal sweep time). This pulse signal is generally not synchronized with the composite sync signal (it may be accidentally synchronized). When the composite sync signal is in the period of the vertical sync signal, the vertical sync signal separation circuit 2 outputs 15 [μ
S] The delayed vertical synchronizing signal is generated and the vertical synchronizing signal line 8
Output to The edge detection circuit 8 generates a synchronization pulse at the time of the leading edge of the vertical synchronization signal and outputs it to the synchronization pulse signal line 5. Therefore, at the time delayed by t1 = 15 [μS] from the leading edge of the vertical synchronizing pulse of the composite synchronizing signal, the timer circuit 7
Is initialized to the count value "30". After that, the timer circuit 7 outputs a pulse P1 to the horizontal synchronizing signal line 8 because the count value becomes “126” when counting t2 = (126−30 + 1) × 0.5 = 48.5 [μS]. Therefore, the time at which the pulse P1 is output is the time t1 + t2 = 15 + 48.5 = 63.5 [μS] = 1H from the leading edge of the vertical sync pulse of the composite sync signal. Therefore, the pulse P1 is synchronized with the horizontal sync pulse (second cut pulse) of the composite sync signal. The composite sync signal contains a large amount of impulse-like noise, but since it is removed by the vertical sync signal separation circuit 2, the timer circuit 7 that generates the horizontal sync signal is less likely to be out of sync with noise as in the conventional example. It is not necessary to have a circuit configuration. After pulse P1 6
Pulses P2, P3, P4, ... Are sequentially output to the horizontal synchronizing signal line 8 every 3.5 [μS] = 1H. Since the pulse P1 is synchronized with the horizontal synchronizing pulse of the composite synchronizing signal, the pulses P2, P3, ... Are also synchronized with the horizontal synchronizing pulse, and a correct horizontal synchronizing signal can be output.

Here, since the timer circuit 7 is initialized only at the leading edge of the vertical synchronizing signal, if there is an error in the frequency of the composite synchronizing signal, the horizontal synchronizing signal is not synchronized at a time far from the vertical synchronizing signal. There is no problem even if it shifts. This is because the VTR servo control circuit uses the horizontal sync signal only when outputting the pseudo vertical sync signal, and the pseudo vertical sync signal outputs only a few H (H: horizontal sweep time) after the vertical sync signal. Is. For example, the frequency of the composite sync signal is 1 [%]
If only the pseudo vertical sync signal is output for 6H even if there is a shift, the horizontal sync signal will be synchronized by 1 [%] × 6 during 6H.
= 6 [%], which is not so great as to disturb the synchronization of the television receiver.

As described above, the horizontal synchronizing signal can be generated in this embodiment. Although only the horizontal synchronizing signal generating circuit has been described in the present embodiment, since the circuit of the present embodiment is actually incorporated in the VTR servo control circuit, the horizontal synchronizing signal generating circuit is configured with extremely small hardware. it can. That is, in FIG. 1, the vertical synchronizing signal generating circuit 2 is originally built in the servo control circuit and does not need to be newly built. The timer circuit 7 is composed of a count clock generation circuit with a period of 0.5 [μS] and a 7-bit counter circuit. However, if the count clock is also used as the operation clock of the servo control circuit, only the 7-bit counter circuit is used. Can be configured. (Actual clock of servo control circuit is 0.
The thing of about 5 [μS] is often used. ) Initialization circuit
6. The edge detection circuit 4 is a simple logic circuit. After all, in order to incorporate the circuit of this embodiment into the VTR servo control circuit, a 7-bit counter and a small-scale logic circuit may be incorporated. Since these circuits are not only small in scale but also do not include analog elements such as a time constant circuit, they can be integrated with a servo control circuit, and can be realized in small size and at low cost.

In the NTSC system television signal, the leading edge of the vertical sync signal is synchronized with the horizontal sync signal in the first field, but in the next field, the leading edge of the vertical sync signal is not the horizontal sync signal, but the equivalent of the horizontal sync signal. It is synchronized with the pulse. Therefore, the first embodiment is not sufficient when the horizontal synchronizing signal must be exactly synchronized regardless of the field, and a second embodiment is an improvement on this point.

 FIG. 3 is a block diagram of the second embodiment.

Each element of the composite synchronizing signal line 1, the vertical synchronizing signal separating circuit 2, the vertical synchronizing signal line 3, the edge detecting circuit 4, the synchronizing pulse signal line 5, the timer circuit 7, and the horizontal synchronizing signal line 8 is the same as that of the first embodiment. Is the same.

The field determination circuit 101 determines the field of the composite sync signal and outputs a low level to the field signal line 102 if the determination result is the first field and a high level if it is the next field.

The field signal line 102 transmits the field determination result.

The initialization circuit 103 is a block including the selection circuit 104 and initializes the timer circuit 7 to the count value [30] or [94] by the synchronization pulse. Here, "30" is a value calculated by the same method as in the first embodiment. "94" is 1/2 of the horizontal sync signal period when the vertical sync signal separation circuit delay time is 15 [μS].
This is a value obtained by dividing the time 46.8 [μS] obtained by adding the time 31.8 [μS] of the above by the count clock 0.5 [μS] of the timer circuit 7.

The selection circuit 104 is a circuit for selecting a value for initializing the timer circuit 7. When the field signal selection 102 is low level, the constant "30" is selected, and when it is high level, the constant "94" is selected.

 Next, the operation will be described.

When the composite sync signal is the first field, the field determination circuit 101 outputs a low level to the field signal line 102. Therefore, since the selection circuit 104 selects the constant "30", the operation is the same as that of the first embodiment. That is, the timer circuit 7 sets the count value "3" at the leading edge time of the vertical synchronizing signal.
The horizontal sync signal is synchronized by initializing to "0".

The operation when the composite sync signal is in the next field is
This will be described with reference to the timing chart in the figure.

The field determination circuit 101 outputs a high level to the field signal line 102. A synchronizing pulse is generated at a time delayed by t1 = 15 [μS] from the leading edge of the vertical synchronizing pulse of the composite synchronizing signal. At this time, the field signal line 102 is at the high level. Initialize to ". After that, the timer circuit 7 is t2 = (126−94 + 1) × 0.5.
Since the count value becomes "126" when only = 16.5 [μS] is counted, the pulse P1 is output to the horizontal synchronizing signal line 8. Therefore, the time to output the pulse P1 is t1 + t2 = 15 + 16.5 = 31.5 from the leading edge of the vertical sync pulse of the composite sync signal.
[ΜS] = 1 / 2H. Therefore, the pulse P1 is synchronized with the horizontal sync pulse (first cut pulse) of the composite sync signal. Similar to the first embodiment, the pulses P2, P3, ...
Is also synchronized with the horizontal sync pulse.

In the present embodiment, the field determination circuit 101, which has the advantage of being able to obtain a horizontal synchronization signal that is correctly synchronized regardless of the field, is often already incorporated in the servo control circuit of the VTR. In comparison, the present embodiment can be realized only by changing the initialization circuit 6 to the initialization circuit 103.

〔The invention's effect〕

As described above, since the present invention configures the horizontal synchronizing signal generating circuit by effectively utilizing the hardware built in the servo control circuit of the VTR, it can be realized by adding a small amount of hardware. Also the additional hardware is suitable for integration,
The horizontal synchronizing signal generation circuit can be made small and inexpensive.

[Brief description of the drawings]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is an operation timing chart of the first embodiment of the present invention, FIG. 3 is a block diagram of the second embodiment of the present invention, and FIG. FIG. 7 is an operation timing chart of the second embodiment of the present invention. 1 ... Composite sync signal line, 2 ... vertical sync signal separation circuit,
3 ... Vertical sync signal line, 4 ... Edge detection circuit, 5 ...
Synchronized pulse signal line, 6 ... Initialization circuit, 7 ... Timer circuit, 8 ... Horizontal synchronization signal line, 101 ... Field determination circuit, 102 ... Field signal line, 103 ... Initialization circuit,
104 …… Selection circuit.

Claims (2)

(57) [Claims] 1. A vertical sync signal separation circuit for receiving a composite sync signal included in a reproduced video signal during special reproduction and generating a separated vertical sync signal delayed by a predetermined time from the vertical sync signal of the composite sync signal. A timer circuit for generating a pulse signal having a constant period which is the same as the period of the horizontal synchronizing signal defined by the technical standard of the television signal, and the leading edge or the trailing edge of the separated vertical synchronizing signal is detected and synchronized. A horizontal synchronization signal generation circuit including an edge detection circuit that generates a pulse, and an initialization circuit that responds to the synchronization pulse and initializes the timer circuit to a specific value determined from the predetermined time. 2. A field determination circuit for determining a first field and a next field of the composite synchronizing signal, further comprising a field determination circuit, wherein the initialization circuit is a first field proportional to the predetermined time.
And a second specific value proportional to the time obtained by adding a half of the period of the horizontal synchronizing signal defined by the technical standard of the television signal to the predetermined time. 2. The horizontal synchronization signal generation circuit according to claim 1, further comprising a selection circuit that selects the specific value according to a determination result of the field determination circuit.