JP2679376B2 - Image signal processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing device for converting a multivalued image into a binary image signal.

2. Description of the Related Art In recent years, with the rapid spread of office processing and image communication, there has been an increasing demand for high-quality image reproduction of other gradation images and print images of conventional black and white binary documents. In particular, pseudo halftone reproduction of a gradation image by a binary image has good compatibility with a display device and a recording device, and many proposals have been made.

The dither method is best known as one means for reproducing these pseudo halftones. This method attempts to reproduce gradation in a predetermined fixed area by the number of black or white dots reproduced in the area, and the threshold value and input image signal prepared in the dither signal matrix are set to 1 Binarization processing is performed while comparing each pixel.
(Reference: "Binary display of grayscale image by dither method", Nikkei Electronics, 5-1, P50-65, 1978). Recently, in order to improve the image quality of such pseudo-halftone reproduction, a single-color binary is used. There is an increasing demand not only for binarization processing but also for binarization processing by a dither method for color images.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention The dither method described above is widely used in terms of ease of hardware configuration and image quality. When using a dither matrix in which the maximum main scanning period and the maximum sub-scanning period are n, a dither matrix of up to main scanning period n × sub-scanning period n can be arbitrarily configured during monochromatic processing.

Further, in the case of dithering a color image, one main scanning line is color-converted into color data of four colors, an n × n dither matrix is provided for each color, and line-sequential binarization is sequentially performed for each color. It is a common method to go. (Hereinafter, referred to as line sequential four-color color processing) However,
This method has a problem that a maximum of n × n dither matrix is required for each color and the hardware scale increases.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a method of monochromatic processing and line sequential 4
It is an object of the present invention to provide an image signal processing device which shares a dither matrix during color processing and has a simple structure and which can efficiently use a memory.

Means for Solving the Problems The image signal processing device of the present invention, when performing a dither process for converting a multi-gradation input image signal sampled in pixel units into a binary image signal, a main scanning address and a sub scanning address. Of the dither matrix, a main scanning period register for setting the main scanning period, a sub scanning register for setting the sub scanning period, and a main scanning address counter for incrementing the main scanning address for each sub scanning period. And a means for inverting the most significant bit.

Operation With the above configuration, when performing dither processing, a dither matrix that is uniquely selected by the main scanning address and the sub-scanning address, and a main scanning period register that sets the main scanning period,
A sub-scanning cycle register for setting a sub-scanning cycle and a means for inverting the most significant bit of a main-scanning address counter for incrementing the main-scanning address for each sub-scanning cycle. The matrix can be shared and an efficient memory configuration can be constructed.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an image signal processing apparatus according to an embodiment of the present invention.

In FIG. 1, 1 IDT is a multivalued input image signal, 2 G
CLK is a pixel clock signal synchronized with 1 IDT, 3 LENBL
Is a line cycle signal indicating an effective section of one line in the main scanning direction, 4 is a main scanning cycle register for designating a dither cycle in the main scanning direction, and 5 is a pixel clock signal of GCLK of 2 to increment the scanning address 6. The main scanning address counter 7 compares the value of the main scanning period register 4 with the main scanning address 6, and if they match, a first matching circuit that sends out a main scanning address reset signal 8 for resetting the main scanning address counter 5, 9 is a sub-scan cycle register that specifies the dither cycle in the sub-scan direction, and 10 is a LE of 3.
A sub-scanning address counter that increments the sub-scanning address 11 by counting NBL. Reference numeral 12 compares the value of the sub-scanning cycle register 9 with the sub-scanning address 11. If they match, the sub-scanning address counter 10 is reset. The second coincidence circuit for sending out the scan address reset signal 13, 14 is an inversion signal for inverting the value of the most significant bit (MSB) of the main scan address counter 5, 15 SEL is invalid during monochromatic processing, line sequential 4 Select signal that is valid during color processing, 16 receives sub scan address reset signal 13
When SEL signal 15 is invalid, inverted signal 14 is not sent and SEL signal 16
When is valid, a selection circuit that sends out the inverted signal 14, 17 is a dither matrix memory that stores threshold data 18 for binarization designated by the main scanning address 6 and the sub-scanning address 11, 19 is an IDT signal of 1 Is compared with the threshold data 18 and 2
This is a comparison circuit that outputs 0 binary data ODT.

FIG. 2 is a timing chart when monochromatic dither processing is performed using the image signal processing apparatus of FIG. In the figure, while LENBL is at the LOW level, dither processing for one line in the main scanning direction is performed, and the sub-scanning direction is switched every time the falling edge of LENBL is counted. By this operation, the processing line in the main scanning direction is BW1, BW
2, BW3 ... and so on. IDT is input in synchronization with GCLK,
The configuration is such that the ODT that is delayed by one clock of GCLK is output.

FIG. 3 is a configuration diagram in the case where the dither matrix size is set to 16 × 16 at maximum and the dither matrix at the time of single color processing is configured to be 8 × 8. A method of generating the main scanning address and the sub scanning address in FIG. 3 will be described with reference to FIG. Set "7" in the main scanning cycle register 4 and set GCLK
The main scanning address counter 5 counts up from "0" to "7" for each count of, and if the value of the main scanning period register 4 is matched by the first matching circuit 7, the reset signal 8 of the main scanning address counter 5 is set. After sending out and resetting the main scanning address counter 5 to "0" again, the operation is set to be repeated. Similarly, "7" is set in the register 9 in synchronization with the sub-scanning, and the sub-scanning address counter 10 counts up from "0" to "7" for each LENBL counter.
If the value of the sub-scanning period register 9 is matched by the coincidence circuit 12, the sub-scanning address reset signal 13 is sent, the sub-scanning address counter 10 is reset to "0" again, and the operation is set to be repeated. Further, when the dither matrix for monochromatic processing is set to other than 8 × 8, it can be easily realized by changing the set values of the main scanning period register 4 and the sub scanning period register 9.

Next, a case where line-sequential four-color color processing is performed will be described. FIG. 4 is a timing chart when line-sequential four-color color processing is performed. Timing and signals are similar to those in the timing chart of FIG.
It is necessary to switch colors for each line processing in the main scanning direction. In FIG. 4, four colors, Y1, M1, C1, B1, Y2, ... Are switched line by line for processing.

FIG. 5 is a conceptual diagram of an 8 × 8 dither matrix used for each of the four colors. FIG. 6 is a block diagram of a dither matrix memory at the time of line sequential four-color color processing for realizing the dither matrix of FIG. 5 when the dither matrix size is set to 16 × 16 at maximum. A method of generating the main scanning address and the sub scanning address in FIG. 6 will be described with reference to FIG. The main scanning cycle register 4 is set to "7", and the main scanning address counter 5 counts up from "0" to "7" at each GCLK count, and the first matching circuit 7
Therefore, if the value matches the value of the main scanning period register 4, the reset signal 8 of the main scanning address counter 5 is sent, the main scanning address counter 5 is reset to "0" again, and then the operation is set to be repeated. "X'F" (hexadecimal number) is set in the sub-scan cycle register 9, and the sub-scanning address counter 10 changes from "0" to "X'F" (hexadecimal number) every count of LENBL.
Counts up, and if the second matching circuit 12 matches the value of the sub-scanning cycle register 9, the sub-scanning address counter reset signal 13 is sent out and the sub-scanning address counter 10 is reset to "0" again. Set to repeat the operation. When the reset signal 13 of the sub-scanning address is transmitted during the line-sequential four-color color processing, the SEL signal is valid, so the selection circuit 16 inverts the value of the most significant bit (MSB) of the main scanning address counter 5. Traffic light 14
Is sent. As a result, the main scanning address 6 is changed from "8" to "X'F" which is the right half of the dither matrix memory shown in FIG.
The area switches to (hexadecimal). In this case as well,
When the sub-scanning address counter 10 counts up to "X'F" (hexadecimal number), the selection circuit 16 outputs an inversion signal 14 which inverts the value of the most significant bit (MSB) of the main-scanning address counter 5, and the main scanning address. Reference numeral 6 switches from the area "0" to the area "7" in the left half of the dither matrix memory shown in FIG. By repeating this processing sequentially, the line sequential four-color color processing function can be realized when the dither matrix is 8 × 8.

Further, even if the size of the dither matrix for line sequential 4-color color processing is 7 × 7 or less, it can be easily realized by changing the set values of the main scanning period register 4 and the sub scanning period register 9. is there.

According to the present invention, the maximum cycle n is set to 16 by manipulating the most significant bit (MSB) of the main scan address for each set sub-scan cycle.
In the case of, a maximum of 16 × 16 dither matrix can be constructed for monochromatic processing, and a maximum of 8 × 8 × 4 color dither matrix, which is half of monochromatic processing, can be constructed for line sequential 4-color color processing.
It is possible to realize an excellent image signal processing device having an efficient memory configuration with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image signal device according to an embodiment of the present invention, FIG. 2 is a timing chart when monochromatic dither processing is performed, and FIGS. 3, 5, and 6 are structures of a dither matrix memory. FIG. 4 and FIG. 4 are timing charts when line-sequential 4-color color processing is performed. 4 ... Main scanning period register, 5 ... Main scanning address counter, 7 ... First matching circuit, 9 ... Sub scanning period register, 10 ... Sub scanning address counter, 12 ... Second matching circuit, 16 …… Selection circuit, 17 …… Dither matrix memory, 19 …… Comparison circuit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yuji Maruyama 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A 63-142968 (JP, A) JP-A 1- 171365 (JP, A)

Claims (1)

(57) [Claims] 1. A dither matrix which is uniquely selected by a main scanning address and a sub-scanning address when performing dither processing for converting a multi-gradation input image signal sampled in pixel units into a binary image signal, and a main scanning. A main scanning cycle register for setting a cycle, a sub scanning cycle register for setting a sub scanning cycle, and means for inverting the most significant bit of a main scanning address counter that increments the main scanning address for each sub scanning cycle. An image signal processing device characterized in that