JP2679175B2 - Audio signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Field of Use B Outline of Invention C Conventional Technology D Problems to be Solved by the Invention E Means for Solving the Problems (Fig. 1) F Action G Example G ₁ Overall Configuration of Example (No. 1) Fig. 4) Configuration of essential parts of G ₂ embodiment (Figs. 1 and 2) Configuration of other essential parts of G ₃ embodiment (Fig. 3) Operation of essential parts of G ₄ embodiment (Fig. 1) , FIG. 2) Operation of other main part of G ₅ embodiment (FIG. 3) H Effect of the invention A Industrial field of application The present invention relates to a pseudo stereo signal generator suitable for a game machine or the like.

B. SUMMARY OF THE INVENTION The present invention is a pseudo stereo signal generator, wherein a common digital audio signal is multiplied by the left and right channel digital main volume coefficients, and the left and right channel digital sub-volume coefficients are equalized in both channels. By multiplying the delayed digital audio signals respectively and synthesizing the main and sub volume-controlled signals for each channel, the main and sub reproduction sound images can be moved in a wide range independently of each other. , It is designed to obtain various sound effects.

C Conventional Technology Conventionally, as a sound source of a sound effect of a game machine or a sound source of an electronic musical instrument, for example, a square wave signal is supplied to a plurality of preset frequency dividers having different frequency division ratios and duty ratios, and output from each frequency divider. Individual sound source signal (so-called voice)
Was synthesized at an appropriate level. As the original oscillation waveform, a triangular wave, a sine wave, or the like is also used.

In the case of musical sounds, for example, like a piano or a drum,
Depending on the musical instrument, the entire tone generation period is divided into four sections: attack, decay, sustain, and release, and in each section, the amplitude (level) of the signal exhibits a unique changing state. The so-called ADSR control is performed so that the signal level of the signal similarly changes.

On the other hand, as a sound source for electronic musical instruments, a so-called FM sound source in which a sine wave signal is frequency-modulated with a low-frequency sine wave signal (FM) is known, and the modulation degree is a function of time. An audio signal (here, meaning an audio signal) can be obtained.

Note that noise may be used as the sound source of the sound effect.

D Problems to be Solved by the Invention In order to reproduce the sounds of various types of musical instruments using the above-described electronic sound source, extremely complicated signal processing is required, and the circuit scale becomes large. there were.

In recent years, in order to solve this problem, the so-called sampler that digitally records the sounds of various actual instruments, writes them in a memory (ROM), and reads out the signals of the required instruments from this memory. The sound source came to be awarded.

In this sampler sound source, in order to save the capacity of the memory, the digital audio signal is data-compressed and written to the memory, and the compressed digital signal read from the memory is expanded to return to the original digital audio signal.

In addition, only a signal of a specific pitch (pitch) is written in a memory for each instrument, and a signal read from the memory is subjected to pitch conversion processing to obtain a signal of a desired pitch. I have.

Further, a signal waveform at the beginning of sound generation, which is unique to each musical instrument and is called a formant, is written in the memory as it is, but a portion of a waveform which is a repetition of the basic cycle is written for one cycle and is repeatedly read.

These signal processing is of course digital processing,
For simplicity, in this specification, they are represented by analog signal processing functions.

By the way, with the sampler sound source as described above, if each voice is made into stereo and further echo (echo) is added in order to obtain more various sound effects, there is a problem that the circuit scale becomes large and the configuration becomes complicated. Occurs.

In view of such a point, an object of the present invention is to provide a pseudo stereo signal generator having a small circuit scale, a simple configuration, and capable of stereo-composing a large number of voices and adding echoes.

E. Means for Solving the Problems In the audio signal generator of the present invention, main multipliers are provided in the left and right channel main transmission lines, respectively, and a sub multiplier and a delay are respectively provided in the left and right channel sub transmission lines. And a circuit for supplying a digital audio signal to the main transmission line and the sub-transmission line in common, supplying digital main volume coefficients of the left and right channels to the main multiplier, respectively, and supplying the left and right channels to the sub-multiplier. The digital auxiliary volume coefficient of the right channel is supplied to each of the delay circuits, the delay amount of the delay circuit is controlled to be equal to that of the left and right channels, and the output signal of the sub transmission line is superimposed on the output signal of the main transmission line. It was done.

According to this configuration, it is possible to convert each sound source signal into a stereo signal and add an echo with a simple configuration using a small-scale circuit, and various acoustic effects can be obtained.

G Embodiment An embodiment of the pseudo stereo signal generator according to the present invention will be described below with reference to FIGS. 1 to 4.

The overall configuration of an embodiment of the overall structure present invention in G ₁ embodiment shown in Figure 4.

In FIG. 4, (1) is a sound source ROM provided outside.
And digitally recorded as described above, e.g., 16
Various data of various musical instruments of the bit are compressed almost instantaneously,
For example, the bit rate is reduced to 4 bits (BRR encoding) and stored in blocks.

(10) indicates a digital signal processing device (DSP) as a whole, and includes a signal processing unit (11) and a register RAM (12). Desired data of the various sound source data in the ROM (1) is controlled by the CPU (13) and transferred to the external RAM (14) via the signal processing unit (11). This external RAM (14)
Has a capacity of, for example, 64 kB. In addition to the sound source data, the CPU (1
The program of 3) is also written and used in time division. Similarly, a register that stores various control data
The RAM (12) is also used by the signal processing unit (11) and the CPU (13) in a time-division manner.

The sound source data read from the external RAM (14) is processed by the signal processing unit (11) in a BRR that is the reverse of the BRR encoding described above.
After being restored to the original sound source data by the decoding process, various processes such as the above-described ADSR process and pitch conversion are performed as necessary. The processed digital audio signal is supplied to the speakers (3L) and (3R) via the DA converters (2L) and (2R), respectively.

A main part of an embodiment of the structure present invention of a main part of the G ₂ embodiment is shown in FIGS. 1 and 2.

^{# A} in this example, ^{# B} ···· ^# are respectively adapted to output the synthesized 2-channel left and right 8 voice ^H, when each of the voice and digital audio signals of each channel For the sake of convenience of explanation, virtual hardware of the same configuration is provided for each voice and for each channel, although the arithmetic processing is performed by division.

In FIG. 1, (20A), (20B) ... (20H)
A is each voice ^{# A,} a signal processing unit for voice ^{# B} · · · · Voice ^{# H,} terminals of an external RAM (14) (1
The desired sound source data read from the sound source data storage unit (14V) is supplied by the sound source selection data SRC a to _h supplied to 5).

The sound source data supplied to the signal processing unit (20A) is supplied to the BRR decoder (21) via the switch S _1a , the data is expanded as described above, and the pitch conversion circuit is supplied via the buffer RAM (22). (23) is supplied. Switch S _1a
Has a register RAM via terminals (31a) and (32a).
(12) (See Fig. 4) to control data KON (key on)
And KOF (key-off) are supplied to control the opening and closing. Further, the pitch conversion circuit (23) is supplied with pitch control data P (H) and P (L) from the register RAM (12) via a control circuit (24) for operation parameters and the like and a terminal (33a). At the same time, the control circuit (24) has a terminal (34a)
And via the switch S _2a, for example, other voice signals, such as voice ^{# H} is supplied. The switch _S2a is connected to the control data FM from the register RAM (12) via the terminal (35a).
ON (FM ON) is supplied to control the connection state.

The output of the pitch conversion circuit (23) is supplied to the multiplier (26), and the control data ENV from the register RAM (12) is supplied.
(Envelope control) and ADSR (ADSR control) are connected to terminals (36a) and (37a), control circuits (27) and (28), respectively.
Is supplied to the multiplier (26) via the selector switch _S3a . Connection state of the switch S _3a is controlled by the most significant bits of the control data ADSR.

When noise is used as the effect sound source, although not shown, for example, the output of an M-sequence noise generator is switched to the output of the pitch conversion circuit (23) and supplied to the multiplier (26).

The output of the multiplier (26) is a second and third multiplier (29l)
And (29r) and register RAM
Control data LVL (left volume) and RVL (right volume) from (12) are supplied to multipliers (29l) and (29r) via terminals (38a) and (39a), respectively.

The instantaneous value OUTX of the output of the multiplier (26) is supplied to the register RAM (12) via the terminal (41a) and to the terminal (34b) of the signal processing unit (20B). Switch S _3a
The peak value ENVX of the output of the register R through the terminal (42a)
Supplied to AM (12).

Further, as indicated by a broken line, the output of the terminal (41a) of the signal processing unit (20A) can be supplied to the terminal (36b) of the signal processing unit (20B).

A map of each control data on the register RAM (12) is shown in Tables 1 and 2 below.

The control data in Table 1 is prepared for each voice. Second
The control data in the table is prepared in common for eight voices. The control data below the address 0D relates to FIG. 2 described below. Each register has 8 bits.

In FIG. 2, (50L) and (50R) are left channel and right channel signal processors, respectively.
The output of the signal processor of FIG second multiplier (20A) (291) is, via the terminal TL _a, is supplied directly to the left channel signal processing unit mainly adder (50L) (51ml), switch
Through S _4a, it is supplied to the sub adder (51el), the output of the third multiplier (29r) is, via the terminal TR _a, the right channel signal processing unit mainly adder (50R) in (51mr) is supplied directly to, via a switch S _5a, it is supplied to the sub adder (51er).

Similarly, voice ^# B to ^# signal processing section of the H (20B)
To (20H) are supplied to the adders (51 ml), (51el), (51mr), and (51er) of the left and right channel signal processing units (50L) and (50R).

Both signal processing unit (50L), a switch S _4a corresponding to the same voice _{(50R), S 5a; S} 4b, S 5b ···· S 4h, the S _5h, the pin (61a), (61b) · ... (61h), register R
Control data EON _a (echo on), EON _b ... from AM (12)
..EON _h is supplied and is opened and closed in conjunction with each other.

The output of the main adder (51 ml) is supplied to the multiplier (52), and the control data MVL (main volume) from the register RAM (12) is supplied to the multiplier (52) via the terminal (62). , The output of the multiplier (52) is supplied to the adder (53).

On the other hand, the output of the sub adder (51el) is passed through the adder (54), the left channel echo controller (14El) of the external RAM (14) and the buffer RAM (55), for example, a finite impulse response (FIR). Digital low-pass filter like filter (5
6) supplied to. The echo controller (14El) has a terminal (6
Control data ESA (echo start address) and EDL (echo delay) from the register RAM (12) are supplied via 3) and (64).

A low-pass filter (56) via a pin (66), the coefficient data C ₀ -C ₇ supplied from the register RAM (12).

The output of the low-pass filter (56) is fed back to the adder (54) via the multiplier (57) and is supplied to the multiplier (58). Both multipliers (57) and (58) have
Register RAM via terminals (67) and (68) respectively
Control data EFB (echo feedback) from (12)
And EVL (echo volume).

The output of the multiplier (58) is supplied to an adder (53).
It is combined with the output of the main adder (52), and is led out to the output terminal Lout via the oversampling filter (59).

The external RAMs (14El) and (14Er) in FIG. 2 are each a part of the external RAM (14) in FIG. Each channel and each channel are used in a time-division manner.

The buffer RAM (22) in FIG. 1 and the buffer RAM (55) in FIG. 2 are also used in a time-division manner, as described above.

Structure of Other Main Part of G ₃ Embodiment FIG. 3 shows the structure of a calculation unit for pseudo stereo according to an embodiment of the present invention. In FIG. 3, parts corresponding to those in FIGS. 1, 2 and 4 are designated by the same reference numerals.

In FIG. 3, reference numeral (71) denotes a multiplier, and a bus (7)
2) via buffer RAM (55) and Y ₀ register (85)
And the output of the register RAM (12) is supplied via the bus (73). The output of the multiplier (71) is supplied to the C register (82), the output of the register (82), via an overflow limiter (83) and a level shifter (84), Y ₀ register (85), Y ₁ register ( 86)
And it is supplied in common to Y ₂ register (87). The output of the register (85) is supplied to the multiplier (71) via the bus (72) as described above, and the output of the register (86) is led out. The output of register (87) is buffer RAM (5
Supplied to 5).

G ₄ operation of the main part of the embodiment Next, of an embodiment of the present invention, the operation of the main part shown in FIGS. 1 and 2.

In the sound source data storage unit (14V), sound source data of various musical instruments such as piano, saxophone, cymbal, etc. are stored with numbers 0 to 255, and are stored according to the sound source selection data SRC a to _h . The selected eight sound source data are the signal processing units (20A) to (20H) of each voice,
Predetermined processing is performed on a time-division basis.

In the present embodiment, the sampling frequency f _s, for example 4
Is selected to 4.1KHz, in one sampling period (1 / f _s) 8
For example, a total of 128 cycles of arithmetic processing are performed on the voice and the two channels. One operation cycle is, for example, 170 nSec
Becomes

In the present embodiment, control of the switch S _1a to S _1h start and (key-on) indicating the stop (key-off) to pronounce each voice is different from the normal, is performed using a separate flag. That is, control data KON (key-on) and KOF (key-off) are separately prepared. Both control data are each 8 bits, and are written in separate registers. Each bit D ₀ to D ₇ of each voice ^# A to ^# H key-on, corresponding respectively to the key-off.

This allows the user (softhouse) to set the flag “1” only for the voices that he wants to key on and off,
Unlike the related art, for example, it is not necessary to perform a troublesome operation of creating a program for temporarily writing the unchanged bit in the buffer register for each individual note.

As described above, for signal processing in a time division 8 voice ^# A to # ^H in this embodiment, in the pitch conversion circuit (23), interpolation operation based on the input data of each 4 samples before and after, i.e. over Sampling is performed and pitch conversion is performed at the same sampling frequency f _{s as} the input data. The desired pitch is represented by control data P (H) and P (L).

If the lower bit of P (L) is set to 0, uneven skipping of the interpolation data can be avoided, and fine pitch fluctuation does not occur, and a high-quality reproduced sound can be obtained.

Switch S by control data FMOM from terminal (35a)
When _2a is closed, it is supplied to the terminal (34a) as described above, for example, audio signal data of the voice ^{# H} is substituted into the pitch control data P (H), P (L ) , Voice ^#A is frequency modulated (FM).

Thereby, when the modulation signal is, for example, a very low frequency of several hertz, the modulated signal is vibratoed, and when the modulation signal is of an audio frequency, the tone of the reproduced sound of the modulated signal changes,
Even without special modulation sound source, sampler method FM
A sound source is obtained.

The control data FMON is written in the aforementioned KON as well as the 8-bit register, each bit D ₀ to D ₇ and voice ^#
A~ ^# correspond to H.

Further, in order to be able to select modulation and modulation voices arbitrarily, a memory for temporarily storing a modulation signal is required. In the present embodiment, the hardware configuration is simplified by modulating the next-stage voice signal with the preceding-stage voice signal.

Further, a multiplier (29) is added to the voice selected as the modulation signal.
In l) and (29r), muting is performed by the control data LVL and RVL to prevent overflow of audio data and the like.

In the multiplier (26), the level of the output signal of the pitch conversion circuit (23) is temporally controlled based on the control data ENV and ADSR.

That is, when the MSB of the control data ADSR is “1”, the switch S
_3a is in the connection state shown in the figure and ADSR control is performed. When the MSB of the control data ADSR is "0", the switch _S3a is in the connection state opposite to that shown in the figure and envelope control such as fading is performed. It is.

In this envelope control, direct designation, straight or broken line fade-in,
Five modes of linear or exponential fade-out can be selected, and the current peak value is adopted as the initial value of each mode.

In the polygonal line fade-in mode, the original y = A ₀ −B ₀ · exp {−kt} ...... (1), which requires three calculations with A ₀ , B ₀ , and k as positive constants, respectively. The exponential level increase characteristic of is approximated by a polygonal line of two kinds of gradients, one gradient being sufficient for one calculation.

In this case, by selecting the gradient of the section from the level 0 to 3/4 and the gradient of the section from the level 3/4 to 1 to 4: 1, (1)
A level rise characteristic of a broken line with a good degree of approximation to the equation can be obtained.

In the exponential fade-out mode, there is an exponential level drop characteristic of the form y = A ₀ · exp {−kt} (2).

In the case of ADRS control, the signal level rises linearly only in the attack section, and drops exponentially in the three sections of decay, sustain and release.

The time lengths of the fade-in and fade-out are appropriately set for each mode according to the parameter value specified by the lower 5 bits of the control data ENV.

Similarly, the attack and sustain times are set according to the parameter values specified by the upper and lower 4 bits of the control data ADSR (2), and the sustain level and
Decay and release time lengths are defined in the control data ADSR
It is set according to the parameter value specified by each two bits of (1).

In the present embodiment, in order to reduce the number of operations, the signal level rises linearly in the attack section of the ADSR mode as described above. However, the ADSR mode is switched to the envelope mode, and the line is broken in the attack section. A more natural ADSR control can be manually performed by associating the fade-in mode with the exponential fade-out mode in three sections of decay, sustain, and release.

When the control circuit (27) is linear specification mode, the other voice, for example, the signal is the signal processing unit ^{# H} (20H) terminal (4
From 1h), when supplied to the terminal (36a) of the signal processing section (20A), the multiplier (26), the audio signal of the voice ^{# A} is amplitude modulated by an audio signal of voice ^{# H.}

As a result, when the modulated signal has a very low frequency of, for example, several hertz, various performance effects can be obtained, such as applying tremolo to the modulated signal.

The signal output of the multiplier (26) and the envelope control input are supplied to the register RA from the terminals (41a) and (42a), respectively.
M (12) is supplied and rewritten every sample period, for example, when a plurality of audio signals having greatly different pitches are respectively obtained from sound source data of the same musical instrument, an audio signal having an arbitrary envelope characteristic different from a predetermined ADSR pattern Is obtained.

The output signal of the multiplier (26) is supplied to the second and third multipliers (29l) and (29r) by volume control data, respectively.
LVL and RVL are multiplied. Each of the control data is signed 8 bits. For example, when one of the two control data of the same code is increased and the other is decreased over a period of about 1 second, the sound images of the reproduced sound are arranged on the left and right. A so-called panning effect of moving between the speakers (3L) and (3R) is obtained.

If both control data have different codes, the reproduced sound image can move beyond the range between the two speakers, and the reproduced sound image can be localized backward by adding an appropriate device. Is also possible.

In the signal processing units (50L) and (50R) in FIG.
The switches S _4a and S _5a ; to S _4h and S _5h are closed by the control data EON (EON _{a to} EON _h ) from the terminals (61a) to (61h), respectively, and the voice to be echoed is selected. . The control data EON is written into an 8-bit register as shown in Table 2 above.

The delay time of the echo given to each voice output from the sub adder (51el) depends on the control data EDL supplied from the terminal (64) to the echo controller (14El), for example, in the range of 0 to 255 msec. Specified equally on channels. The amplitude ratio of the preceding and succeeding echoes is
The in-phase is set in the left and right channels by signed 8-bit control data EFB supplied from 7) to the multiplier (57).

The control data ESA from the terminal (63) is stored in the external RAM
Of (14), the upper 8 bits of the start address of the portion used for echo control are given.

Further, the FIR filter (56), pin (66) coefficients C ₀ -C ₇ of 8-bit signed is supplied from, auditory, as natural echo sound is obtained, passing the filter (56) The characteristics are set.

The echo signal obtained as described above is multiplied by a multiplier (5
8) Multiplied by the control data EVL in the multiplier (52)
Is synthesized by the adder (53) with the main audio signal multiplied by the control data MVL. Both control data MVL and EVL are both unsigned 8 bits and independent of each other,
The left and right channels are also independent.

This allows the level control of the main audio signal and the echo signal independently. For example, in the case of an image in which a huge wall rotates in a game machine, the main sound image remains stationary and only the echo sound image remains. It becomes possible to control so as to pan, and it is possible to obtain a reproduced sound field rich in a sense of reality that makes the user imagine the original acoustic space.

Operation Next other main part of the G ₅ examples illustrate the operation of the main part shown in FIG. 3 of an embodiment of the present invention.

For example, in the case of the left channel volume control of the voice ^{# A,} left volume control coefficient from the register RAM (12) and [LVL], the signal data x _e from Y ₀ register (85) is multiplied in a multiplier (71) You. In the case of right channel volume control,
The right volume control coefficient [RVL] from the register RAM (12) and Y ₀
And signal data x _e from the register (85) is multiplied in a multiplier (71).

Each operation sequence is expressed by the following equations (3) and (4): x _e · [LVL] + x _Li-1 → x _Li …… (3) x _e · [RVL] + x _Ri-1 → x _ri ...... (4) for the other voice ^# B to # ^H, similarly to the above, the volume control of the left and right channels is performed.

In this embodiment, in order to add the echo as described above,
Further, the following calculation is performed.

For main volume control of left and right channels, register RA
And M (12) master volume control coefficient from [MVL], (3) and (4) as represented by the formula, Y ₀ register signal data x _L and x _R and the multiplier from (85) ( 71) are multiplied. This multiplication result is temporarily stored in the register (82).

On the other hand, in the case of the sub-volume control, the audio data x _LE and x _{RE of} each voice selected to add an echo
Low-pass filtered and filtered audio data
is multiplied y _LF and echo feedback coefficient y _RF [EFB] respectively, after being added respectively selected audio data x _LE and x _RE, is supplied to the external memory (14El) and (14Er).

Then, the filtered audio data y _LF and y _RF are each multiplied by an echo volume control coefficient [EVL], and added to the main volume data.

The above operation is represented by the following equations (5) to (8).

y _LF・ [EFB] ＋ x _LE → y _LE …… (5) y _RF・ [EFB] ＋ x _RE → y _RE …… (7) The calculation results of the expressions (6) and (8) are stored in the buffer RAM (55) via the register (87).

Although the embodiment in which the present invention is applied to the sample sound source has been described above, the present invention can be applied to any sound source.

H Effect of the Invention As described above in detail, according to the present invention, common digital audio signals are multiplied by the left and right channel digital main volume coefficients, respectively, and the left and right channel digital sub-volume coefficients are set for both channels. Since the main and sub volume-controlled signals are combined for each channel by multiplying the digital audio signals that are equally delayed by, the main and sub reproduction sound images are moved in a wide range independently of each other. It is possible to obtain a pseudo-stereo signal generator that produces various acoustic effects.

[Brief description of the drawings]

FIG. 1 and FIG. 2 are block diagrams showing the configuration of the main part of an embodiment of the pseudo stereo signal generator according to the present invention, and FIG. 3 is a block diagram showing the configuration of the other main part of the embodiment of the present invention. FIG. 4 is a block diagram showing the overall construction of an embodiment of the present invention. (10) Digital signal processor, (12) Register RA
M, (14V) are sound source data storage units, (14El) and (14Er) are echo control units, (20A), (20B) ... (20H), (5
0L) and (50R) are signal processing units, (22) and (55) are RAMs,
(23) is a pitch conversion circuit, (24), (27), (28) is a control circuit, (26), (29l), (29r), (52), (57),
(58) and (71) are multipliers, (51ml) and (51mr) are main adders, and (51el) and (51er) are sub-adders.

Claims (1)

(57) [Claims] 1. A main multiplier is provided in each of the left and right channel main transmission lines, and a sub multiplier and a delay circuit are provided in each of the left and right channel sub transmission lines. A common digital audio signal is supplied to the channels, the main multipliers are supplied with left and right channel digital main volume coefficients, and the sub-multiplier is supplied with left and right channel digital sub-volume coefficients. An audio signal generator, wherein the delay amount of the delay circuit is controlled to be equal for the left and right channels so that the output signal of the sub transmission line is superimposed on the output signal of the main transmission line.