JP2664720B2 - IC mounting equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an IC mounting device having a plurality of multi-terminal IC chips such as a memory card.

[Conventional technology]

In recent years, as semiconductor memories such as ROMs and RAMs have increased in capacity, memory cards in which a large number of IC chips for these semiconductor memories are mounted on a single substrate have been manufactured, and are widely used for games, process management, and the like. Used in application fields.

However, the IC chip for semiconductor memory has 30 to 50 connection terminals, and these connection terminals are common to data bus terminals and control bus terminals except for some individual terminals such as chip enable terminals. These are connection terminals, and the connection wiring of these common connection terminals and individual connection terminals on a narrow board has been a problem.

 The conventional wiring structure will be described below with reference to the drawings.

FIG. 8 is a plan view of a conventional memory card, FIG. 9 is a partial plan view showing connection wiring between IC chips, and FIG. 10 is a partial sectional view. The substrate 50 constituting the memory card 5 is a double-sided wiring board as shown in FIG. 10, the upper surface 50a A ₁ to A ₂₀
In addition to the 20 IC chips shown by the symbols, the top pattern a shown by a solid line, the bonding pattern n shown by a black circle,
A through hole m indicated by a white circle is provided, and a lower surface pattern b indicated by a dotted line is provided on the lower surface 50b, and is connected to the upper surface 50a by the through hole m.

As shown in FIG. 9, each IC chip A has a square shape,
Each of the opposing sides c and d is provided with 20 connection terminals, and the other opposing sides e and f are not provided with connection terminals. The connection terminals provided on the side c are all common connection terminals, and the other 19 connection terminals provided on the side d are common connection terminals except for one chip enable terminal. .

Connect the connection wiring between the above IC chips to IC chips A ₁ , A ₂ , A ₃
Will be described.

Provided on a side portion c ₂ of the IC chip A ₂ as shown in FIG. 9
Connect 20 connection terminals to each bonding pattern n ₂ and side d ₂
Respectively connected by wire bonding the 20 connection terminals provided on the respective through holes m _2. In the same way
IC chip A ₃ sides c ₃ of the connection terminals each Bonn Dengue patterns n ₃ also, to wire Bonn dengue connection terminal side portion d ₃ in the through-hole m _3. As a result, IC chip A ₂ of the connecting terminals is connected a Bonn dengue pattern n ₂ halves (10) are
Which is connected to each of Bonn Dengue pattern n ₃ of the common connection terminal is connected to the IC chip A ₃ via a through-hole m ₂ top pattern a ₁ ten disposed on the left side of the IC chip A ₂ to avoid And the remaining bonding pattern n ₂ is IC chip A ₂
By the upper surface pattern a ₂ of the ten disposed on the right side are connected to the corresponding Bonn dengue pattern of the IC chip A _3. Through-hole m ₂ to which the connection terminal of IC chip A ₂ is connected
Are directly connected by the through hole m ₃ of the IC chip A ₃ by the lower surface pattern b provided on the lower surface side of the substrate 50.

That is, in the above configuration, the I
The connection terminals provided on one side of the C chip are connected, and the connection terminals provided on the other side are connected on the lower surface 50b where no IC chip is present, and the individual connection terminals are routed. Wiring is done.

The above is the connection structure between the IC chips. Next, the entire connection structure will be described with reference to FIG.

That is, 20 IC chips A _{1 to} A ₂₀ are arranged and bonded in four rows in the arrangement direction indicated by the arrow B on the substrate 50. At this time, by setting the direction of each IC chip to the opposite direction for each column as shown by the arrow, it is possible to perform the connection between the IC chips across the columns in a plan view without crossing over.

[Problems to be solved by the invention]

As described above, in the conventional memory card, since a large number of IC chips are directly mounted on one circuit board, it is necessary to disperse the wiring between the common connection terminals on the upper and lower surfaces of the circuit board. As a result, a large number of through-holes and high-density wiring patterns are required for the circuit board, and there are problems such as an increase in cost due to a high manufacturing cost through-hole process and a decrease in yield due to high-density mounting of IC chips on the high-density wiring patterns. . It is also possible to use a single-sided printed circuit board to make all connections between the common connection terminals on the IC chip bonding surface.However, in this case, a considerably large wiring space is required on both sides of the IC chip. It is necessary to arrange them with a sufficiently large distance, and as a result, there is a problem that the number of IC chips that can be mounted on one card is limited.

The object of the present invention is to solve the above-mentioned problems, the cost is easy,
An object of the present invention is to provide a reliable and high-density IC mounting apparatus.

[Means for solving the problem]

The configuration of the present invention for achieving the above object is as follows.

A plurality of IC chips for memory having a plurality of common connection terminals mounted on a circuit board having external connection terminals, and the common connection terminals of each IC chip are connected to the external connection terminals of the circuit board. In the above, a large number of IC chips are divided into a plurality of groups, a plurality of IC chips constituting each group are mounted on an auxiliary substrate to form a plurality of chip units, and each chip unit is mounted on the circuit board. Are arranged and the connection between the unit connection terminals provided in each chip unit and the connection to the external connection terminals are performed by a wiring pattern on the circuit board.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view of a memory card according to an embodiment of the present invention.
The circuit board 1 constituting the memory card 10 is provided with a notch 1a for accommodating a power supply device, a memory mounting part 1b, and a decoder mounting part 1c, and a plurality of external parts are provided at an end of the memory mounting part 1b. A connection terminal T is provided.

And memory mounting portion 1b of the circuit board 1, with four chip unit B ₁ to be described later, B _2, B _3, B ₄ are aligned disposed, a plurality of chip components on its periphery distribution Has been established.

The decoder mounting section 1c has mounted thereon elements such as a decoder IC2 and a capacitor 3. FIG. 2 and FIG.
Figure is a plan view and a sectional view of a chip unit B ₁ shown in FIG. 1, the chip unit B ₁ represents an IC chip mounted D ₁ to D ₄ for four memory on the auxiliary substrate 4 as one group, It is sealed with a sealing resin 6. And said plurality of unit connection terminals t to the side of the long side direction of the auxiliary substrate 4 is t ₁
Tt ₄ are provided separately. Each of the blocks t ₁ tt ₄ of the unit connection terminal t has the four IC chips D ₁ DD _4. Common connection terminals and one chip enable terminal) are connected to each other after they are commonly connected by a common connection pattern on the auxiliary substrate 4, and each block is connected to each IC chip. D ₁ to D ₄ of the chip d for connecting the enable terminal chip enable connection terminal te (hereinafter abbreviated as CE connection terminals) are provided.

Ie, the number of unit connection terminal t of the chip unit B ₁ represents has 32 number of terminals which is the sum of the four enable terminal provided one by one to the common connection terminal 28 and the IC chip D ₁ to D ₄ Each of the 32 terminals is divided into eight blocks t _{1 to} t ₄ .

And each of the chip units B ₂ , B ₃ , B ₄ shown in FIG.
Including the number and arrangement of unit connection terminal, all have the same configuration as the chip unit B _1.

4 and 5 are a top view and a back view of the circuit board 1 shown in FIG. 1, respectively, showing a wiring pattern. As shown in FIG. 4, the memory units 1b on the upper surface of the circuit board 1 have chip units B ₁ , B ₂ ,
A bonding pattern P is formed corresponding to the position of each unit connection terminal t when B ₃ and B ₄ are aligned and arranged, and a common bonding pattern P for each chip unit and its bonding pattern. The external connection terminal T corresponding to P is commonly connected by a wiring pattern.

Further, a decoder IC2 is mounted on the decoder mounting section 1c in a bonding pattern Ps as shown by a dashed line.

Next, a description will be given of implementation and connection wiring in the chip unit memory mounting section 1b as Case chip unit B _1.
The unit connection terminals t ₁ , t ₂ , t ₃ , and t ₄ of the chip unit B ₁ placed at the positions indicated by the dashed lines are respectively connected to the circuit board 1.
The upper bonding patterns P ₁ , P ₂ , P ₃ , and P ₄ are positioned, and by performing soldering in this state, the mounting state shown in FIG. 1 is obtained.

As a result, the chip enable bonding pattern Pd provided for each block of the bonding pattern
(Hereafter CE Bonn abbreviated as dengue pattern) CE connection terminal te provided for each block of the unit connection terminals of the chip unit B ₁ is, the circuit board 1 via the through hole while being respectively soldered It is connected to the back.

The bonding patterns P ₁ , P ₂ , P ₃ , and P ₄ excluding the CE bonding pattern Pd are connected to the corresponding blocks T ₁ , T ₂ , T ₃ , and T ₄ of the external connection terminals, respectively. I have.

Similarly, by mounting the other chip units B ₂ , B ₃ and B ₄ , the common unit connection terminals of each chip unit are connected linearly by the wiring pattern, and the bonding pattern P ₁ , P ₂ , P ₃ , and P ₄ and the external connection terminals T ₁ , T ₂ , T ₃ , and T ₄ are arranged in the same order, thereby enabling planar connection without crossover wiring.

Further, as shown in FIG. 5, a through hole P'd connected to the CE bonding pattern Pd on the upper surface is provided on the back surface of the circuit board 1, and the CE connection terminals te are all wired through the through hole P'd. It is connected to the decoder IC2 by a pattern. Furthermore, the decoder IC2 has an external connection terminal T
The enable control of the IC chip mounted on each of the chip units is performed by supplying the decoder control signal via ₀ .

As described above, by adopting a chip unit structure in which a plurality of IC chips are compactly packaged, the wiring density on the circuit board 1 can be reduced, and the number of through holes and the number of soldered terminals are significantly reduced. I was able to do it.

As an example, the number of solders in a case where four 29-terminal IC chips in this embodiment are set as one chip unit and the four chip units are mounted on a circuit board is different from that in the case of the conventional IC chip independent mounting. In comparison, the conventional is 29 terminals x 16 chips = 464 soldering, the present application is 32 terminals x 4 units = 128 soldering, and the number of soldering is 1/3 or less. As a result, the number of wirings and the number of through holes can be greatly reduced, and the spacing between wiring patterns can be widened.

Further, by making the arrangement order of the unit connection terminals t of the chip unit and the external connection terminals T of the circuit board 1 coincide, the planarization and linearization of the wiring pattern are realized, and the soldering is facilitated.

Furthermore, by performing a reliability check for each chip unit, the mounting yield on the circuit board 1 can be greatly improved. I was able to improve the badness of stay. 6 and 7 are a plan view and a sectional view showing another embodiment of the chip unit B according to the present invention. The difference from the embodiment of FIG. 2 is that the sealing resin 6 is an IC chip. Separated into a sealing resin 6a sealing D ₁ and D ₂ and a sealing resin 6b sealing IC chips D ₃ and D ₄ , the center line K indicated by a dashed line is used as a boundary. Thus, a plurality of common connection patterns L are exposed between the sealing resins 6a and 6b of the auxiliary substrate 4 by being separated into a first block Ba and a second block Bb.

The configuration of the above-described embodiment is intended to further improve the overall yield by forming a chip unit. The reliability of the chip unit B is checked for the first block Ba and the second block Bb, and one of the blocks is defective. If there is, cut and separate at the center line K, replace the defective block with a non-defective block at the center line K, and connect the common connection patterns L with each other by a method such as soldering to reproduce. The completed chip unit B is completed.

That is, four ICs mounted on the chip unit B
In the case where one defect is present in the chip, four IC chips are discarded in the embodiment of FIG.
Only two IC chips are discarded, and the remaining two IC chips can be rescued. As a result, the overall yield can be improved. Note that the number of IC chips mounted in the chip unit and the number of chip units mounted on the circuit board in the present invention can be arbitrarily selected.

〔The invention's effect〕

As described above, according to the present invention, it is possible to reduce the wiring and connection density on a circuit board by arranging chip units on which a plurality of IC chips are mounted on a circuit board.
It is possible to improve the IC mounting density and the reliability by unit management at the same time, which has a great effect on improving the product competitiveness of each IC mounting.

[Brief description of the drawings]

FIG. 1 is a plan view of a memory card of the present invention, and FIGS.
FIGS. 6 and 7 are plan and sectional views of the chip unit of the present invention, FIGS. 4 and 5 are plan and rear views of the circuit board of the present invention, and FIG. 8 is a conventional memory card. FIGS. 9 and 10 are a partial plan view and a partial cross-sectional view of a conventional memory card. 1 ...... circuit board, 5,10 ...... memory card, B ₁ .about.B ₄ ...... chip unit, D ₁ to D ₄ ...... IC chip.

Claims (1)

(57) [Claims] An IC chip for a memory having a plurality of common connection terminals is mounted on a circuit board having an external connection terminal, and a common connection terminal of each IC chip is connected to the external connection terminal of the circuit board. In many IC mounting locations,
IC chips are divided into a plurality of groups, a plurality of IC units constituting each group are mounted on an auxiliary substrate to form a plurality of chip units, and each chip unit is arranged and arranged on the circuit board. An IC mounting device, wherein connection between unit connection terminals provided on a chip unit and connection to the external connection terminal are performed by a wiring pattern on the circuit board.