JP2648909B2 - Write timing compensator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal writing device in a digital magnetic recording device. More specifically, the present invention relates to a method for writing a signal to a magnetic recording medium, and then detecting a pattern peak shift of a read signal occurring when reading. The present invention relates to an apparatus for compensating timing of a write current to be reduced.

[Conventional technology]

In a magnetic recording device such as a magnetic tape device or a magnetic disk device, when writing data to a magnetic recording medium, generally, the code is changed and the encoded data is written. At this time, as the writing conditions, a large minimum magnetization reversal interval (Tmin) and a small maximum magnetization reversal interval are one criterion for code selection. Therefore, conventional MFM (Modified Frequency Modula
Option) became mainstream, but recently 2-7RLLC (Run
Length Limited Code) has been put into practical use, and various systems will be developed in the future.

A characteristic of magnetic recording is the pattern peak shift.
When a pattern having a short magnetization reversal interval and a pattern having a long magnetization reversal interval are continuously recorded, there is a disadvantage that the peak interval of the read signal is longer than when a portion having a short magnetization reversal interval is written.

FIG. 5 is a diagram showing the principle of occurrence of a pattern peak shift.
Figure Iw is the write current waveform, a pulse width T ₁ is sufficiently smaller than T _2. If the write was line summer in a repeating pattern of the T _1, T _2, readout waveform S peak point of _R A, B, time indicated by C, (between _{A-B) T 3, T} 4 ( between B-C ) Is T ₃ > T ₁ , T ₄
<T _2, and the more inversion timing of the original _{T 3 = T 1, T 4} = T 2 become to place the write current, development appearing the peak position of the read waveform is deformed. The peak shift due to this phenomenon causes an error (data error) when decoding the read lower data to the original data.

As a countermeasure, by anticipating the direction in which a pattern peak shift will occur at the time of writing and performing timing compensation, that is, by compensating the magnetization reversal interval, the occurrence of the pattern peak shift during reproduction is reduced, and no data error occurs. It is possible to do so.

FIG. 7 is a timing chart based on the conventional timing compensation method, in which (1) is a write clock,
(2) is input data, (3) is encoded data obtained by encoding the input data (2), and (4a to 4e) are encoded data (3)
And (5) are compensated encoded data obtained by partially selecting and combining the signals (4a to 4e) according to the pattern of the encoded data (3).
(6) is a write signal generated based on the pulse rise of the encoded data (5) after correction.

Next, the operation will be described. The input data (2) is synchronized with the write clock (1) to generate encoded data (3). To compensate for the encoded data (3), a plurality of delayed signals (4a to 4e) are created. In the seventh illustrated to Example respect pulses P ₁ of the coded data (3), different pulse P _1a to P _1e of this case five timing occurs.

In the case of magnetic recording, the pattern peak shift tends to be reproduced when the portion where the magnetization reversal is short in time and the portion where the magnetization reversal time is long are adjacent to each other, and the long portion is short and the short portion is long. This has been described with reference to FIG.

Encoded data (3) to prevent pattern peak shift
By knowing the combination of the patterns in advance, it becomes possible to write the pattern at a timing shifted in the direction of preventing the pattern peak shift. That considered to make signal (4 a to 4 e) any pulses P _1a to P _1e selects the compensated encoded data (5) from the. To compensate for the pulse P ₁ in the figure, it is necessary to examine the distance before and after the pulse P ₁ of the coded data (3). The time interval T _2-1 of the pulse P ₂ and the pulse P ₁ before the figure "2", pulse after with the pulse P ₁
The time interval T _{1-3 from} P ₃ is “6”. Leave appropriate compensation amount previously determined to correspond with a peak shift amount in the combination of this interval it, select the pulse P _1a closest to the proper compensation amount from the signal (4 a to 4 e), the compensated encoded data (5 )make.

In this way, from the encoded data (3), an appropriate signal (4a
44e) to select encoded data after compensation (5)
Can be generated.

The write timing compensation method has been roughly described above.

This will be described in more detail. FIG. 6 is an example of a circuit for realizing the above-described write compensation method. In the figure, (7) is an encoding circuit, (8) is a temporary storage circuit of encoded data (3) output from the encoding circuit (7), (9) is a compensation amount determination circuit, and (10) ) Is the delay element, (11) is the selection circuit, (1)
2) is an addition circuit, and (13) is a write current generation circuit.

The writing clock (1) and the input data (2) are input to the encoding circuit (7), and the encoded data (3) is output. In this case, the temporary storage circuit (8) comprises a 15-stage shift register, and sequentially shifts the encoded data (3) at twice the frequency of the write clock. Center stage pulse P ₁ to be compensated Thus the shift register (8
when shifted to h), the shift register (8 a to 8 e) has been stored in the part after the pulse P ₁ of the coded data (3), the shift register (8I～8o) prior P ₁ Is stored.

The compensation amount determination circuit (9) corresponds to the pattern stored in the shift register (8), and selects an appropriate gate in the selection circuit (11) to thereby control the delay element (10).
To select the delay coded codes (4a to 4e) having different delay amounts to obtain the compensated coded data (5).

When the obtained encoded data (5) after compensation is input to the write current generation circuit (13), the write current (6) whose polarity is inverted at the rising edge of the pulse of the encoded data (5) after compensation.
Is obtained.

[Problems to be solved by the invention]

In the conventional write timing compensation method, the encoded data must be stored over several bits, so that the scale of the circuit to be implemented becomes large, and a considerable amount of time is required from the input of the input data to the actual recording on the recording medium. There were problems such as a time delay.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and is directed to a coding system for dividing input data and encoding the divided data in units of divisions where the division units vary in various ways. However, the write timing of the encoded data can be determined based on the input data.
It is another object of the present invention to provide a write timing compensator capable of determining a write timing compensation amount with a simple circuit configuration.

[Means for solving the problem]

The write timing compensator according to the present invention comprises: an input data immediately before an input data in which a division unit length to be encoded changes to a set length; an input data currently to be encoded; A shift register for holding input data to be encoded in the shift register; a word length counter for dividing the currently encoded input data held in the shift register into set unit lengths; An encoded data generation circuit for encoding input data to be encoded in units of data divisions divided by the word length counter, and outputting the encoded data as encoded data; and encoding data encoded by the encoded data generation circuit on a recording medium. The amount of timing compensation for correcting the write timing is determined by comparing the immediately preceding input data held in the shift register with the currently encoded input data. And a compensation amount determining circuit for determining based on the input data and the input data to be encoded immediately thereafter.

Further, the input data holding portion of the shift register to be currently encoded is shared with a register used for encoding processing in the encoded data generation circuit.

[Action]

The word length counter of the write timing compensator according to the present invention divides the current coded input data held in the shift register into predetermined division unit lengths, generates a divided signal, and generates encoded data. The circuit encodes the input data in units of data division by a word length counter, and the compensation amount determining circuit encodes the encoded input data of the shift register, the input data encoded immediately before the input data, and A write timing compensation amount of the encoded data is determined for each preset data division unit based on the input data encoded immediately after the encoded input data.

(Example of the invention)

Hereinafter, an embodiment of the present invention will be described. Here, 2-
A case in which the present invention is applied to the 7RLLC coding method will be described as an example.

FIG. 3 shows an encoding algorithm based on 2-7 RLLC, in which input data is divided into seven variable-length words having a maximum length of 4 bits and converted into corresponding encoded data. FIG. 4 shows an arbitrary input data sequence encoded by this encoding algorithm.

In FIG. 4, "1" is one or two in the sequence of encoded data (3) corresponding to one division of input data (2), and the last bit in one division of input data (2) is "1". 0 "
In this case, the last three bits of the corresponding coded data are "100", and when the last bit of the input data (2) is "1", the four bits after the corresponding coded data are "1000".

In the case of this encoding method, the encoding is performed for each division of the input data (2). One division of the input data string being encoded at that time and one division of the input data string that was encoded immediately before that are performed. By referring to the last bit in the division,
“1” in encoded data to be compensated and “1” before it
You can see the interval between

Similarly, the interval between "1" in the encoded data to be compensated and the subsequent "1" can be determined by referring to one division in which encoding is performed in the input data and one division immediately thereafter. .

By referring to the 8 bits before and after including the input data string being encoded in this manner, the interval between "1" before and after "1" of the encoded data can be known, and as a result, timing compensation can be performed. it can.

FIG. 1 is a timing chart of one embodiment of the present invention.
(1) is the write clock, (2) is the input data, 2a to 2h
Is the output of an 8-bit shift register that sequentially shifts the input data in synchronization with the write clock (1).
6) is a signal indicating the division of the input data (2), (3) is encoded data, (4a to 4e) are signals obtained by delaying encoded data at different timings by the number of types of compensation, and (5) is compensation. The post-encoded data, (6), is the post-compensation write current.

Next, the operation will be described. The input data (2) is sequentially shifted in synchronization with the write clock (1) to produce a data string (2a to 2h) consisting of 8 bits. At this time, encoding is actually performed for a maximum of 4 bits (2g to 2d).
h is the last bit of the one-division data which was previously encoded. Data strings (2a to 2h) (2g to 2d) are coded according to the coding algorithm, and coded data (3) is generated. If there is a division of the data being coded at this time, this is indicated. A signal (16) is generated.

For example consider a case where the timing compensating pulse P ₁ in the coded data (3). The pulse P ₁ is believed to be obtained by encoding definitive "10" in the input data (2).

That is, the rising edge of the signal indicating the division of the input data (F
The output (2a to 2h) of the shift register is
“1”, 2g = “1”, 2f = “0”, 2e = “0”, 2d = “1”, 2c = “0”,
2b = "0" and 2a = "0". Here, “1” in 2h indicates that three “0” s continue from “1” P ₂ before the encoded data to the delimiter F, and 2g = “1” and 2f = “0” indicate the current The encoded data (3) being encoded consists of 4 bits,
Indicating that the divided F There is one "0" before the next pulse P _1, also from 0 to the pulse P ₁ to the next division G there are two. Further 2e = "0", 2d = "1", 2c = "0" indicates that the next encoded data sequence is "010", i.e. the segmented G to the next pulse P ₃ "0" is 0 It shows that it is an individual.

Spacing of the thus pulse P ₁ and the pulse P _2, P ₃ of the front and back become apparent by referring to the output of the 8-bit shift register for shifting the input data (2) (2a~2g).

Using this, signals (4a to 4e) having different timings are selected based on the 8-bit input data string (2). For example, in this case, _P2c , _P1e , and _P3c are sequentially selected. , Compensated encoded data (5) is generated, and a signal which is inverted at the rise thereof becomes a write current (6).

Next, an example of means for realizing the above method will be described with reference to FIG.

In FIG. 2, (7) is an encoding circuit, and 2-7RLL
The C type coding circuit (7) comprises a four-stage shift register 7a for storing input data (2), a combination circuit 7b for generating coded data (3) based on the contents of the shift register, and a coding circuit 7b. It comprises a word length counter 7c indicating the word length of the input data in the input data "0110
When encoding "11 ...", the upper four bits "0110" are stored in the shift register 7a, and the corresponding data word "011X" is associated with the conversion table in FIG. The word length "3" of the data word "011" is set in 7c. From this state, the corresponding encoded data "001000" is generated in synchronization with the write clock (1), and at the same time the word length counter 7c is decremented by one. Thereafter, when the word length counter 7c becomes "0", the word length counter 7c outputs a data division signal (16), and the next division of the input data (2) is encoded.

The configuration of the encoding circuit (7) as described above is the same as that of the sixth embodiment.
There is no difference from the coding circuit (7) shown in a simplified manner in the figure.

In FIG. 2, (10) is a delay element, (11) is a selection circuit,
(12) is an adder, (13) is a write current generator, and (1)
4) is an 8-bit shift register obtained by adding one bit before and three bits after the 4-bit shift register 7a included in the encoding circuit (7). From the side closer to the input side of input data (2)
Each of the registers is indicated by a continuous suffix 14a, 14b... 14h, and 2a to 2h are outputs of the registers (14a to 14h). (15) is a compensation amount decision circuit, and the output of each register (2a
~ 2h), encoded data (3) and data division signal (16)
To determine the compensation amount.

 Next, the operation will be described.

The input data (2) is input to the shift register (14) together with the write clock (1), and is sequentially shifted in synchronization with the write clock (1). At the same time, the encoding circuit (7) obtains the outputs (2d to 2g) of the shift register 7a, encodes the input data (2), and encodes the data division signal (16).
Is output. The compensation amount determination circuit (15) determines the compensation amount based on the 8-bit pattern of the input data (2) held in the shift register (14) when the data division signal (16) rises, and gates the selection circuit (11). Select one. The encoded data (3) is converted into signals (4a to 4e) having five different timings by the delay element (10), and is compensated through a gate selected only in the selection circuit (11). It becomes post-encoded data (5), and at the rise, the write current (6) is inverted.

 In this way, timing compensation is possible.

In this embodiment, a 3-bit shift register is provided after the shift register 7a instead of the 4-bit shift register. That is, when the input data currently being encoded is “0010” or “0011”, the amount of timing compensation can be determined if the first three digits of the input data to be encoded immediately are known. That is, if the input data currently being encoded is “0010”, if the input data to be immediately encoded is “0010”, the encoded data becomes “00 00100100 00100100”,
If “0011”, the encoded data is “00 00100100 0
0001000 ". Therefore, the number of" 0 "between the encoded data of the input data currently being encoded and the encoded data" 1 "of the input data to be immediately encoded becomes two, four or more, “1”
Two “0” s between “1” and “1” are used as a timing compensation amount to narrow the write timing during this period.

Similarly, if the input data currently being encoded is “0011”, and if the input data to be immediately encoded is “0010”,
The encoded data becomes “00 00001000 00100100”, and if it is “0011”, the encoded data becomes “00 00001000 00001”.
Therefore, there are five or more "0" s between the encoded data of the input data currently being encoded and the "1" of the encoded data of the input data to be immediately encoded. The timing is not changed, and the amount of timing compensation becomes zero.

As described above, in this embodiment, if there is a 3-bit shift register after the shift register 7a, the timing compensation amount of the encoded data is determined.

In the description, the number of compensations is five, but this can be arbitrarily selected.

〔The invention's effect〕

As described above, according to the present invention, the word length counter for dividing the input data held in the shift register for each division unit length for encoding is provided, and the compensation amount determination circuit is configured to input the encoded data of the shift register. Data, the input data encoded immediately before the input data, and the input data encoded immediately after the input data to be encoded. Since the data write timing compensation amount is determined, it becomes possible to determine the write timing of the encoded data based on the input data even in an encoding method in which the divided unit length to be encoded varies variously. ,Also,
The capacity of a register for holding data for determining the write timing compensation amount can be reduced.

Furthermore, in a shift register in which a portion for holding input data to be encoded is shared with a register used for the encoding process in the encoded data generation circuit, the register for holding the input data is changed from the register for holding the input data to the encoded data generation circuit. The movement of data to the register used for the encoding process can be omitted, and the time delay from input of input data to recording on the recording medium can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing the timing of each signal of the timing correction system according to an embodiment of the present invention, FIG. 2 is a circuit block diagram showing an example of realizing means of the present invention, and FIG. FIG. 4 is a diagram showing an example of data encoding by applying the encoding algorithm as an embodiment, FIG. 5 is a waveform diagram showing how a peak shift occurs, FIG. FIG. 7 is a circuit block diagram showing an example of means for realizing a conventional timing compensation system, and FIG. 7 is a diagram showing the timing of each signal according to an embodiment of the conventional timing compensation system. In the figure, (1) is a write clock, (2) is input data,
(2a to 2h) are shift register outputs, (3) is encoded data, (4a to 4e) is delayed encoded data, (5) is compensated encoded data, (6) is compensated write current, (16) ) Is an input data decomposition signal. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. An input data which is encoded immediately before, an input data which is currently encoded, and an input data which is encoded immediately after, of input data whose division unit length to be encoded changes. A shift register; a word length counter for dividing the currently encoded input data held in the shift register into set unit lengths; and a word length counter for dividing the currently encoded input data held in the shift register. An encoded data generation circuit that encodes the data in units of data divided by the counter and outputs the encoded data as encoded data, and a timing compensation amount that corrects the timing of writing the encoded data by the encoded data generation circuit to a recording medium,
A compensation amount determining circuit that determines based on the immediately-encoded input data held in the shift register, the currently-encoded input data, and the immediately-encoded input data. A write timing compensating device characterized by the above-mentioned. 2. The apparatus according to claim 1, wherein the input data holding section of the shift register to be currently encoded is shared with a register used for encoding processing in the encoded data generating circuit. Write timing compensator.