JPS61154237A - Synchronizing system - Google Patents

Abstract

PURPOSE:To avoid the mis-recognition of a synchronizing signal and a data in the M<2> system by using a signal inverted for a prescribed number of times at a period corresponding to a 2.5-bit width as a synchronizing signal so a to zero an accumulated charge in the synchronizing signal period thereby preventing generation of a DC component. CONSTITUTION:When a synchronizing signal generating command signal is outputted from a control circuit 2 and a data (08) H is outputted sequentially one by one bit from the most significant bit in figure A from a data generator 5, a bit series B is outputted sequentially at each 2-bit from an M<2> recording bit generator 6 and the data is fed to one input terminal of an AND gate 8 sequentially one by one bit by shift register 7. The output of the register 7 is combination between a signal C corresponding to a data bit and a signal D corresponding to a clock bit. An output E of a gate signal generator 9 goes to a low level when the count of a counter is equal to '7' and '13', a data F is outputted sequentially from the AND gate 8 one by one bit and given to one input terminal of an exclusive OR gate 10 to obtain a write signal G having an inverting period of 2.5T.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a synchronization method in digital information transmission.

BACKGROUND ART PCM (PCM) converts an analog signal such as an audio signal into a binary code, records it on a recording medium, receives it or reproduces it, decodes it, and obtains the original analog signal again.
, f pulse code modulation) system is formed from a plurality of consecutive frames, and when data for multiple channels is included, time division multiplexing is often performed. When receiving or reproducing such digital data, if decoding is not started in synchronization with the arrival of the first data in one frame, the data may be incorrectly connected to another channel and the analog signal obtained by decoding may be replaced by the original analog signal. The signal will be different. Therefore, a synchronization signal consisting of a plurality of focuses and having a predetermined bit soturn is provided at the beginning of each frame, and frame synchronization is normally performed using this synchronization signal.

On the other hand, various modulation methods have been proposed for recording or transmitting digital data at high density.

These various modulation methods, especially those that can record or transmit at a higher density than other methods, divide the data string into consecutive blocks of m pinos, and convert the m-bit binary code in each block into n Code conversion is performed to convert bits into binary codes, and the binary code string obtained after the code conversion is converted into N RZ I (N
o Zero Tnverse ) or in combination with NR and Z modulation.

In general, a modulation method for high-density recording on a recording medium is required to satisfy the following conditions.

(1) The minimum inversion interval (hereinafter referred to as Tm1n) of the write signal waveform to the recording medium obtained after modulation is long and the maximum inversion interval (hereinafter referred to as Tmax) is short. When Tm is long, interference between adjacent inversions becomes small, allowing for higher density, and when 'T'max is short, self-synchronization becomes easier.

(11) Detection window width (hereinafter T
It is written as W. ) is wide. In magnetic recording, recording bits are detected by detecting the peak of the reproduced signal waveform, but since the TW is the tolerance for the deviation of the peak position, a wider TW is suitable for high-density recording. In a recording/reproducing device using a laser beam, if the TW is wide, the tolerance range for the deviation of the detection position becomes wider, and the amplitude at the detection point becomes larger, increasing the noise margin.

DC and low frequency components should not exist in the write signal to the recording medium obtained after 01O modulation. In a device having a transmission system that cannot transmit direct current and low frequency components, the waveform of a signal containing these components will be distorted. In addition, in recording and reproducing devices using laser light, these components are not exposed to radiation. Decreases system reliability.

Conversely, if these components do not exist, it becomes possible to remove low frequency noise and drift using a high/bus filter.

MPM (Modified Freqtb
ency ≠ 1,000. That is, for example, in Figure 1 (5
)d
.

is a 2-bit binary code a depending on the state of the previous pick) d-1. The code sequence shown in FIG. 0 is obtained by converting to bo. The obtained code sequence is modulated by NR and ZI to obtain a write signal S1 as shown in FIG.

Here, in order to estimate the DC component in the write signal obtained as described above, the cumulative charge is determined. The cumulative charge is assumed to be +1 for the positive minimum pulse width, -1 for the negative minimum pulse width, and +2 for the double pulse width, and then counted. It can be obtained by The amount of DC component can be estimated based on the magnitude of this accumulated charge.

Now, in the write signal shown in FIG. 10, the sum of the high level sections in the part corresponding to the input data series "old 10" is 1T, and the sum of the low level sections is 3T, so the accumulated charge is -2. Note that T indicates the reciprocal of the data bit transfer rate (bit period). Therefore, if the input data series is a series of "old 10", the accumulated charge will be negative infinity. Therefore, there may be cases where a DC component exists.

In the MFM method, input data bit sequences can be classified into the following five types of sequences.

(a) "OO" (b) "01...10" (Number of consecutive 1's: Odd number) (C) "Old...10" (Number of consecutive 1's: Even number) @) ”]・・・・・・1″(
Number of consecutive 1s: odd number) (e) ``1...
A DC component occurs only in the write signal corresponding to the series (c) among the five series of 1'' (number of consecutive 1's: even number) or more.

Therefore, the M2 (Motified Miller) method and the like have been proposed as a modulation method that does not generate a DC component in the write signal. In the M2 system, improvements have been made to the code conversion for the sequence (c). Sunawachi,
In the M2 method, almost the same conversion as the MTi'M method is performed, but if an even number of bits tttll are consecutive after 1101+ and the accumulated charge at tt is not zero, then , the last Pino) "1" is converted to correspond to non-inversion. For example, each bit in the input data bit sequence as shown in FIG. 2(A) is converted into a 2-bit binary code as shown in FIG. 2(C). The obtained code sequence is modulated by NTFI to obtain a write signal S2 as shown in FIG. As is clear from the same figure (q), in the M2 method, the accumulated charge of the write signal becomes zero, and no DC component is generated.However, in the M2 method, Tm and ax become 3T, and the MFM
Tm is longer than ax (-2T).

When recording, reproducing, or transmitting digital data using the M2 method, it is desirable to add a synchronization signal to ensure synchronization so that no DC component is generated.

- To provide a synchronization method that can reliably achieve synchronization without causing a DC component in a write signal when recording, reproducing, or transmitting data.

The synchronization method according to the present invention is characterized in that a signal that is inverted in synchronization corresponding to a width of 2.5 bits is used as a synchronization signal.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 3 to 5.

FIG. 3 is a block diagram showing an encoder that performs encoding while generating a synchronization signal based on the synchronization method according to the present invention. In the figure, each bit in a data bit series including information such as audio information is sequentially applied to a data input terminal of a buffer memory 1 at a predetermined period. Address signals and mode control signals for the buffer memory 1 are output from a control circuit 2. A clock C1 generated in synchronization with a data bit applied to a data input terminal of the buffer memory 1 is supplied to the control circuit 2 from a clock generation circuit 3. The control circuit 2 changes the address signal and the mode control signal so that data is sequentially written into the buffer memory 1 one bit at a time in synchronization with the clock C4, and at the same time the written data is sequentially read out one bit at a time. It is configured to generate a synchronization signal generation command signal at the start of readout and at the end of readout of data for one frame.

The data read from the buffer memory 1 is sequentially applied bit by bit to one input terminal of the multiplexer 4. The output of the data generator 5 is applied to the other input terminal of the multiplexer 4. The data generator 5 is configured to sequentially output 1 pin of predetermined data one pin at a time in response to a command, for example. A synchronization signal generation command signal output from the control circuit 2 is applied to a data switching control input terminal of the multiplexer 4 . multiplexer 4
According to the output of the control circuit 2, one of the output data of the buffer memory 1 and the output data of the data generator 5 is selectively outputted. The output of this multiplexer 4 is M
2 is applied to the data input terminal of the recording bit generator 6. A clock C1 is applied to the clock input terminal of the M2 recording bit generator 6. The M2 recording bit generator 6 generates, for example, ++O# and °゛0'' in the Ikabinod series.
It when the number of mutually adjacent °゛1'' between is an even number
A P(A) generator that generates an output P(A) that becomes O++, and an output P that becomes °'0'' when the cumulative charge up to the first 0'' of the 0'' surrounding II 1 jl is zero. The P(B) generator generates the P(B) signal, and the converter includes a ROM and the like and performs code conversion based on a conversion table as shown in the table below.

from the converter in the M2 recording bit generator 6 with α. ,
Data consisting of each bit of ho is output and applied to parallel input terminals of a 2-bit shift-renostaph.

The clock C1 is applied to the parallel cent clock input terminal of the /futoreno star 7, and the clock C2 outputted from the clock generation circuit 3 at the period of the clock C1 is applied to the shift clock input terminal of the shift register 7. . Two bits of output data from the converter in the M2 recording bit generator 6 are simultaneously sent to the shift register 7 by the clock C1. Thereafter, each bit a forming the data set in this shift register 7.

. The output of the gate signal generating circuit 9 is supplied to the other input terminal of the AND gate 8.

The gate signal generation circuit 9 includes a counter whose count value changes according to the clock C2 when, for example, the synchronization signal generation command signal output from the control circuit 2 is output, and when the count value of the counter changes to a predetermined value. The output is configured to be at a low level when the two are equal.

ANT) The output of gate 8 is the exclusive OR gate 10.
is applied to one input terminal of Exclusive OR Key-I
The output of -IO is applied to the D input terminal of the D-type furinozofurozo 11. A clock C2 is applied to the clock input terminal of the D-type furinozo 11.

The Q output of this D-type frizzo float 11 is applied to the other input terminal of the exclusive OR gate 10.

The exclusive OR gate 10 and the D-type Frisosophoroscope 11 form an NT'(,7) modulator, and the Q output of the D-type Frisosophore f11 is output as a write signal.

In the above configuration, when the control circuit 2 outputs the synchronization signal generation command signal, the data generator 5 sequentially outputs data [QllJ]IT one bit at a time starting from the most significant bit, as shown in FIG. 4G). shall be

Then, the M2 recording bit generator 6 sequentially outputs a bit sequence as shown in FIG. 40, two bits at a time. The output data of the M2 recording bit generator 6 is applied bit by bit sequentially to one input terminal of the A-NU) gate 8 by the shift register 7. The output of the shift register 7 is a signal obtained by combining a signal as shown in FIG. 4 0 corresponding to the data bit and a signal as shown in FIG. 4 0 corresponding to the clock bit. Here, in the gate signal generator 9, the count value of the counter is '7''' and I
If the output becomes low level when it becomes equal to tlall, as shown in Fig. 4, the AND gate
Then, the clock bits corresponding to the 7th and 13th bits from the most significant bit in the output data of the M2 recording bit generator 6 corresponding to [08]H are set to 0'', as shown in Figure 4 (■). Data is sequentially output one bit at a time.The output data of the AND gate 8 is applied to one input terminal of the exclusive OR gate 10, thereby writing data with an inversion interval of 2.5T as shown in FIG. I get a signal.

If this write signal is used as a synchronization signal to record, reproduce, or transmit digital data, and if decoding is started when a bit pattern in the synchronization signal is detected on the playback or reception side, decoding can be performed without errors. It is possible to obtain an analog signal that is almost the same as the original analog signal. In other words, the inversion interval is 2
．． The write signal shown in Figure 40 of 5T corresponds to the irregularity/main turn in the M2 modulation type, so unless dropouts occur, data and synchronization signals will not be misidentified, and synchronization will be achieved reliably. You can take it.

In the above explanation, the data generator 5 [08]
It is assumed that when T( is output and the count value of the counter in r-t signal generator 9 becomes equal to 7" and 13, the output becomes low level. As shown in (5), <[21,]H is output and the count value of the counter in the dirt signal generator 9 is II 9
II and '13'', the output may be set to a low level as shown in FIG. 5(G).

In this case, the M2 recording bit generator 6 sequentially outputs a bit sequence as shown in FIG. 5(c) two bits at a time. The output of the shift register is a signal obtained by combining a signal as shown in FIG. 50 corresponding to a data bit and a signal as shown in FIG. 50 corresponding to a clock bit. And A, NT) Figure 5 [F] from External Part 8
Data as shown in is outputted one bit at a time j]P.

By applying the output data of the A, ND gate 8 to one input terminal of the exclusive OR gate 10, a synchronizing signal with an inversion interval of 2.5T is obtained as shown in FIG. 50. .

Effects of the Invention As detailed above, the synchronization method according to the present invention uses a signal that is inverted a predetermined number of times with a period corresponding to 2.5 bit width as a synchronization signal, so that the accumulated charge in the synchronization signal section is zeroed and the DC component is Occurrence can be prevented. It's Kade.
Since the bit turn of the synchronization signal becomes the irregularity turn in the M2 system, synchronization can be reliably achieved without misidentification of the synchronization signal and data. Indeed, since the inversion interval in the synchronization signal section is less than or equal to the maximum inversion interval in the M2 system, self-synchronization does not become difficult. You can also add clock bits to the encoder “
A synchronizing signal can be easily generated by simply adding a circuit for setting the value to 0''.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of code conversion in the Ml"M method, FIG. 2 is a diagram showing an example of code conversion in the M2 method, and FIG. 3 is a diagram showing an example of code conversion in the M2 method. FIG. FIGS. 4 and 5 are circuit block diagrams showing an encoder that performs code conversion while illustrating the operation of each part of the apparatus shown in FIG. 3 when generating a synchronization signal.

Claims (2)

[Claims] (1) Bit value in a data series consisting of binary code
Converting a 0" bit into a 2-bit binary code having a bit pattern of either "00" or "10" according to the bit value of the bit immediately before that bit, and the data series A bit with a bit value "1" in is converted into a 2-bit binary code having a bit pattern of either "01" or "00" depending on the state of the bit string before that bit, and the resulting A synchronization method during data transmission using a signal obtained by making "1" of a data series correspond to inversion and "0" correspond to non-inversion, and is inverted a predetermined number of times at a period corresponding to 2.5 bit width. A synchronization method characterized by using a signal as a synchronization signal. (2) The synchronization method according to claim 1, wherein the predetermined circuit is 2.