JP2646113B2 - Machine check processing method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a machine check processing method and apparatus in a multiprocessor system having a plurality of scalar units and one vector unit. An object of the present invention is to provide a machine check processing method and apparatus capable of easily performing machine check separation. This type of system is provided by an individual part unique to each scalar unit and a scalar unit. When a machine check occurs in a common part, the occurrence of a machine check is reported to all scalar units. When a machine check occurs in an individual part, the corresponding scalar Report the occurrence of a machine check to the unit. As another method, when a machine check occurs in the common part, the occurrence of the machine check can be reported only to the scalar unit that has issued the vector instruction that is currently using the common part.

[Industrial applications]

The present invention relates to a machine check processing method and apparatus in a multiprocessor system including a plurality of scalar units and a vector unit that processes vector instructions from the plurality of scalar units.

[Conventional technology]

Figure 6 shows two scalar units and one vector
FIG. 2 is a block diagram of a dual scalar unit processor (DSUP) including a unit. In the figure, 100 is a main storage unit, 200 is a storage control unit, 300 and 301 are scalar units, 400 is a vector execution unit, 410 is a vector register, 421
Is the load pipeline, 422 is the store pipeline, 423 is the addition pipeline, 424 is the multiplication pipeline,
425 is a division pipeline, 500 is a vector control unit,
Reference numeral 600 denotes a vector unit, and L denotes a signal line.

Vector unit 600 is the vector execution unit 400
And a vector control unit 500. The vector control unit 500 is a unit for controlling a vector instruction. When receiving a vector instruction sent from a plurality of scalar units 300 and 301, the vector control unit 500 selects the vector instruction and transmits the selected vector instruction to the vector via a signal line L. Send to execution unit 400. The vector execution unit 400
It has a vector register 410, a load pipeline 421, a store pipeline 422, an addition pipeline 423, a multiplication pipeline 424, and a division pipeline 425.

In the dual scalar unit processor shown in FIG. 6, instructions from the main storage unit 100 are fetched by the scalar units 300 and 301. When the scalar units 300 and 301 fetch a scalar instruction, the scalar instruction itself is executed. When the vector instruction is fetched, the vector instruction is passed to the vector control unit 500.

The vector control unit 500 selects vector instructions sent from the plurality of scalar units 300 and 301, and passes the selected vector instructions to the vector execution unit 400.

FIG. 7 is a block diagram showing a configuration example of a vector control unit. In the figure, 510 and 511 are vector fetch stages, 520 is a switching circuit, 530 is a switching circuit control unit, 540 is a switching mode setting unit, 551 is a vector predecode stage, 552 is a vector waiting stage, and 5
Numeral 53 indicates a vector execution stage.

Vector instructions are input from scalar units 300 and 301 to respective vector fetch stage registers VFSR0 and VFSR1 via respective buses. When an instruction is fetched into the vector fetch stage register VFSR0, if the vector fetch buffer VFB0 is empty and the switching circuit 520 is switched to the scalar unit 300 side, the vector instruction becomes a vector fetch instruction. Vector predecode from stage register VFSR0
Sent to stage 551.

If the vector fetch buffer VFB0 contains a preceding instruction, or if the switching circuit 520 is a scalar unit 301
If the side is selected, the instruction in the vector fetch stage register VFSR0 is moved to the vector fetch buffer VFB0. Vector fetch buffer
The instruction contained in VFB0 is transferred from the first instruction to the vector predecode stage 551 when the switching circuit 520 selects the scalar unit 300. The same operation is performed for the vector instruction sent from the scalar unit 301.

Switching circuit control section 530 controls switching circuit 520.
The mode set by the mode setting switch of the switching mode setting unit 540 is input to the switching circuit control unit 530. Although not shown, the switching circuit control unit 530 includes a BUSY detection circuit for the 0 system and 1 system, and
Detection circuit output BUSY0 and 1-system BUSY detection circuit output BUS
Y1 is output to switching circuit 520. A signal indicating whether there is a 0-system instruction in vector fetch stage 510
FS0-BUSY0, vector predecode stage 55
A signal indicating whether there is a 0-system instruction in 1 is VPS-BUSY0, a signal indicating whether there is a 0-system instruction in the vector waiting stage 552 is VQS-BUSY0, and a 0-system instruction is present in the vector execution stage 553. VES-BUSY
Set to 0. Similarly, a signal indicating whether or not there is a system 1 instruction in the vector fetch stage 511 is defined as VFS1-BUSY1, and a signal indicating whether or not there is a system 1 instruction in the vector predecode stage 551 is defined as VPS1−BUSY1. −BUSY1, a signal indicating whether or not there is a 1-system instruction in the vector waiting stage 552 is defined as VQS-BUSY1, and a signal indicating whether or not there is a 1-system instruction in the vector execution stage 553 is defined as VES-BUSY1. .

In the mode state, the signals VFS0-BUSY0 and VPS-BUSY
0, VQS-BUSY0, OR of VES-BUSY0 becomes BUSY0,
Under the mode state, the signals VFS0-BUSY0, VPS-BUSY0, V
The result of ORing QS-BUSY0 is BUSY0, and the result of ORing signals VFS0-BUSY0 and VPS-BUSY0 is BU
It becomes SY0. Similarly, under mode conditions, signal VFS1
-BUSY1, VPS-BUSY1, VQS-BUSY1, and VES-BUSY1 are ORed and become BUSY1, and the signal VFS1-B
The result of ORing USY1, VPS-BUSY1, and VQS-BUSY1 becomes BUSY1, and under the state of the mode, the signals VFS1-BUSY1, VPS-BUS
The result of ORing Y1 is BUSY1.

The switching circuit 520 sends the instruction of the vector fetch stage 510 to the vector predecode stage 551 when both the signal BUSY0 and the signal BUSY1 are “0”, and outputs the signal B
When both USY0 and signal BUSY1 are “1”, the previous state is maintained. When signal BUSY0 is “1” and signal BUSY becomes “0”, vector fetch stage 510 is selected, and signal BUSY0 is “0”. When the signal BUSY1 becomes "1", the vector
Select stage 511. 6 and 7
The dual scalar unit processor shown in the figure is described in detail in Japanese Patent Application No. 63-140297 filed earlier by the present applicant.

In the dual scalar unit processor as shown in FIGS. 6 and 7, when a scalar unit generates a machine check within itself, the scalar unit performs the machine check processing within itself. The vector unit reports to the scalar unit when a machine check occurs in itself, and the machine check process is performed by the scalar unit.

[Problems to be solved by the invention]

In a duplicated scalar unit processor as described above, when a machine check occurs in a vector unit, it becomes a problem to which scalar unit the machine check is to be reported. Of course, if a machine check occurs due to a vector instruction sent from a scalar unit, the machine check must be reported to at least the scalar unit.

Ideally, the machine check detector of each circuit in the vector unit only needs to recognize which scalar unit caused the machine check to occur, but the circuit becomes complicated and the physical quantity becomes large. To increase. Originally, if the probability of a machine check is low,
It is not advisable to perform complicated control to check the machine that happened. Actually, even if a machine check report is issued to a scalar unit that has not caused a machine check, there is no theoretical inconsistency.

The present invention has been made in view of this point,
It consists of a plurality of scalar units that process scalar instructions and a vector unit that processes vector instructions sent from these scalar units, and the vector unit selects vector instructions sent from multiple scalar units. It is an object of the present invention to provide a machine check processing method and apparatus capable of easily performing machine check separation in a vector unit in a multiprocessor system that executes the same.

[Means for solving the problem]

FIG. 1 is a diagram for explaining the principle of the present invention. The present invention comprises a plurality of scalar units SU0,
SU1, ... SUn and these scalar units SU0, SU1, ... SUn
And a vector unit VU for processing a vector instruction sent from a multiprocessor system. The vector unit VU has a one-to-one correspondence with each of a plurality of scalar units, and individual parts VU-F0, VU-F1,..., VU-Fn used only by vector instructions from the corresponding scalar unit. , Common part VU used commonly by vector instructions from all scalar units
I.

A machine check processing method according to claim 1 is a machine check processing method in a multiprocessor system as shown in FIG. 1, wherein when a machine check occurs in a common part, all the scalar units are used. When a machine check occurs in an individual part, the machine check is reported to the corresponding scalar unit, and the machine check is not reported to other scalar units. It is a constituent requirement.

A machine check processing method according to claim 2 is a machine check processing method in a multiprocessor system as shown in FIG. 1, wherein when a machine check occurs in a common part, the common part is actually used. The scalar that issued the vector instruction
The configuration requirement is to report the machine check only to the unit, and not to report the machine check to the other scalar units. Is the same.

A machine check processing apparatus according to claim 3 is a machine check processing method in a multiprocessor system as shown in FIG. 1, wherein a machine check for a plurality of individual parts corresponding to each of the plurality of individual parts is provided. Output means, machine check output means for a common part corresponding to the common part, outputs of the machine check output means for a plurality of individual parts, and outputs of the machine check output means for the common part Machine check generation signal transfer means, wherein the machine check output means for each individual part is configured to output a machine check generation signal when a machine check occurs in the corresponding individual part, and the machine for the common part The check output means is configured to output a machine check occurrence signal when a machine check occurs in a common part. The machine check occurrence signal transfer means transfers the machine check occurrence signal to all scalar units when the machine check occurrence signal is output from the common part machine check output means, When a machine check generation signal is output from the machine check output means of (1), the machine check generation signal is transferred to the corresponding scalar unit, and the machine check generation signal is not transferred to other scalar units. It is a configuration requirement that it is configured as follows.

A machine check processing device according to claim 4 is a machine check processing method in a multiprocessor system as shown in FIG. 1, wherein a machine check for a plurality of individual parts corresponding to each of the plurality of individual parts is provided. Output means, machine check output means for common parts corresponding to common parts, output of machine check output means for a plurality of individual parts, output of machine check output means for common parts, use common parts Machine check generation signal transfer means to which a used scalar unit identification signal indicating from which scalar unit the vector instruction being executed is input is provided. Machine check output means for each individual part includes: It is configured to output a machine check occurrence signal when a machine check occurs in the corresponding individual part. The machine check output means is configured to output a machine check occurrence signal when a machine check occurs in the common part, and the machine check occurrence signal transfer means outputs the machine check occurrence signal from the machine check output means for the common part. If it is output, the machine check generation signal is transferred to the scalar unit determined by the scalar unit identification signal, and the machine check generation signal is not transferred to the other scalar units. When a machine check generation signal is output from the machine check output unit, transfer the machine check generation signal to the corresponding scalar unit and do not transfer the machine check generation signal to other scalar units. Is a configuration requirement.

〔Example〕

FIG. 2 is a diagram showing the configuration of a duplicated scalar unit processor in terms of the individual parts and common parts used by the scalar unit. In the figure, VU-F0 and VU-F1 indicate individual parts, and VU-I indicates a common part.

The individual part VU-F0 is a part of the vector unit 600 used only by the vector instruction from the scalar unit 300, and the individual part VU-F1 is used only by the vector instruction from the scalar unit 301 of the vector unit 600. This is the part to use. The common part VU-I consists of both scalars and
This is a part commonly used by the vector instructions from the units 300 and 301. The individual portion VU-F0 corresponds to the portion denoted by reference numeral 510 in FIG. 7, and the individual portion VU-F1 corresponds to the portion denoted by reference numeral 511 in FIG. The common part VU-I is denoted by reference numerals 551 to 5 in FIG.
53 and correspond to the reference numeral 400 in FIG.

FIG. 3 is a diagram showing an example of a circuit for transmitting a machine check generation signal from a vector unit to a scalar unit. In the figure, 560 to 562 and 570 and 5
71 is an OR circuit, MCH VU-F0 (1) to MCH VU-F0 (I)
Is a machine check generation signal sent from the I machine check detectors in the individual part VU-F0, MCH VU-F1
(1) to MCH VU-F1 (J) are J in the individual part VU-F1
The machine check generation signals MCH VU-I (1) to MCH VU-1 (K) sent from the machine check detection units are machine check generation signals sent from the K machine check detection units in the common part VU-I. Showing signals each.

Machine check occurrence signal MCH VU-F0 (1) to MCH
VU-F0 (I) is input to an OR circuit 560, and the machine check generation signals MCH VU-F1 (1) to MCH VU-F1 (J) are ORed.
Input to the circuit 561, the machine check generation signal MCH VU−
I (1) to MCH VU-1 (K) are input to the OR circuit 562. The output of the OR circuit 560 and the output of the OR circuit 562 are OR circuits 57
0, the output of the OR circuit 561 and the output of the OR circuit 562 become O
Input to R circuit 571. The output signal of the OR circuit 570 becomes the machine check generation signal to the 0-system scalar unit, and OR
The output signal of the circuit 571 becomes a machine check generation signal to the scalar unit of the first system.

In the embodiment shown in FIG. 3, since a machine check is reported to all scalar units when a machine check occurs in a common portion, the number of machine checks in the entire system may increase. The embodiment of FIG. 4 improves this point. In FIG.
580 and 581 are AND circuits, VU-I BUSY SU0 is a 0-system scalar
A signal indicating whether the vector instruction from the unit uses the common part VU-I. VU-I BUSY SU1 indicates whether the vector instruction from the system 1 scalar unit uses the common part VU-I. Each of the signals indicates whether or not the signal has been set.
The same reference numerals as those in FIG. 3 denote the same components.

Machine check occurrence signal MCH VU-F0 (1) to MCH
VU-F0 (I) is input to an OR circuit 560, and the machine check generation signals MCH VU-F1 (1) to MCH VU-F1 (J) are ORed.
Input to the circuit 561, the machine check generation signal MCH VU−
I (1) to MCH VU-I (K) are input to the OR circuit 562. Signal VU-I BUSY SU0 and output of OR circuit 562 are AND circuit
The signal VU-I BUSY SU1 and the output of the OR circuit 562 are input to the AND circuit 581. Output of OR circuit 560 and AND circuit
The output of 580 is input to the OR circuit 570, and the output of the OR circuit 561 and the output of the AND circuit 581 are input to the OR circuit 571. The output signal of the OR circuit 570 becomes a machine check generation signal to the 0-system scalar unit, and the output signal of the OR circuit 571 becomes a machine check generation signal to the 1-system scalar unit. In the embodiment shown in FIG. 4, when a machine check occurs while the vector instruction of the 0-system scalar unit uses the common part VU-I, the machine check is reported only to the 0-system scalar unit. When a machine check occurs while the vector instruction of the scalar unit of the first system uses the common part VU-I, the machine check is reported only to the scalar unit of the first system.

FIG. 5 is a diagram showing an example of a circuit for generating a signal indicating whether or not a vector instruction from the scalar unit 0 uses a common part. In the figure, reference numeral 590 denotes an OR circuit.

Signal VPS BUSY0, VQS BUSY0 and VES BUSY0 are OR circuit 590
And the output of the OR circuit 590 becomes the signal VU-I BUSY SU0. If the vector instruction of the scalar unit 0 uses the common part VU-I, VU-I BUSY SU0 = 1
become. Although not shown, a signal VU-I BUSY SU1 indicating whether or not the vector instruction of the scalar unit 301 of the first system uses the common part is generated in the same manner.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, an efficient machine check can be reported with a small amount of hardware and a simple circuit. In particular, when the probability of the machine check occurring in the common part is small, there is little fear that the result is unnecessarily reported to the scalar unit. Further, according to the method shown in FIG. 5, when the common part is used in a time-sharing manner by each scalar unit, the scalar 0 system
Since the use of the common part by the unit and the use of the common part by the scalar unit of the first system are almost exclusive, the machine check in the common part can be almost completely separated. In the above description, the scalar unit is 2
However, the present invention can be applied to a system having two or more scalar units.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, and FIG. 2 is a diagram showing a configuration of a duplicated scalar unit processor in terms of an individual part and a common part used by a scalar unit. FIG. 3 shows an example of a circuit for transmitting a machine check generation signal from a vector unit to a scalar unit. FIG. 4 shows a circuit for transmitting a machine check generation signal from a vector unit to a scalar unit. FIG. 5 is a diagram showing an example of a circuit for generating a signal indicating that a vector instruction from a scalar unit of the 0 system uses a common part.
FIG. 6 is a block diagram of a duplicated scalar unit processor having two scalar units and one vector unit, and FIG. 7 is a block diagram showing a configuration example of a vector control unit. 100: Main memory unit, 200: Memory control unit, 30
0 and 301: scalar unit, 400: vector execution unit, 410: vector register, 421: load
Pipeline, 422 …… Store pipeline, 423 ……
Addition pipeline, 424 …… Multiplication pipeline, 425 ……
Division pipeline, 500 …… Vector control unit, 510
511: vector fetch stage, 520: switching circuit, 530: switching circuit control unit, 540: switching mode setting unit, 551: vector pre-decoding stage, 552: vector waiting stage, 553 …… Vector execution stage, 560 or 562 …… OR circuit, 570 and 571 ……
OR circuit, 580 and 581 …… AND circuit, 590 …… OR circuit, 600…
... vector units.

Claims (4)

(57) [Claims] A plurality of scalar units for processing scalar instructions; and a vector unit for processing vector instructions sent from the scalar units, wherein the vector units are each one of the plurality of scalar units. A one-to-one correspondence with a corresponding scalar
A machine check processing method in a multiprocessor system in which a plurality of individual parts used only by vector instructions from a unit and a common part commonly used by vector instructions from all the scalar units are provided, When a machine check occurs in the common part, the machine check is reported to all of the above scalar units, and when a machine check occurs in the individual part, the machine check is performed for the corresponding scalar unit. A machine check processing method in which a report is made and a machine check is not reported to other scalar units. 2. A scalar unit comprising: a plurality of scalar units for processing scalar instructions; and a vector unit for processing vector instructions sent from the scalar units, wherein the vector unit is one of the scalar units. Each of them has a one-to-one correspondence and is divided into a plurality of individual parts used only by the vector instructions from the corresponding scalar unit and a common part used commonly by the vector instructions from all the scalar units. A machine check processing method in a multiprocessor system, wherein when a machine check occurs in the common part, the machine check is reported to a scalar unit that has issued a vector instruction using the common part, The machine check is not reported for other scalar units. When a machine check occurs in an individual part, a machine check is reported to the corresponding scalar unit, and no machine check is reported to other scalar units. Processing method. 3. A scalar unit comprising: a plurality of scalar units for processing a scalar instruction; and a vector unit for processing a vector instruction sent from the scalar unit, wherein the vector unit is one of the scalar units. Each of them has a one-to-one correspondence and is divided into a plurality of individual parts used only by the vector instructions from the corresponding scalar unit and a common part used commonly by the vector instructions from all the scalar units. A machine check processing method in a multiprocessor system, comprising: a machine check output unit for a plurality of individual parts corresponding to each of the plurality of individual parts; and a machine check output unit for a common part corresponding to the common part. And an output of the machine check output means for the plurality of individual parts, and a common part And a machine check generation signal transfer unit to which the output of the machine check output unit is input. The machine check output unit for each of the individual parts includes a machine check when a machine check occurs in the corresponding individual part. Wherein the machine check output means for the common part is configured to output a machine check occurrence signal when a machine check occurs in the common part; and When a machine check generation signal is output from the common part machine check output means, the machine check generation signal is transferred to all of the scalar units, and the machine check output means for the individual part outputs When a machine check occurrence signal is output, the corresponding scalar unit Shin check generating signals to transfer, machine check processing apparatus characterized by being configured not to forward the machine check occurrence signal to the other scalar unit. 4. A scalar unit comprising: a plurality of scalar units for processing a scalar instruction; and a vector unit for processing a vector instruction sent from the scalar unit, wherein the vector unit is one of the scalar units. Each of them has a one-to-one correspondence and is divided into a plurality of individual parts used only by the vector instructions from the corresponding scalar unit and a common part used commonly by the vector instructions from all the scalar units. A machine check processing method in a multiprocessor system, comprising: a machine check output unit for a plurality of individual parts corresponding to each of the plurality of individual parts; and a machine check output unit for a common part corresponding to the common part. The output of the machine check output means for the plurality of individual parts, Machine check generation signal transfer means to which an output of a machine check output means for a part and a used scalar unit identification signal indicating from which scalar unit the vector instruction using the common part is input Wherein the machine check output means for each individual part is configured to output a machine check occurrence signal when a machine check occurs in the corresponding individual part, and the machine check output means for the common part comprises And outputting a machine check occurrence signal when a machine check occurs in the common portion. The machine check occurrence signal transfer means outputs the machine check occurrence signal from the machine check output means for the common portion. If the scalar unit is determined by the scalar unit identification signal When the machine check output signal is output from the machine check output means for the individual part, the corresponding machine check output signal is not transferred to the other scalar units. A machine check processing device configured to transfer a machine check generation signal to a scalar unit and not to transfer a machine check generation signal to another scalar unit.