JP2643790B2 - emulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulator, and more particularly to an emulator used for debugging a target LSI (large-scale integrated circuit).

[0002]

2. Description of the Related Art Conventionally, in this type of emulator, an emulation unit uses the same chip as the target LSI for emulation of only peripheral hardware or the whole except for a memory.

In this case, a RAM built in the target LSI
An alternative memory composed of a general-purpose memory is used as a memory such as a ROM or a ROM, and the alternative memory is operated by a built-in power supply of the emulator.

[0004]

In the above-mentioned conventional emulator, since the substitute memory is composed of a general-purpose memory and operates with a power supply built in the emulator, the memory state of the target LSI at the time of power-on is emulated. There is a drawback that you can not.

Another drawback is that it is not possible to emulate the data holding state of the RAM after canceling the standby operation for reducing the power supply voltage, as in the case of turning on the power.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an emulator which eliminates the above-mentioned drawbacks, emulates a memory state when an internal state of an LSI changes, and improves debugging efficiency.

[0007]

An emulator according to the present invention is an emulator including an emulation unit for performing emulation by using the same chip as an integrated circuit to be tested, wherein a power supply of a user board is supplied to the same chip. Supply means and a built-in memory of the same chip.
Memory and the power supply to the same chip.
The internal memory in a standby state in which the pressure is reduced
And data for checking the data retention state of the
A replacement memory, a power-on reset operation of the same chip , a transition to the standby state , and the standby
Detection means for detecting at least one of the release of the state, and when the detection means detects one of the power-on reset operation , the transition to the standby state, and the release of the standby state, Built-in memory and said
Means for transferring data to and from the replacement memory .

[0008]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, emulation LSI2
Is composed of a RAM 3, a control register 4, another emulation circuit 5 such as a CPU, and an interface circuit 6.

The emulation unit 1 supplies a positive power supply voltage A and a negative power supply voltage B supplied from a user board (not shown) to the emulation LSI 2. Note that the rise or fall of the positive power supply voltage A and the negative power supply voltage B supplied from the user board to the emulation unit 1 are monitored by the power supply voltage monitoring circuit 8.

When the power supply voltage monitoring circuit 8 detects the rise or fall from the positive power supply voltage A and the negative power supply voltage B, it outputs a voltage rise detection signal C or a voltage fall detection signal D to the emulator control unit 9.

An emulator control unit 9 emulates an emulation LSI based on a program stored in the replacement memory 7.
The emulation is performed using 2. When the voltage rise detection signal C or the voltage fall detection signal D is input from the power supply voltage monitoring circuit 8, the emulator control unit 9 transfers the contents of the RAM 3 of the emulation LSI 2 to the replacement memory 7 via the interface circuit 6. Control.

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

When the power supply of the user board is turned on (power-on reset), the power supply voltage detecting circuit 8
When a voltage rise is detected from the negative power supply voltage (GND) B and the negative power supply voltage (GND) B, a voltage rise detection signal C is output to the emulator control unit 9.

When the emulator control section 9 obtains the voltage rise detection signal C, the RAM data in the emulation LSI 2 operating on the power supply of the user board (the initial value depends on the rise of the power supply of the user board), that is, the undefined state of the RAM 3 The data is controlled to be transferred to the replacement memory 7 via the interface circuit 6 to prepare for the start of emulation execution.

As a result, the memory state at power-on can be reproduced with the indefinite data in the RAM 3 stored in the substitute memory 7, and the memory state at power-on can be emulated.

Further, when shifting to the standby state where the power supply voltage Ru is reduced, similarly to the above operation, the fall of the voltage from the positive supply voltage A supply voltage detection circuit 8 and the negative power supply voltage B is detected Then, the voltage falling detection signal D is output to the emulator control unit 9.

When the emulator control unit 9 obtains the voltage falling detection signal D, the data in the replacement memory 7, that is, the data for confirming the data holding state of the RAM 3 in the standby state, is transmitted through the interface circuit 6. <br/> Control to transfer to RAM3 in simulation LSI2
To your to prepare for the start of the execution of the standby.

After that, when the power supply voltage detecting circuit 8 detects the rise of the voltage from the positive power supply voltage A and the negative power supply voltage B,
It outputs a voltage rise detection signal C to the emulator control unit 9. When the voltage rise detection signal C is obtained, the emulator control unit 9 controls the data in the RAM 3 in the emulation LSI 2 to be transferred to the replacement memory 7 via the interface circuit 6, and in the standby state, the RAM 3
Check if the data has been retained.

[0020] Thus, it is possible to emulate the RAM3 data holding state in the emulation LSI2 after the power supply voltage is out of Standby that will be reduced.

FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention. Referring to the figure, in another embodiment of the present invention, an evaluation LSI 10 is mounted on the emulation unit 1 and a gate circuit 11 and a control circuit 12 are provided in place of the power supply voltage detecting circuit 8 in one embodiment of the present invention shown in FIG. The configuration is similar to that of the example, and the same components are denoted by the same reference numerals.

The gate circuit 11 performs an OR operation on the inverted signal H of the standby control signal from the user substrate and the standby transition signal I from the emulation unit 1 by an OR gate 11 a, and outputs the operation result to the control circuit 12.

The gate circuit 11 has an OR gate 11b.
And an inverted signal E of a reset (RESET) signal from the user substrate and an inverted signal F of an NMI (non-maskable) signal.
And the OR of the external interrupt signal G and the inverted signal H of the standby control signal inverted by the inverter 11c, and outputs the operation result to the control circuit 12.

The control circuit 12 outputs an inverted signal E of the reset signal from the user substrate via the gate circuit 11 and NM
The inverted signal F of the I signal, the external interrupt signal G, the inverted signal H of the standby control signal, and the standby transition signal I from the emulation unit 1 are monitored, and the data transfer request signals J and K are determined according to the monitoring result. Is output to the emulator control unit 9.

FIG. 4 is a timing chart showing the operation of another embodiment of the present invention. FIG. 4A is a diagram showing the transition to the standby state by the standby transition signal I from the emulator unit 1 of FIG. 3, and FIG. 4B is the standby state by the inverted signal H of the standby control signal from the user board. FIG. The operation of another embodiment of the present invention will be described with reference to FIGS.

When the power supply of the user board is turned on (power-on reset), an inverted signal E of the reset signal is supplied from the reset circuit (not shown) on the user board to the gate circuit 11.
To the control circuit 12 via The control circuit 12 outputs a data transfer request signal J to the emulator control unit 9 at the rise of the inverted signal E of the reset signal.

When the emulator control unit 9 obtains the data transfer request signal J, the RAM data in the emulation LSI 2 which operates on the power supply of the user board (the initial value depends on the rise of the power supply of the user board), that is, the undefined state of the RAM 3 The data is controlled to be transferred to the replacement memory 7 via the interface circuit 6 to prepare for the start of emulation execution. Note that this operation is performed when N can release the standby state.
This is also performed when the inverted signal F of the MI signal and the external interrupt signal G are input.

As a result, the memory state at power-on can be reproduced with the undefined data in the RAM 3 stored in the replacement memory 7, and the memory state at power-on can be emulated.

Further, when shifting to the standby state where the power supply voltage Ru is reduced, the control circuit 12 is a standby transition signal I gate circuit from the emulation unit 1 11
And outputs a data transfer request signal K to the emulator control unit 9.

When the emulator control unit 9 obtains the data transfer request signal K, the data in the replacement memory 7, that is, the data for confirming the data holding state of the RAM 3 in the standby state is transmitted via the interface circuit 6. to transfer to RAM 3 in emulation LSI 2
Control and prepare for the start of standby execution (see FIG. 4A).

Thereafter, when the control circuit 12 detects the input of the inverted signal F of the NMI signal capable of canceling the standby state or the input of the external interrupt signal G, the data transfer request signal J is output to the emulator control section 9.

When the emulator control section 9 obtains the data transfer request signal J, the emulator control section 9 reads the RA in the emulation LSI 2
Control is performed to transfer the data of M3 to the replacement memory 7 via the interface circuit 6, and it is confirmed whether or not the data is held in the RAM 3 in the standby state.

[0033] Thus, it is possible to emulate the RAM3 data holding state in the emulation LSI2 after the power supply voltage is out of Standby that will be reduced.

When the standby control is performed by the inverted signal H of the standby control signal (the standby state when the low level is input), the control circuit 12 outputs the data transfer request signals K and J when the inverted signal H of the standby control signal falls and rises, respectively. It outputs to the emulator control unit 9 and performs the same operation as the above-mentioned operation (see FIG. 4B).

As described above, the emulation unit 1 using the same chip as the target LSI is operated by the power supply of the user board, and the power supply voltage is reduced immediately after the power-on reset.
By such transfer data to and from RAM3 and alternative memory 7 in the emulation LSI2 upon migration or standby state release to the standby state that will be, to emulate the RAM3 data state of the target LSI same characteristics Can be.

As a result, it is possible to improve the efficiency of the debugging work in which it is difficult for the user to perform strict debugging at the time of debugging, and to shorten the development period.

[0037]

As described above, according to the present invention, the power supply of the user board is supplied to the emulation unit for performing the emulation using the same chip as the integrated circuit to be tested, and the state change of the chip is detected. Sometimes, by reading and storing the contents of the built-in memory of the chip, it is possible to emulate the memory state when the internal state of the LSI changes, thereby improving the efficiency of debugging work.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of another embodiment of the present invention.

4A shows a transition to a standby state by a standby transition signal from the emulator unit of FIG. 3, and FIG. 4B shows a transition to a standby state by an inverted signal of a standby control signal from a user board; FIG.

[Explanation of symbols]

 Reference Signs List 1 emulation unit 2 emulation LSI 3 RAM 6 interface circuit 7 substitute memory 8 power supply voltage monitoring circuit 9 emulator control unit 11 gate circuit 12 control circuit

Claims (1)

(57) [Claims] 1. An emulator including an emulation unit for performing emulation using the same chip as an integrated circuit to be tested, comprising: means for supplying power of a user board to the same chip;
To the same chip as the contents read from the internal memory
The power supply voltage is reduced in the standby state.
Data for checking the data retention state of the storage memory.
An alternative memory for storing, a power-on reset operation of the same chip , a transition to the standby state , and
At least detecting means for detecting one, shifts the standby state to the standby state and the power-on reset operation by the detecting means of the release of the standby state
Means for transferring data between the built-in memory and the replacement memory when one of the cancellation is detected.