JP2638557B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2638557B2 JP2638557B2 JP9585595A JP9585595A JP2638557B2 JP 2638557 B2 JP2638557 B2 JP 2638557B2 JP 9585595 A JP9585595 A JP 9585595A JP 9585595 A JP9585595 A JP 9585595A JP 2638557 B2 JP2638557 B2 JP 2638557B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode pad
- solder
- semiconductor device
- semiconductor element
- notch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、電気絶縁基板上に半導体素子を搭載し、半導体素子
の電極端子に接続された配線回路の一端に外部端子とな
る半田バンプを形成してなる半導体装置に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for mounting a semiconductor element on an electrically insulating substrate and forming a solder bump as an external terminal at one end of a wiring circuit connected to an electrode terminal of the semiconductor element. The present invention relates to a semiconductor device comprising:
【０００２】[0002]
【従来の技術】電気絶縁基板の表面に半導体素子を搭載
し、基板裏面にマトリックス状に半田バンプを形成した
半導体装置は、通常ＢＧＡ（ball grid array ）と呼ば
れ、多ピン化に適した安価な実装技術として期待されて
いる。図５（ａ）は、この種の従来の構造を示す断面図
であり、図５（ｂ）はその電極パッド部の半田バンプを
除去した状態を示す平面図である。2. Description of the Related Art A semiconductor device in which a semiconductor element is mounted on the surface of an electrically insulating substrate and solder bumps are formed in a matrix on the rear surface of the substrate is usually called a BGA (ball grid array) and is inexpensive suitable for increasing the number of pins. Is expected as a new mounting technology. FIG. 5A is a cross-sectional view showing a conventional structure of this type, and FIG. 5B is a plan view showing a state where the solder bumps of the electrode pad portion have been removed.
【０００３】図５に示されるように、ガラス・エポキシ
樹脂基板などからなる電気絶縁基板５の表・裏面には銅
箔をエッチングして形成した配線回路４が設けられてい
る。表・裏面の配線回路４はスルーホール９を介して接
続されている。電気絶縁基板５の表面には半導体素子７
が搭載されており、該半導体素子の電極端子は配線回路
４の内部パッド部にワイヤ８を介して接続されている。
半導体素子７は封止樹脂６により封止されている。配線
回路４の一端に設けられた電極パッド２には半田バンプ
１１が形成されている。基板裏面は、半田バンプ形成個
所を除いて全面的にソルダーレジスト３により被覆され
ている。[0005] As shown in FIG. 5, a wiring circuit 4 formed by etching a copper foil is provided on the front and back surfaces of an electric insulating substrate 5 made of a glass epoxy resin substrate or the like. The wiring circuits 4 on the front and back sides are connected via through holes 9. A semiconductor element 7 is provided on the surface of the electrically insulating substrate 5.
Are mounted, and the electrode terminals of the semiconductor element are connected to internal pad portions of the wiring circuit 4 via wires 8.
The semiconductor element 7 is sealed with a sealing resin 6. A solder bump 11 is formed on the electrode pad 2 provided at one end of the wiring circuit 4. The back surface of the substrate is entirely covered with the solder resist 3 except for the portions where the solder bumps are formed.
【０００４】図６（ａ）〜（ｄ）は、半田バンプ１１の
形成過程を説明するための工程順斜視図である。図６
（ａ）に示されるように、電気絶縁基板５の表面は電極
パッド２の部分を除いてソルダーレジスト３により被覆
されている。なお、図には示されていないが、基板の反
対側の面には既に半導体素子が搭載され、封止樹脂によ
り封止されている。電極パッド２上にディスペンサー１
２を用いて、ロジン系フラックスなどの比較的粘性の高
いフラックス１０を塗布する〔図６（ｂ）〕。次に、真
空ピンセット１３を用いて球状半田１１ａを各電極パッ
ド２上に配置する〔図６（ｃ）〕。球状半田１１ａはフ
ラックス１０の粘性により仮付けされる。次に、半導体
装置を２００℃程度の温度でリフローし、球状半田１１
ａを電極パッド２に接着して半田バンプ１１を形成する
〔図６（ｄ）〕。FIGS. 6A to 6D are perspective views illustrating a process of forming the solder bumps 11 in the order of steps. FIG.
As shown in (a), the surface of the electrically insulating substrate 5 is covered with the solder resist 3 except for the electrode pads 2. Although not shown in the drawing, a semiconductor element is already mounted on the surface on the opposite side of the substrate and is sealed with a sealing resin. Dispenser 1 on electrode pad 2
2, a flux 10 having a relatively high viscosity such as a rosin-based flux is applied (FIG. 6B). Next, the spherical solder 11a is arranged on each electrode pad 2 using the vacuum tweezers 13 (FIG. 6C). The spherical solder 11a is temporarily attached due to the viscosity of the flux 10. Next, the semiconductor device is reflowed at a temperature of about 200 ° C.
a is bonded to the electrode pad 2 to form the solder bump 11 (FIG. 6D).
【０００５】半田バンプの形成方法としては、上記の外
に、ペースト状の共晶半田をスクリーン印刷で電極パッ
ド部に塗布しその後リフローする方法や、ワイヤー状の
共晶半田の先端を電気放電の熱で溶融させて球状にし、
その球状部を電極パッドに超音波を加えて接着するボー
ルボンディング法などがある。[0005] In addition to the above, solder bumps can be formed by applying paste-like eutectic solder to electrode pads by screen printing and then reflowing, or by applying electric discharge to the tip of wire-like eutectic solder. Melted with heat to form a sphere,
There is a ball bonding method in which the spherical portion is bonded to the electrode pad by applying ultrasonic waves.
【０００６】[0006]
【発明が解決しようとする課題】上記のように形成した
半田バンプでは、球状半田を電極パッドに取り付ける際
のリフロー時に、気化したフラックスがバンプ内に取り
込まれるれるため、ボイドが形成される。このボイド
は、図７（ａ）に示されるように、半導体装置がマザー
ボード１５等に実装される時に、溶融した半田内を上昇
するため、図７（ｂ）に示されるように、その殆どがバ
ンプの上部、すなわち電極パッドとの接合付近に集ま
る。In the solder bumps formed as described above, voids are formed because vaporized flux is taken into the bumps during reflow when the spherical solder is attached to the electrode pads. As shown in FIG. 7A, most of the voids rise in the molten solder when the semiconductor device is mounted on the motherboard 15 or the like, as shown in FIG. It gathers on the upper part of the bump, that is, near the junction with the electrode pad.
【０００７】その結果、半田バンプの電極パッドへの接
合強度が不足して信頼性の不足を招く。また、バンプの
表面付近に発生したボイド１４は高い吸湿性を示す。そ
して、マザーボード上に実装された半導体装置が温度サ
イクル（−４０℃５分ミニマム〜１２５℃５分ミニマム
の繰り返し）を受けた際に、ボイド中の気体、水分が膨
張・収縮を繰り返すため、バンプにクラックが生じてし
まう。さらに、ボイド１４中にトラップされた水分は、
部品交換等の再リフロー時に急激に膨張し溶融した半田
を周囲にまき散らすなどのトラブル発生の原因になって
いた。As a result, the bonding strength of the solder bump to the electrode pad is insufficient, resulting in insufficient reliability. Further, the voids 14 generated near the surface of the bump show high hygroscopicity. When the semiconductor device mounted on the motherboard undergoes a temperature cycle (minimum of −40 ° C. for 5 minutes to minimum of 125 ° C. for 5 minutes), the gas and moisture in the voids repeatedly expand and contract, so that the bumps are formed. Cracks will occur. Further, the moisture trapped in the void 14
At the time of re-reflow such as replacement of parts, it has caused troubles such as a sudden expansion and molten solder being scattered around.
【０００８】このようなボイドの除去方法として、特開
平３−２０８３４６号公報には、半田バンプが溶融して
いる状態で針を刺し、ガスを抜く方法が提案されてい
る。しかし、このような方法で、ボイドを除去しても、
マザーボード等に実装する際には、マザーボード側にフ
ラックスを塗布してリフローを行うことが多いため、リ
フロー時に気化したフラックスを新たに取り込むことに
なるため、上述の問題を解決することはできない。As a method of removing such voids, Japanese Patent Application Laid-Open No. 3-208346 proposes a method of removing gas by piercing a needle with a solder bump being melted. However, even if voids are removed in this way,
When mounting on a motherboard or the like, flux is often applied to the motherboard and reflow is performed. Therefore, the vaporized flux is newly taken in at the time of reflow, so that the above problem cannot be solved.
【０００９】本発明は、このような状況に鑑みてなされ
たものであって、その目的は、第１に、半田バンプにボ
イドが発生することがあってもその影響を極力少なくす
る手段を提供することであり、第２に、ボイドを有効に
除去しうる手段を提供することである。The present invention has been made in view of such circumstances, and a first object of the present invention is to provide a means for minimizing the influence of a void even if a solder bump is generated. Second, it is to provide a means capable of effectively removing voids.
【００１０】[0010]
【課題を解決するための手段】上記目的を達成するた
め、本発明によれば、電極パッド（２）と、半導体素子
の電極端子との接続部となる内部パッドとを有する配線
回路（４）が形成された電気絶縁基板（５）に半導体素
子（７）を搭載し、前記半導体素子の電極端子と前記配
線回路の内部パッドとを接続し、前記配線回路の電極パ
ッド上に金属ろう材の金属バンプ（１１）を外部端子と
して設けてなる半導体装置において、前記電極パッド
（２）には、導電材料の欠落した切欠部（１ａ、１ｂ）
が形成されていることを特徴とする半導体装置、が提供
される。そして、好ましくは、前記切欠部は、前記電極
パッドのほぼ中央に形成された円形状切欠部（１ａ）
と、これに連なりこれから該電極パッド外に達するよう
に形成された溝状切欠部（１ｂ）とを有している。According to the present invention, there is provided a wiring circuit (4) having an electrode pad (2) and an internal pad serving as a connection portion with an electrode terminal of a semiconductor element. A semiconductor element (7) is mounted on an electrically insulating substrate (5) on which is formed, and an electrode terminal of the semiconductor element is connected to an internal pad of the wiring circuit, and a metal brazing material is placed on the electrode pad of the wiring circuit. In a semiconductor device provided with a metal bump (11) as an external terminal, the electrode pad (2) has a cutout (1a, 1b) in which a conductive material is missing.
Are formed, and a semiconductor device is provided. Preferably, the notch is a circular notch (1a) formed substantially at the center of the electrode pad.
And a groove-shaped notch (1b) connected to the groove and formed so as to reach the outside of the electrode pad.
【００１１】[0011]
【実施例】次に、本発明の実施例について図面を参照に
して説明する。図１（ａ）は、本発明の第１の実施例の
半田バンプ形成前の状態を示す断面図であり、図１
（ｂ）は、図１（ａ）のＡで示した部分の平面図であ
る。また、図１（ｃ）は、図１（ｂ）のＡ−Ａ線での断
面図である。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a sectional view showing a state before the formation of solder bumps according to the first embodiment of the present invention.
FIG. 2B is a plan view of a portion indicated by A in FIG. FIG. 1C is a cross-sectional view taken along line AA of FIG. 1B.
【００１２】図１に示された半導体装置は次のように作
製される。ガラス・エポキシ樹脂を基板とする両面銅張
り積層板を出発材料として用いて、これにメッキ、フォ
トエッチングなどを施して、電気絶縁基板５の両面に配
線回路４が形成され、表・裏面の配線回路がスルーホー
ル９で接続されてなるチップキャリアを形成する。基板
の裏面を、電極パッド２の表面を露出させてソルダーレ
ジスト３にて被覆する。半導体素子７を基板上に搭載
し、半導体素子７の電極端子と配線回路４の一端部に設
けられた内部パッドとの間をワイヤ８を用いて接続す
る。しかる後、トランスファモールド法を用いて、封止
樹脂６により半導体素子７を封止する。The semiconductor device shown in FIG. 1 is manufactured as follows. Using a double-sided copper-clad laminate made of glass / epoxy resin as a starting material, this is subjected to plating, photoetching, and the like, so that wiring circuits 4 are formed on both sides of the electrically insulating substrate 5, and wiring on the front and back sides is formed. A chip carrier in which circuits are connected by through holes 9 is formed. The back surface of the substrate is covered with a solder resist 3 exposing the surface of the electrode pad 2. The semiconductor element 7 is mounted on a substrate, and an electrode terminal of the semiconductor element 7 is connected to an internal pad provided at one end of the wiring circuit 4 using a wire 8. Thereafter, the semiconductor element 7 is sealed with the sealing resin 6 by using a transfer molding method.
【００１３】電極パッド２には、そのほぼ中心に、円形
状切欠部１ａが形成されている。この電極パッド２上
に、従来と同様に、鉛／錫共晶合金からなる球状半田を
用いて半田バンプを形成する。このように構成された半
導体装置では、これをマザーボードなどに実装するため
に半田バンプ１１をリフローした際に、図２に示すよう
に、その中に巻き込んでいたボイド１４が切欠部１ａに
集中する。このようにボイド１４が中央に集中したこと
により、半田バンプ１１と電極パッド２との接合強度が
高まり、また吸湿性も低くなる。さらに、周辺部におい
て発生するクラックも生じにくくなり、温度サイクルを
経てもクラックの発生が抑制される。The electrode pad 2 has a circular notch 1a formed substantially at the center thereof. Solder bumps are formed on the electrode pads 2 by using a spherical solder made of a lead / tin eutectic alloy as in the related art. In the semiconductor device configured as described above, when the solder bumps 11 are reflowed for mounting the semiconductor device on a motherboard or the like, as shown in FIG. . Since the voids 14 are concentrated at the center, the bonding strength between the solder bumps 11 and the electrode pads 2 is increased, and the hygroscopicity is reduced. Further, cracks that occur in the peripheral portion are less likely to occur, and the occurrence of cracks is suppressed even after a temperature cycle.
【００１４】本実施例において、電極パッド２の大きさ
はφ０．６５ｍｍ、円形状切欠部１ａの大きさはφ０．
２ｍｍ、半田バンプ１１の最大径は設計値でφ０．７６
ｍｍである。また、本実施例の半導体装置では、２２５
個の半田バンプ１１がマトリックス状に配列されてい
る。この実施例の半導体装置を厚さ１．５ｍｍのガラス
・エポキシ基板（ＦＲ−４）に実装し、温度サイクル試
験を行ったところ、従来は６００サイクル程度から半田
バンプと半導体装置基体の電極パッドとの界面にクラッ
クが生じ不良となっていたのが、１０００サイクルまで
不良が発生しなくなった。In this embodiment, the size of the electrode pad 2 is φ0.65 mm, and the size of the circular notch 1a is φ0.
2 mm, maximum diameter of solder bump 11 is φ0.76 at design value
mm. In the semiconductor device of this embodiment, 225
The solder bumps 11 are arranged in a matrix. The semiconductor device of this embodiment was mounted on a glass epoxy substrate (FR-4) having a thickness of 1.5 mm and subjected to a temperature cycle test. Cracks occurred at the interface of the sample, and the defect did not occur, but the defect did not occur until 1000 cycles.
【００１５】図３は、本発明の第２の実施例を示す要部
拡大平面図である。本実施例では、電極パッド２の略中
央に円形状切欠部１ａが設けられ、さらにこの円形状切
欠部１ａから電極パッド２の外部にまでつながる溝状切
欠部１ｂが設けられている。FIG. 3 is an enlarged plan view of a main part showing a second embodiment of the present invention. In the present embodiment, a circular notch 1a is provided substantially at the center of the electrode pad 2, and a groove-shaped notch 1b extending from the circular notch 1a to the outside of the electrode pad 2 is provided.
【００１６】このような構造の切欠部を設けた場合に
は、半田バンプのリフロー時に中央の円形状切欠部１ａ
に集められたボイドは、溝状切欠部１ｂを介して外部に
放出され、ボイド自体が小さくなるため、半田バンプの
接合状態はより良好となり、また、温度サイクルでのク
ラック発生もより確実に抑制される。さらに、ボイドが
小さくなったことにより、半導体装置の交換のために再
リフローを行う際に、溶融した半田を周囲にまき散らす
トラブルも回避される。When a notch having such a structure is provided, the center circular notch 1a is formed at the time of reflow of the solder bump.
The voids collected at the surface are released to the outside through the groove-shaped notch 1b, and the voids themselves become smaller, so that the bonding state of the solder bumps becomes better, and the occurrence of cracks in the temperature cycle is more reliably suppressed. Is done. Further, since the void is reduced, a problem of dispersing the melted solder around when reflow is performed for replacement of the semiconductor device is also avoided.
【００１７】図４は、本発明の第３の実施例を示す要部
拡大平面図である。本実施例では、電極パッド２の略中
央に円形状切欠部１ａが設けられ、さらにこの円形状切
欠部１ａから電極パッド２の外部にまでつながる溝状切
欠部１ｂが配線回路側に設けられている。本実施例にお
いても、円形状切欠部１ａの外に溝状切欠部１ｂが設け
られたことにより、第２の実施例の場合と同様にボイド
の外部放出が可能になり、第２の実施例と同様の効果を
奏することができる。FIG. 4 is an enlarged plan view of a main part showing a third embodiment of the present invention. In this embodiment, a circular notch 1a is provided substantially at the center of the electrode pad 2, and a groove-like notch 1b extending from the circular notch 1a to the outside of the electrode pad 2 is provided on the wiring circuit side. I have. Also in the present embodiment, since the groove-shaped notch 1b is provided outside the circular notch 1a, the external discharge of the voids becomes possible as in the case of the second embodiment. The same effect as described above can be obtained.
【００１８】以上好ましい実施例について説明したが、
本発明はこれら実施例に限定されるものではなく、特許
請求の範囲に記載された範囲内において、適宜の変更が
可能なものである。例えば、実施例では、半田バンプを
鉛／錫共晶合金を用いて形成していたが、これに代え他
のろう材を用いてバンプを形成してもよい。また、実施
例では、半導体素子をフェースアップの状態で搭載し、
ワイヤボンディング方式で接続を行っていたが、この方
式に限らず、バンプを有するフリップチップをフェース
ダウン方式で接続するようにしてもよい。また、実施例
では電極パッド毎に一つの溝状切欠部を設けていたが、
各電極パッド毎に複数の溝状切欠部を設けるようにして
もよい。Although the preferred embodiment has been described above,
The present invention is not limited to these embodiments, but can be appropriately modified within the scope described in the claims. For example, in the embodiment, the solder bump is formed by using the lead / tin eutectic alloy, but the solder bump may be formed by using another brazing material instead. In the embodiment, the semiconductor element is mounted in a face-up state,
Although the connection is performed by the wire bonding method, the present invention is not limited to this method, and a flip chip having bumps may be connected by a face-down method. In the embodiment, one groove-shaped notch is provided for each electrode pad.
A plurality of groove-shaped notches may be provided for each electrode pad.
【００１９】[0019]
【発明の効果】以上説明したように、本発明の半導体装
置は、半田バンプを形成する電極パッドに切欠部を設け
たものであるので、半導体装置の実装時にバンプ内に巻
き込んだボイドを一個所に集中させることが可能にな
り、半田バンプの電極パッドへの接合強度を向上させる
ことができるとともに温度サイクル試験におけるクラッ
クの発生を抑制することができる。さらに、電極パッド
外に延びる溝状切欠部を設けた実施例によれば、ボイド
自体を減らすことができるようになり、上記の効果をよ
り確実なものとすることができる外、従来例で問題とな
っていた、ボイド中に吸収されていた水分が部品交換等
の再リフロー時に急激に膨張して溶融した半田を周囲に
まき散らすなどのトラブルを回避することが可能にな
る。As described above, in the semiconductor device of the present invention, the notch is provided in the electrode pad for forming the solder bump. Thus, the bonding strength of the solder bump to the electrode pad can be improved, and the occurrence of cracks in a temperature cycle test can be suppressed. Further, according to the embodiment in which the groove-shaped notch extending outside the electrode pad is provided, the void itself can be reduced, and the above-described effect can be more reliably achieved. Thus, it is possible to avoid troubles such as that the moisture absorbed in the voids expands abruptly at the time of reflow such as component replacement and the molten solder is scattered around.
【図１】本発明の第１の実施例の半田バンプ形成前の状
態を示す断面図と、その要部拡大平面図と、要部拡大断
面図。FIG. 1 is a sectional view showing a state before solder bump formation according to a first embodiment of the present invention, an enlarged plan view of a main part thereof, and an enlarged sectional view of a main part thereof.
【図２】本発明の第１の実施例の要部拡大断面図。FIG. 2 is an enlarged sectional view of a main part of the first embodiment of the present invention.
【図３】本発明の第２の実施例の半田バンプ形成前の状
態を示す要部拡大平面図。FIG. 3 is an enlarged plan view of a main part showing a state before solder bump formation according to a second embodiment of the present invention.
【図４】本発明の第３の実施例の半田バンプ形成前の状
態を示す要部拡大平面図。FIG. 4 is an enlarged plan view of a main part showing a state before a solder bump is formed according to a third embodiment of the present invention.
【図５】従来例の断面図とその要部拡大平面図。FIG. 5 is a cross-sectional view of a conventional example and an enlarged plan view of a main part thereof.
【図６】半田バンプの形成過程を説明するための工程順
斜視図。FIG. 6 is a perspective view illustrating a process of forming a solder bump in the order of steps.
【図７】半導体装置の実装状態示す側面図と従来例の問
題点を説明するための部分拡大断面図。FIG. 7 is a side view showing a mounting state of a semiconductor device and a partially enlarged cross-sectional view for explaining a problem of a conventional example.
１ａ 円形状切欠部 １ｂ 溝状切欠部 ２ 電極パッド ３ ソルダーレジスト ４ 配線回路 ５ 電気絶縁基板 ６ 封止樹脂 ７ 半導体素子 ８ ワイヤ ９ スルーホール １０ フラックス １１ 半田バンプ １１ａ 球状半田 １２ ディスペンサー １３ 真空ピンセット １４ ボイド １５ マザーボード DESCRIPTION OF SYMBOLS 1a Circular notch 1b Groove notch 2 Electrode pad 3 Solder resist 4 Wiring circuit 5 Electrical insulating substrate 6 Sealing resin 7 Semiconductor element 8 Wire 9 Through hole 10 Flux 11 Solder bump 11a Spherical solder 12 Dispenser 13 Vacuum tweezer 14 Void 15 Motherboard
Claims (5)
の接続部となる内部パッドとを有する配線回路が形成さ
れた電気絶縁基板に半導体素子を搭載し、前記半導体素
子の電極端子と前記配線回路の内部パッドとを接続し、
前記配線回路の電極パッド上に金属ろう材の金属バンプ
を外部端子として設けてなる半導体装置において、前記
電極パッドには、導電材料の欠落した切欠部が形成され
ていることを特徴とする半導体装置。1. A semiconductor element is mounted on an electric insulating substrate on which a wiring circuit having an electrode pad and an internal pad serving as a connection portion between the electrode terminal of the semiconductor element and the electrode terminal of the semiconductor element is provided. Connect to the internal pads of the circuit,
In a semiconductor device in which a metal bump made of a brazing metal is provided as an external terminal on an electrode pad of the wiring circuit, the electrode pad is formed with a cutout in which a conductive material is missing. .
ることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said brazing metal is a eutectic alloy of lead and tin.
央に円形状に形成されていることを特徴とする請求項１
記載の半導体装置。3. The device according to claim 1, wherein the notch is formed in a circular shape substantially at the center of the electrode pad.
13. The semiconductor device according to claim 1.
央に形成された円形状切欠部と、これに連なりこれから
該電極パッド外に達するように形成された溝状切欠部と
を有していることを特徴とする請求項１記載の半導体装
置。4. The notch includes a circular notch formed substantially at the center of the electrode pad, and a groove-shaped notch connected to the notch and extending from the electrode pad to reach the outside of the electrode pad. The semiconductor device according to claim 1, wherein
いてソルダレジストにより被覆されていることを特徴と
する請求項１記載の半導体装置。5. The semiconductor device according to claim 1, wherein the wiring circuit is covered with a solder resist except for the electrode pad portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9585595A JP2638557B2 (en) | 1995-03-30 | 1995-03-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9585595A JP2638557B2 (en) | 1995-03-30 | 1995-03-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08274211A JPH08274211A (en) | 1996-10-18 |
| JP2638557B2 true JP2638557B2 (en) | 1997-08-06 |
Family
ID=14148991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9585595A Expired - Lifetime JP2638557B2 (en) | 1995-03-30 | 1995-03-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2638557B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6341071B1 (en) * | 1999-03-19 | 2002-01-22 | International Business Machines Corporation | Stress relieved ball grid array package |
| JP2001160597A (en) * | 1999-11-30 | 2001-06-12 | Nec Corp | Semiconductor device, wiring substrate and method of manufacturing semiconductor device |
| US7141885B2 (en) * | 2002-02-13 | 2006-11-28 | Samsung Electronics Co., Ltd. | Wafer level package with air pads and manufacturing method thereof |
| JP2006205670A (en) | 2005-01-31 | 2006-08-10 | Brother Ind Ltd | Inkjet head |
| KR100596452B1 (en) * | 2005-03-22 | 2006-07-04 | 삼성전자주식회사 | Wafer level chip scale package having air gap between ball land and solder ball and manufacturing method thereof |
| JP2007258605A (en) | 2006-03-24 | 2007-10-04 | Toshiba Corp | Component incorporated printed wiring board, manufacturing method for component incorporated printed wiring board, and electronic equipment |
-
1995
- 1995-03-30 JP JP9585595A patent/JP2638557B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08274211A (en) | 1996-10-18 |
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