JP2002270629A - Electronic component and manufacturing method therefor - Google Patents

Electronic component and manufacturing method therefor

Info

Publication number
JP2002270629A
JP2002270629A JP2001063691A JP2001063691A JP2002270629A JP 2002270629 A JP2002270629 A JP 2002270629A JP 2001063691 A JP2001063691 A JP 2001063691A JP 2001063691 A JP2001063691 A JP 2001063691A JP 2002270629 A JP2002270629 A JP 2002270629A
Authority
JP
Japan
Prior art keywords
conductive film
bump
forming layer
film forming
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001063691A
Other languages
Japanese (ja)
Inventor
Yukihiro Ishimaru
幸宏 石丸
Tsutomu Mitani
力 三谷
Hiroteru Takezawa
弘輝 竹沢
Takashi Kitae
孝史 北江
Tosaku Nishiyama
東作 西山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001063691A priority Critical patent/JP2002270629A/en
Publication of JP2002270629A publication Critical patent/JP2002270629A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13011Shape comprising apertures or cavities, e.g. hollow bump
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13017Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/13076Plural core members being mutually engaged together, e.g. through inserts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00015Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve the problem of SBB method which uses wire bonding of inferior productivity for forming bumps in an electronic component and each formed bump by the wire bonding is in a port-belly shape, composed of a base and a smaller top than the base to result in that the transfer of adhesives to the bump being unstable, and hence the connection of a semiconductor device with a support base being apt to be unstable. SOLUTION: A bump 212 comprises a base 103 fixed to a substrate electrode 315, provided at a semiconductor device 101 and a top 104, formed at the substrate electrode 315 on the base 103 and has an outside diameter 105 of the top end of the top 104 at the electrode 315 larger than the outside diameter of the top 104 at the base 103. The bump holds surely a conductive adhesive with the top 104 to surely connect the semiconductor device 101 to the substrate electrode 315 and turning them into a mounting structure.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えば半導体装置
にバンプを有した電子部品およびその製造方法に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, an electronic component having a bump on a semiconductor device and a method of manufacturing the same.

【0002】[0002]

【従来の技術】近年の半導体部品を中心とした電子部品
の開発は、市場の要求から、軽薄短小の言葉に代表され
るように、小型化への方向性がますます進めれられてい
る。これらの要求にともない電子部品が小型化されてい
る中で、電子部品を接続する接合部分も小型化、狭ピッ
チ化されている。
2. Description of the Related Art In recent years, in the development of electronic components, mainly semiconductor components, the direction of miniaturization has been increasingly promoted, as typified by the words of light, thin and small, in accordance with market requirements. As electronic components have been miniaturized in response to these demands, junctions connecting the electronic components have also been miniaturized and narrowed in pitch.

【0003】ところで、半導体装置を代表するICチッ
プの実装方式として、従来のリードを用いた実装方式だ
けでなく、BGA(Ball Grid Array),CSP(Chip
scale package)と呼ばれる2次元のアレイ状に配列し
た外部接続電極を用いた実装形態が使用されている。こ
れらは、従来用いられていたQFP(Quad Flat packag
e)に比べると、外部接続電極がパッケージの裏面にあ
るので半導体装置のサイズが大幅に小型化されるという
利点がある。また外部接続電極のピッチもQFPでは0.
3mmや0.5mmに設定されるのに比べ1.0mmや0.8mmといった
比較的あらいものであって実装が容易となり、このため
新たな実装体として有用である。
By the way, as a mounting method of an IC chip representing a semiconductor device, not only a mounting method using a conventional lead but also a BGA (Ball Grid Array), a CSP (Chip)
A mounting form using external connection electrodes arranged in a two-dimensional array called a “scale package” is used. These are the QFPs (Quad Flat packags) conventionally used.
Compared with e), there is an advantage that the size of the semiconductor device is significantly reduced because the external connection electrodes are on the back surface of the package. Also, the pitch of the external connection electrodes is 0 in QFP.
It is relatively rough, such as 1.0 mm or 0.8 mm, compared to being set to 3 mm or 0.5 mm, and is easy to mount. Therefore, it is useful as a new mounting body.

【0004】しかし、BGA,CSPを用いた実装では
クリームハンダあるいはハンダボールを用いるため、接
続信頼性に優れている。しかし、外部接続電極間ピッチ
をファインにすると、リフロー時の基板のそりなどによ
りハンダが広がって隣接とショートする危険があるとい
う課題を有する。
[0004] However, mounting using BGA or CSP uses cream solder or solder balls, so that connection reliability is excellent. However, when the pitch between the external connection electrodes is made fine, there is a problem in that the solder may spread due to warpage of the substrate during reflow and the like, and there is a risk of short-circuiting with the adjacent one.

【0005】そこで半導体装置を基板に実装する方法と
して、SBB(Stud Bump Bonding)法(特公平07−05
0726、特開平4−335542)と呼ばれる実装形
態がある。ここで、SBB法で半導体装置にバンプを形成
する方法及びこの半導体装置を基板への実装する方法に
ついて、図10及び図11を用いて説明する。
Therefore, as a method of mounting a semiconductor device on a substrate, an SBB (Stud Bump Bonding) method (Japanese Patent Publication No.
0726, JP-A-4-335542). Here, a method for forming bumps on a semiconductor device by the SBB method and a method for mounting this semiconductor device on a substrate will be described with reference to FIGS.

【0006】このSBBはワイヤーボンディング法を用い
るもので、図10(a)に示すようにキャピラリ1003の孔1
004に通した銅製ワイヤ(以下「Auワイヤ」という)1
005の先端に熱エネルギーを加えてAuワイヤ1005を溶
融させてボール1006を形成する。なお、このボール1006
はガス炎または静電放電等によって形成される。
[0006] This SBB uses a wire bonding method, and as shown in FIG.
Copper wire passed through 004 (hereinafter referred to as “Au wire”) 1
Heat energy is applied to the tip of 005 to melt the Au wire 1005 to form a ball 1006. This ball 1006
Are formed by gas flame or electrostatic discharge.

【0007】このようにして形成したボール1006を、図
10(b)に示すように、半導体装置1001の電極パッド100
2にキャピラリ1003を介して熱圧着や超音波振動によっ
て固着させる。次に、図10(c)に示すように、Auワ
イヤ1005をキャピラリ1003の孔1004に通した状態でキャ
ピラリ1003を図10(d)に示すようにループ状軌道に移
動させ、図10(e)に示すように電極パッドに固着した
ボール1006の上部に逆U字状にAuワイヤ1005を残存さ
せてキャピラリ1003を降下してAuワイヤ1005を切断す
る。
As shown in FIG. 10B, the ball 1006 thus formed is connected to the electrode pad 100 of the semiconductor device 1001.
2 is fixed by thermocompression bonding or ultrasonic vibration via a capillary 1003. Next, as shown in FIG. 10C, while the Au wire 1005 is passed through the hole 1004 of the capillary 1003, the capillary 1003 is moved to a loop-shaped orbit as shown in FIG. As shown in ()), the Au wire 1005 is left in an inverted U-shape on the ball 1006 fixed to the electrode pad, and the capillary 1003 is lowered to cut the Au wire 1005.

【0008】以上の工程により、半導体装置1001の電極
パッド1002上に2段突出形状の突出接点が形成される。
Through the above steps, a two-stage projecting contact is formed on the electrode pad 1002 of the semiconductor device 1001.

【0009】このようにして半導体装置1 001の全ての
電極パッド1002上に突出接点を形成した後、図11(a)
に示すように、半導体装置1001を、表面が粗であるよう
な素材1110に押しつけるようにして突出接点をバンプ11
09とする。
After protruding contacts are formed on all the electrode pads 1002 of the semiconductor device 1001 in this manner, FIG.
As shown in FIG. 11, the semiconductor device 1001 is pressed against a material 1110 having a rough surface to
09.

【0010】この際に形成されるバンプ1109は、同図に
示すように、台座部900とこの台座部900より小さい頂上
部901からなる2段のダルマ形状であり、頂上部901は平
坦化してかつその表面が粗に形成されている。
The bump 1109 formed at this time has a two-stage Dharma shape composed of a pedestal portion 900 and a top portion 901 smaller than the pedestal portion 900, as shown in FIG. And the surface is formed roughly.

【0011】次に、図11(b)に示すように前記バンプ1
109を形成した半導体装置1001を、支持基材1112上に形
成したフェノキシレジンをバインダーとする導電性接着
剤接合層1111に接触させることにより、バンプ1109の頂
上部901に対して導電性接着剤接合層1111を転写する。
Next, as shown in FIG.
The semiconductor device 1001 formed with 109 is brought into contact with the conductive adhesive bonding layer 1111 using phenoxy resin as a binder formed on the supporting base material 1112, thereby bonding the conductive adhesive to the top 901 of the bump 1109. Transfer the layer 1111.

【0012】以上のようにして、電極パッド1102上のバ
ンプ1109に導電性接着剤接合層1111を形成した半導体装
置1001を、図11(c)に示すように、支持基礎1112の導
体パターン1113に位置合せして熱硬化等により固着する
ことによって、半導体装置1001と支持基材1112とが電気
的に接続される。
As described above, the semiconductor device 1001 in which the conductive adhesive bonding layer 1111 is formed on the bump 1109 on the electrode pad 1102 is connected to the conductive pattern 1113 of the support base 1112 as shown in FIG. The semiconductor device 1001 and the supporting base material 1112 are electrically connected by being aligned and fixed by thermosetting or the like.

【0013】[0013]

【発明が解決しようとする課題】上記従来のSBB法は部
品どうしの電気的な接続信頼性に優れ、かつファインピ
ッチに適する。しかし、2段突起の形成に際しワイヤー
ボンディング法を用いるために、生産性に劣るという課
題を有する。
The above-mentioned conventional SBB method has excellent electrical connection reliability between parts and is suitable for fine pitch. However, since the wire bonding method is used in forming the two-step projection, there is a problem that productivity is poor.

【0014】さらに、上記ワイヤーボンディング法を用
いて形成されるバンプ1109の形状は、台座部900とこの
台座部900より小さい頂上部901からなる2段のダルマ形
状であるため、バンプ1109に対する導電性接着剤あるい
はハンダペーストの転写が不安定になり、従って半導体
装置1001と支持基礎1112との電気的な接続が不安定にな
り易いという課題を有する。
Further, the shape of the bump 1109 formed by the wire bonding method is a two-stage Dharma shape composed of the pedestal portion 900 and the top 901 smaller than the pedestal portion 900. There is a problem that the transfer of the adhesive or the solder paste becomes unstable, so that the electrical connection between the semiconductor device 1001 and the support base 1112 tends to be unstable.

【0015】そこで本発明は、導電性接着剤の転写性に
優れたバンプを有する電子部品及びその製造方法の提供
を目的とする。
Accordingly, an object of the present invention is to provide an electronic component having a bump excellent in transferability of a conductive adhesive and a method of manufacturing the same.

【0016】[0016]

【課題を解決するための手段】本発明における電子部品
は、接続部品側に設けた電極に固着した台座部と、この
台座部における被接続部品側に一体的に形成される頂上
部とを備え、導電性接着剤を頂上部に付着した状態で前
記接続部品と被接続部品とを電気的に接続するためのバ
ンプを有し、このバンプの頂上部における被接続部品側
の先端部の外径が、頂上部における台座部側の外径に比
べて大きく形成されている。
An electronic component according to the present invention includes a pedestal portion fixed to an electrode provided on the connection component side, and a top formed integrally with the connected component side of the pedestal portion. A bump for electrically connecting the connection component and the component to be connected with the conductive adhesive adhered to the top, and an outer diameter of a tip of the top of the bump on the component to be connected side. However, it is formed larger than the outer diameter of the pedestal portion at the top.

【0017】また、前記バンプの頂上部における被接続
部品側の先端部の外径が台座部側の外径に比べて大きい
略円錐台状に形成されている。
Also, the outer diameter of the tip of the bump on the connected component side at the top of the bump is formed in a substantially truncated cone shape which is larger than the outer diameter of the pedestal side.

【0018】上記構成の電子部品において、接着剤をバ
ンプに転写する際に、頂上部の先端部の外径が底部の外
径より大きい形状であることから、一度転写された接着
剤は確実に頂上部に保持され、接続部品と被接続部品と
が確実に電気的に接続される。
In the electronic component having the above configuration, when the adhesive is transferred to the bumps, the outer diameter of the tip at the top is larger than the outer diameter of the bottom, so that the adhesive once transferred can be reliably applied. It is held on the top, and the connection component and the connection target component are reliably electrically connected.

【0019】上記電子部品は、接続部品側に設けた電極
に固着した台座部と、この台座部における被接続部品側
に一体的に形成される頂上部とを備え、導電性接着剤を
頂上部に付着した状態で前記接続部品と被接続部品とを
電気的に接続するためのバンプを有し、電極および接続
部品の表面に対して第一導電膜形成層を施す工程と、前
記電極の表面を露出させるよう第一導電膜形成層の電極
対向箇所に、バンプの台座部を形成するための第一穴を
形成する工程と、この第一穴および第一導電膜形成層の
表面に対して導電性材料を付着させて第一導電膜を形成
する工程と、前記第一穴に付着させた導電性材料を残し
他の部分の導電性材料を除去することで第一穴に台座部
を形成する工程と、前記第一導電膜形成層の表面および
前記台座部の表面に対して第二導電膜形成層を施す工程
と、前記台座部の表面を露出させるとともにバンプの頂
上部における被接続部品側の先端部の外径が頂上部にお
ける台座部側の外径に比べて大きくなるよう壁面を傾斜
させた第二穴を、第二導電膜形成層の台座部対向箇所に
形成する工程と、この第二穴および第二導電膜形成層の
表面に対して導電性材料を付着させて第二導電膜を形成
する工程と、前記第二穴に付着させた導電性材料を残し
他の部分の導電性材料を除去することで第二穴に頂上部
を形成する工程と、前記第一導電膜形成層および第二導
電膜形成層を除去する工程によって製造される。
The electronic component includes a pedestal portion fixed to an electrode provided on the connection component side, and a top portion integrally formed on the connected component side of the pedestal portion, and a conductive adhesive is applied to the top portion. Having a bump for electrically connecting the connecting component and the connected component in a state of being attached to the first conductive film forming layer on the surface of the electrode and the connecting component; and Forming a first hole for forming a pedestal portion of a bump at an electrode-facing portion of the first conductive film forming layer so as to expose the first conductive film forming layer; Forming a first conductive film by attaching a conductive material, and forming a pedestal portion in the first hole by removing the conductive material remaining in the first hole while leaving the conductive material attached to the first hole And the surface of the first conductive film forming layer and the surface of the pedestal portion The step of applying a second conductive film forming layer, and exposing the surface of the pedestal portion, the outer diameter of the tip of the connected component side at the top of the bump is smaller than the outer diameter of the pedestal portion at the top. A step of forming a second hole having an inclined wall surface so as to be larger at a position facing the pedestal portion of the second conductive film forming layer, and applying a conductive material to the surface of the second hole and the second conductive film forming layer. A step of forming a second conductive film by attaching, and a step of forming a top in the second hole by removing the conductive material of the other portion leaving the conductive material attached to the second hole, It is manufactured by a step of removing the first conductive film forming layer and the second conductive film forming layer.

【0020】また上記製造方法において、第一導電膜形
成層および第二導電膜形成層を絶縁層とし、第一導電膜
および第二導電膜を形成する際に、導電性材料をメッキ
により付着させ、第一導電膜および第二導電膜を除去す
る際に、導電性材料をエッチングにより除去し、頂上部
形成後に第一導電膜形成層および第二導電膜形成層を剥
離する。
In the above manufacturing method, the first conductive film forming layer and the second conductive film forming layer are used as insulating layers, and when forming the first conductive film and the second conductive film, a conductive material is adhered by plating. When removing the first conductive film and the second conductive film, the conductive material is removed by etching, and after forming the top, the first conductive film forming layer and the second conductive film forming layer are separated.

【0021】これら形成方法によれば、頂上部における
被接続部品側の先端部の外径が、頂上部における台座部
側の外径に比べて大きいバンプが一括して多数個形成さ
れるので、電子部品の生産性に優れる。
According to these forming methods, a large number of bumps are formed at once, since the outer diameter of the tip on the connected part side at the top is larger than the outer diameter of the pedestal at the top. Excellent electronic component productivity.

【0022】また本発明の電子部品は、接続部品側に設
けた電極に固着した台座部と、この台座部における被接
続部品側に一体的に形成される頂上部とを備え、導電性
接着剤を頂上部に付着した状態で前記接続部品と被接続
部品とを電気的に接続するためのバンプを有し、前記頂
上部が台座部の一側から被接続部品側に向けて拡径する
よう傾斜して形成されるとともに、他側に前記導電性接
着剤を保持するための保持凹部が形成されている。
Further, the electronic component of the present invention comprises a pedestal portion fixed to an electrode provided on the connection component side, and a top formed integrally with the connected component side of the pedestal portion, and a conductive adhesive Has a bump for electrically connecting the connection component and the connected component in a state where the connection portion is attached to the top portion, and the top portion expands in diameter from one side of the pedestal portion toward the connected component side. A holding concave portion for holding the conductive adhesive is formed on the other side while being formed at an angle.

【0023】上記構成の電子部品におけるバンプは、台
座部と頂上部の2段形状からなり、導電性接着剤を保持
するための保持凹部を有しているので、導電性接着剤が
バンプに転写される際に十分な転写量が確保され、接続
部品と被接続部品とが確実に電気的に接続される。
The bump in the electronic component having the above-described structure has a two-stage shape of a pedestal portion and a top, and has a holding concave portion for holding the conductive adhesive, so that the conductive adhesive is transferred to the bump. In this case, a sufficient transfer amount is secured, and the connection component and the connection target component are reliably electrically connected.

【0024】また、複数のバンプを同じ向きに形成する
ことで導電性接着剤は片側にのみ広がり反対側には広が
りにくいため、接続部品と被接続部品とを電気的に接続
する際に隣合うバンプに付着している導電性接着剤どう
しが接触してショートするのが防止される。
Further, since the conductive adhesive spreads only on one side and hardly spreads on the other side by forming a plurality of bumps in the same direction, the conductive adhesive is adjacent to each other when the connection component and the connection target component are electrically connected. It is possible to prevent the conductive adhesives attached to the bumps from coming into contact with each other and causing a short circuit.

【0025】さらに上記電子部品は、接続部品側に設け
た電極に固着した台座部と、この台座部における被接続
部品側に一体的に形成される頂上部とを備え、導電性接
着剤を頂上部に付着した状態で前記接続部品と被接続部
品とを電気的に接続するためのバンプを形成するため
に、電極および接続部品の表面に対して導電膜形成層を
施す工程と、前記台座部の表面を露出させるとともにバ
ンプの頂上部における被接続部品側の先端部の外径が頂
上部における台座部側の外径に比べて大きくなるよう壁
面を傾斜させた穴を、導電膜形成層の台座部対向箇所に
形成する工程と、この穴および導電膜形成層の表面に対
して導電性材料を付着させて導電膜を形成する工程と、
前記穴に施した導電性材料の一部を残し他の部分の導電
性材料を除去することで穴に対して台座部および頂上部
を形成する工程とで製造される。
Further, the electronic component includes a pedestal portion fixed to the electrode provided on the connection component side, and a top formed integrally with the connected component side of the pedestal portion, and a conductive adhesive is provided on the top. Applying a conductive film forming layer to the surface of the electrode and the connecting component to form a bump for electrically connecting the connecting component and the connected component in a state of being attached to the base, A hole whose wall is inclined such that the outer diameter of the tip of the connected component side at the top of the bump is larger than the outer diameter of the pedestal side at the top of the bump is exposed to the surface of the conductive film forming layer. A step of forming a conductive film by forming a conductive material on the surface of the hole and the conductive film forming layer;
A step of forming a pedestal portion and a top portion for the hole by removing a portion of the conductive material provided in the hole and removing the other portion of the conductive material.

【0026】また上記形成方法において、導電膜形成層
を絶縁層とし、導電膜をエッチングにより除去し、頂上
部形成後に導電膜形成層を剥離する。
In the above formation method, the conductive film forming layer is used as an insulating layer, the conductive film is removed by etching, and the conductive film forming layer is peeled off after the top is formed.

【0027】この形成方法によれば、頂上部における被
接続部品側の先端部の外径が、頂上部における台座部側
の外径に比べて大きいバンプが一括して多数個形成され
るので、生産性に優れる。
According to this forming method, a large number of bumps are formed at once, since the outer diameter of the tip portion on the connected component side at the top is larger than the outer diameter of the pedestal portion at the top. Excellent productivity.

【0028】[0028]

【発明の実施の形態】以下、本発明の実施の形態1ない
し実施の形態3を、図面に基づいて説明する。 (実施の形態1)図1ないし図3は、本発明の実施の形
態1を示すもので、図1はこの実施の形態の電子部品に
おけるバンプ212の断面形状を示している。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments 1 to 3 of the present invention will be described below with reference to the drawings. (Embodiment 1) FIGS. 1 to 3 show Embodiment 1 of the present invention, and FIG. 1 shows a cross-sectional shape of a bump 212 in an electronic component of this embodiment.

【0029】そしてこのバンプ212は、半導体装置101
(接続部品の一例)側に設けた外部接続端子102(電
極)に接続した円錐台形状の台座部103と、この台座部1
03に連続して一体的に形成されるとともに、後述の基板
電極315(被接続部品の一例)側に設けた頂上部104とを
備え、導電性接着剤を頂上部104に付着させた状態で、
前記半導体装置101と基板電極315とを電気的に接続する
ものである。
The bumps 212 are connected to the semiconductor device 101.
(An example of connecting parts) A frustum-shaped pedestal 103 connected to an external connection terminal 102 (electrode) provided on the side,
And a top portion 104 formed on the side of the substrate electrode 315 (an example of a part to be connected) described later, and a conductive adhesive is attached to the top portion 104. ,
The semiconductor device 101 and the substrate electrode 315 are electrically connected.

【0030】またこのバンプ212は、前述のように台座
部103と頂上部104の2段形状からなる凸型であり、かつ
頂上部104の先端部すなわち、基板電極315側の外径105
が、頂上部104における台座部103側の外径106に比べて
大きく形成されている。
As described above, the bump 212 has a convex shape having a two-stage shape of the pedestal portion 103 and the top portion 104, and has a tip portion of the top portion 104, that is, an outer diameter 105 on the substrate electrode 315 side.
However, it is formed larger than the outer diameter 106 on the pedestal portion 103 side of the top portion 104.

【0031】図2(a)〜(m)は、実施の形態1の電子部品
の製造方法を示した工程図である。以下、図面を用いて
この工程について説明する。
FIGS. 2A to 2M are process diagrams showing a method for manufacturing an electronic component according to the first embodiment. Hereinafter, this step will be described with reference to the drawings.

【0032】まず、図2(a)に示すように、電極すなわ
ち複数個の外部接続端子102を設けた半導体装置101に、
第一導電膜形成層(絶縁層としてのメッキレジスト)20
7aを形成する。第一導電膜形成層207aとしては、ドライ
フィルム形態のものでも、液状レジスト形態のものでも
良い。
First, as shown in FIG. 2A, a semiconductor device 101 provided with electrodes, that is, a plurality of external connection terminals 102,
First conductive film forming layer (plating resist as insulating layer) 20
Form 7a. The first conductive film forming layer 207a may be a dry film type or a liquid resist type.

【0033】次に、図2(b)に示すように、前記外部接
続端子102上の第一導電膜形成層207aに円錐台状の第一
穴208を加工し、外部接続端子102の表面を露出させる。
Next, as shown in FIG. 2B, a first hole 208 having a truncated cone shape is formed in the first conductive film forming layer 207a on the external connection terminal 102, and the surface of the external connection terminal 102 is formed. Expose.

【0034】なお、この第一穴208の形状としては、外
部接続端子102側の底面積の方が反対側の底面積よりも
小さくなるように形成する。すなわちこの第一穴208加
工に際しては、レーザーを用いることで外部接続端子10
2側の底面積の方が反対側の底面積よりも自ずと小さく
なるので、特別な装置や方法は不要である。また、光感
光性材料を用いた第一導電膜形成層207aとすれば、フォ
ト法で容易に第一穴208の加工をすることもできる。
The shape of the first hole 208 is formed such that the bottom area on the external connection terminal 102 side is smaller than the bottom area on the opposite side. In other words, when processing the first hole 208, the external connection terminal 10 is formed by using a laser.
The bottom area on the two sides is naturally smaller than the bottom area on the opposite side, so no special equipment or method is required. In addition, if the first conductive film forming layer 207a is formed using a photosensitive material, the first hole 208 can be easily processed by a photo method.

【0035】次に、図2(c)に示すように、第一穴208お
よび第一導電膜形成層207aの表面に対して第一導電膜20
9a(銅、アルミニウム、ニッケル等が用いられる)を形
成する。この導電性材料として、実施の形態1では銅を
用い、これをメッキ法により形成した。
Next, as shown in FIG. 2C, the first conductive film 20 is placed on the surface of the first hole 208 and the first conductive film forming layer 207a.
9a (copper, aluminum, nickel or the like is used) is formed. In the first embodiment, copper is used as the conductive material, and is formed by plating.

【0036】次に、図2(d)に示すように、エッチング
レジスト210を、第一導電膜209a上の第一穴208に対向す
る箇所に形成し、続いて図2(e)に示すように、エッチ
ングレジスト210を形成した部分以外の第一導電膜209a
をエッチングにより除去し、続いて図2(f)に示すよう
に、前記エッチングレジスト210を除去する。これによ
り第一穴208にバンプ212の台座部103が形成される。
Next, as shown in FIG. 2 (d), an etching resist 210 is formed on the first conductive film 209a at a position facing the first hole 208, and then as shown in FIG. 2 (e). The first conductive film 209a other than the portion where the etching resist 210 is formed
Is removed by etching, and then, as shown in FIG. 2 (f), the etching resist 210 is removed. As a result, the pedestal portion 103 of the bump 212 is formed in the first hole 208.

【0037】次に、図2(g)に示すように、第二導電膜
形成層(メッキレジスト)207bを、第一導電膜形成層20
7aの表面および第一穴208に形成した台座部103上に形成
する。そして、図2(h)に示すように、台座部103の表面
を露出させるよう、第一穴208より小さい円錐台状の第
二穴211を形成する。
Next, as shown in FIG. 2 (g), the second conductive film forming layer (plating resist) 207b is
7a and on the pedestal portion 103 formed in the first hole 208. Then, as shown in FIG. 2 (h), a frustum-shaped second hole 211 smaller than the first hole 208 is formed so as to expose the surface of the pedestal portion 103.

【0038】このとき第二穴211は、第一穴208と同様に
外部接続端子102側の底面積の方が反対側の底面積より
も小さくなるように形成するもので、第二穴211の壁面
は、基板電極315に向けて拡径された傾斜面とする。
At this time, like the first hole 208, the second hole 211 is formed so that the bottom area on the side of the external connection terminal 102 is smaller than the bottom area on the opposite side. The wall surface is an inclined surface whose diameter is increased toward the substrate electrode 315.

【0039】第二穴211の形成に際しては、例えば上記
と同様にレーザーを用いて形成することで、特別な装置
や方法は不要である。
When the second hole 211 is formed, for example, by using a laser in the same manner as described above, a special device or method is unnecessary.

【0040】次に、図2(i)に示すように第二穴211およ
び第二導電膜形成層207bの表面に対して導電性材料をメ
ッキ法により付着させることで第二導電膜209bを形成
し、図2(j)に示すように、エッチングレジスト210を、
第二導電膜209b上の第二穴211に対向する箇所に形成す
る。
Next, as shown in FIG. 2I, a second conductive film 209b is formed by applying a conductive material to the second hole 211 and the surface of the second conductive film forming layer 207b by plating. Then, as shown in FIG. 2 (j), the etching resist 210 is
The second conductive film 209b is formed at a position facing the second hole 211.

【0041】続いて図2(k)に示すように、エッチング
レジスト210を形成した部分以外の導電性材料をエッチ
ングにより除去し、図2(l)に示すように、前記エッチ
ングレジスト210を除去することで、第二穴211に頂上部
104を形成する。
Subsequently, as shown in FIG. 2K, the conductive material other than the portion where the etching resist 210 is formed is removed by etching, and as shown in FIG. 2L, the etching resist 210 is removed. By the top of the second hole 211
Form 104.

【0042】最後に図2(m)に示すように、第一導電膜
形成層207aおよび第二導電膜形成層207bを剥離すること
で、前述のような台座部103と頂上部104の2段形状から
なり頂上部104の先端部の外径105が台座部103側の外径1
06に比べて大きいバンプ212を形成した電子部品が製造
される。
Finally, as shown in FIG. 2 (m), the first conductive film forming layer 207a and the second conductive film forming layer 207b are peeled off, so that the above-described pedestal portion 103 and top 104 are formed in two steps. The outer diameter 105 of the tip of the top 104 is the outer diameter 1 of the base 103 side.
An electronic component having bumps 212 larger than 06 is manufactured.

【0043】このようにして複数個のバンプ212を並べ
て形成した半導体装置101を、図3(a)に示すようにバン
プ212を下方に向けた状態で、導電性接着剤接合層313
(ハンダ接合層でもよい)が塗布された基板314の上方
に位置させ、図3(b)に示すように、バンプ212の頂上部
104全体が導電性接着剤接合層313中に浸漬するよう半導
体装置101を降下させ、続いて図3(c)に示すように、半
導体装置101を上方に引き上げる。
The semiconductor device 101 formed by arranging the plurality of bumps 212 in this manner is placed on the conductive adhesive bonding layer 313 with the bumps 212 facing downward as shown in FIG.
(It may be a solder bonding layer) is positioned above the substrate 314 to which the solder bonding layer is applied, and as shown in FIG.
The semiconductor device 101 is lowered so that the entire 104 is immersed in the conductive adhesive bonding layer 313, and then the semiconductor device 101 is pulled upward as shown in FIG.

【0044】この一連の工程によって、一度で導電性接
着剤(導電性接着剤接合層313)が複数のバンプ212の頂
上部104に転写され、バンプ212および導電性接着剤から
なる電極構造が形成される。
Through this series of steps, the conductive adhesive (conductive adhesive bonding layer 313) is transferred onto the tops 104 of the plurality of bumps 212 at once, and an electrode structure composed of the bumps 212 and the conductive adhesive is formed. Is done.

【0045】そしてバンプ212の形状は、頂上部104の先
端部の外径105が底部の外径106より大きい形状であるた
め、転写された導電性接着剤がバンプ212の頂上部104で
確実に保持された電極構造となる。
The shape of the bump 212 is such that the outer diameter 105 at the tip of the top 104 is larger than the outer diameter 106 at the bottom, so that the transferred conductive adhesive is surely formed at the top 104 of the bump 212. The electrode structure is held.

【0046】その後、図3(d)に示すように、各バンプ2
12と基板電極315側の端子電極316とを位置合わせして、
基板電極315に対して半導体装置101を実装し、導電性接
着剤を硬化させることで両者を電気的に接続し、電子部
品の実装体とする。
Thereafter, as shown in FIG.
Align the 12 and the terminal electrode 316 on the substrate electrode 315 side,
The semiconductor device 101 is mounted on the substrate electrode 315, and the conductive adhesive is cured to electrically connect the semiconductor device 101 and the electronic device, thereby forming a mounted electronic component.

【0047】なお、必要に応じて図3(e)に示すよう
に、封止樹脂317で各バンプ212を含めた電極構造部分を
封止してもよい。
As shown in FIG. 3E, the electrode structure including the bumps 212 may be sealed with a sealing resin 317 as needed.

【0048】以上のように本発明の実施の形態1におけ
る電子部品は、各バンプ212が、頂上部104の先端部の外
径105が底部の外径106より大きい形状であるため、導電
性接着剤を確実に保持して、半導体装置101と基板電極3
15とが確実に接続された実装体となる。
As described above, in the electronic component according to the first embodiment of the present invention, since each bump 212 has a shape in which the outer diameter 105 at the tip of the top 104 is larger than the outer diameter 106 at the bottom, the conductive adhesive The semiconductor device 101 and the substrate electrode 3
15 is a mounted body that is securely connected.

【0049】図3(f)は、実施の形態1における電子部
品の電極構造の拡大図であり、バンプ212と導電性接着
剤を有して、導電性接着剤が2段形状からなる凸型のバ
ンプ212のにのみ形成されている。これにより、バンプ2
12を形成したピッチで接合部が形成できるため、ファイ
ンピッチの電極構造が容易に得られる。
FIG. 3F is an enlarged view of the electrode structure of the electronic component according to the first embodiment. The electrode structure has a bump 212 and a conductive adhesive, and the conductive adhesive has a two-stage convex shape. Are formed only on the bumps 212 of FIG. This allows bump 2
Since the joints can be formed at the pitch of 12, a fine pitch electrode structure can be easily obtained.

【0050】また本実施の形態1では、バンプ212を形
成するに当たりワイヤーボンディング法を用いることな
く、上記のように一度の工程でもってバンプ212を多数
個形成できるため、電子部品の生産性を向上させること
ができる。
Also, in the first embodiment, the number of bumps 212 can be formed in a single step as described above without using a wire bonding method in forming the bumps 212, thereby improving the productivity of electronic components. Can be done.

【0051】なお、実施の形態1ではメッキ法を用いて
バンプ212を形成したため、図1に示したように頂上部1
04に対向する第二導電膜209bは、他の部分に比べて成
長が遅れることで中心が凹んだ形状になる傾向があり、
従って中心が凹んだ形状の頂上部10 4となるが、この構
成では各バンプ212の頂上部104に働く端子電極316に対
しての接触圧力が大きくなり、頂上部104と端子電極316
との間にある導電性接着剤を押しつぶすので、頂上部10
4の端子電極316表面が平坦な場合に比べ、半導体装置10
1と基板電極315との電気的接続をさらに確実にすること
ができる。
In the first embodiment, since the bumps 212 are formed by using the plating method, as shown in FIG.
The second conductive film 209b opposed to 04 tends to have a shape with a concave center due to slower growth than other portions,
Therefore, the top portion 104 has a concave shape at the center, but in this configuration, the contact pressure applied to the terminal electrode 316 acting on the top portion 104 of each bump 212 increases, and the top portion 104 and the terminal electrode 316
Crush the conductive adhesive between
4 compared to the case where the surface of the terminal electrode 316 is flat.
Electrical connection between 1 and substrate electrode 315 can be further ensured.

【0052】なお本実施の形態1では、バンプ212に導
電性接着剤を転写して半導体装置101と基板電極315を接
続したが、ハンダペーストを用いてリフローソルダリン
グにより実装を行っても良い。
In the first embodiment, the semiconductor device 101 and the substrate electrode 315 are connected by transferring a conductive adhesive to the bump 212, but mounting may be performed by reflow soldering using a solder paste.

【0053】(実施の形態2)次に、図4および図5に
基づいて実施の形態2を説明する。図4は実施の形態2
の電子部品におけるバンプ212の断面形状を示す。図5
(a)〜(i)は、実施の形態2における電子部品の製造方法
を示した工程図である。以下実施の形態2を、図面を用
いて説明する。
(Second Embodiment) Next, a second embodiment will be described with reference to FIGS. FIG. 4 shows the second embodiment.
3 shows a cross-sectional shape of a bump 212 in the electronic component of FIG. FIG.
(a)-(i) is a process drawing showing a method for manufacturing an electronic component in the second embodiment. Embodiment 2 will be described below with reference to the drawings.

【0054】まず、図5(a)に示すように、半導体装置1
01の表面およびそこに設けられた外部接続端子102の表
面を覆うように導電膜209を形成する。導電膜209として
は、実施の形態1と同様に、銅を用いてメッキ法により
形成した。
First, as shown in FIG.
A conductive film 209 is formed so as to cover the surface of 01 and the surface of the external connection terminal 102 provided thereon. The conductive film 209 was formed by a plating method using copper as in Embodiment 1.

【0055】次に、図5(b)に示すように、導電膜209上
に第一導電膜形成層(メッキレジスト)207aを形成す
る。この第一導電膜形成層207aとしては、ドライフィル
ム形態のものでも、液状レジスト形態のものでも良い。
Next, as shown in FIG. 5B, a first conductive film forming layer (plating resist) 207a is formed on the conductive film 209. The first conductive film forming layer 207a may be a dry film type or a liquid resist type.

【0056】次に、図5(c)に示すように前記外部接続
端子102上の前記第一導電膜形成層207aに第一穴208を加
工し、外部接続端子102を被覆する導電膜209を露出させ
る。
Next, as shown in FIG. 5C, a first hole 208 is formed in the first conductive film forming layer 207a on the external connection terminal 102, and a conductive film 209 covering the external connection terminal 102 is formed. Expose.

【0057】第一穴208は、外部接続端子102側の底面積
の方が反対側の底面積よりも小さくなるように加工す
る。すなわち、第一穴208の加工に際しては、レーザー
を用いることで外部接続端子102側の底面積の方が反対
側の底面積よりも自ずと小さくなるので、特別な装置や
方法が不要になる。また、光感光性材料を用いた第一導
電膜形成層207aとすれば、フォト法で容易に第一穴208
の加工をすることもできる。
The first hole 208 is processed so that the bottom area on the side of the external connection terminal 102 is smaller than the bottom area on the opposite side. That is, when the first hole 208 is processed, the bottom area on the side of the external connection terminal 102 is naturally smaller than the bottom area on the opposite side by using a laser, so that a special device or method is not required. Further, if the first conductive film forming layer 207a is formed using a photosensitive material, the first hole 208 can be easily formed by a photo method.
Can also be processed.

【0058】次に、図5(d)に示すように、前記第一穴2
08に対し導電性材料を付着させて(メッキ法を用いる)
バンプ212の台座部103を形成する。
Next, as shown in FIG.
Apply conductive material to 08 (using plating method)
The pedestal 103 of the bump 212 is formed.

【0059】続いて図5(e)に示すように、この台座部1
03の表面および第一導電膜形成層207aの表面に対して第
二導電膜形成層207bを形成し、図5(f)に示すように、
第二導電膜形成層207bの台座部103に対向する箇所に第
一穴208より小さな第二穴211を形成し、台座部103の表
面を露出させる。
Subsequently, as shown in FIG.
A second conductive film forming layer 207b is formed on the surface of the substrate 03 and the surface of the first conductive film forming layer 207a, and as shown in FIG.
A second hole 211 smaller than the first hole 208 is formed in a portion of the second conductive film forming layer 207b facing the pedestal portion 103 to expose the surface of the pedestal portion 103.

【0060】次に、図5(g)に示すように、第二穴211に
メッキ法によりバンプ212の頂上部104を形成する。この
とき頂上部104の表面はその中心に向けて凸となるよう
形成する。続いて図5(h)に示すように、第一導電膜形
成層207aおよび第二導電膜形成層207bを剥離する。
Next, as shown in FIG. 5 (g), the top 104 of the bump 212 is formed in the second hole 211 by plating. At this time, the surface of the top 104 is formed so as to be convex toward the center. Subsequently, as shown in FIG. 5H, the first conductive film forming layer 207a and the second conductive film forming layer 207b are separated.

【0061】最後に図5(i)に示すように、エッチング
により最初に形成した導電膜209の一部を除去すること
で、台座部103と頂上部104の2段形状からなる凸型で、
かつ頂上部104の先端部の外径105が底部の外径106より
大きいバンプ212が複数個形成される。
Finally, as shown in FIG. 5I, by removing a part of the conductive film 209 formed first by etching, a convex shape having a two-stage shape of the pedestal 103 and the top 104 is obtained.
Further, a plurality of bumps 212 are formed in which the outer diameter 105 at the tip of the top 104 is larger than the outer diameter 106 at the bottom.

【0062】以下、図示は省略するが、実施の形態1と
同様に、複数個のバンプ212が並べて形成された半導体
装置101を、バンプ212を下方に向けた状態で、導電性接
着剤接合層313(ハンダ接合層でもよい)が塗布された
基板314の上方に位置させ、バンプ212の頂上部104全体
が導電性接着剤接合層313中に浸漬するよう半導体装置1
01を降下させ、続いて半導体装置101を上方に引き上げ
るといった動作により、一度に複数個のバンプ212の頂
上部104に導電性接着が転写され、電子部品が製造され
る。
Although not shown, as in the first embodiment, the semiconductor device 101 having the plurality of bumps 212 arranged side by side is mounted on the conductive adhesive bonding layer with the bumps 212 facing downward. The semiconductor device 1 is positioned above the substrate 314 on which the solder bonding layer 313 (which may be a solder bonding layer) is applied, and the entire top 104 of the bump 212 is immersed in the conductive adhesive bonding layer 313.
By lowering the semiconductor device 101 and then lifting the semiconductor device 101 upward, the conductive adhesive is transferred to the tops 104 of the plurality of bumps 212 at once, and an electronic component is manufactured.

【0063】そして、この電子部品におけるバンプ212
の形状は、頂上部104の先端部の外径105が底部の外径10
6より大きい形状であるため、転写された導電性接着剤
がバンプ212の頂上部104で確実に保持される。
Then, the bump 212 of this electronic component is
The outer diameter 105 at the tip of the top 104 is equal to the outer diameter 10 at the bottom.
Since the shape is larger than 6, the transferred conductive adhesive is securely held at the top 104 of the bump 212.

【0064】最後に各バンプ212と基板電極315側の端子
電極316とを位置合わせして基板電極315に半導体装置10
1を実装し、導電性接着剤を硬化させることで両者を電
気的に接続することで実装体を製造する。
Finally, each bump 212 and the terminal electrode 316 on the substrate electrode 315 side are aligned, and the semiconductor device 10
1 is mounted, and the conductive adhesive is cured to electrically connect the two, thereby manufacturing a mounted body.

【0065】本実施の形態2では、バンプ212の形成の
際に、メッキ法を用いて第一穴208および第二穴211にの
み導電性材料を付着させて、図4に示したように頂上部
104の中央部分が突出するようにバンプ212を形成した
が、この構成においても頂上部104の中央部分に働く接
触圧力が大きくなり、頂上部104と端子電極316との間に
ある導電性接着剤を押しつぶすことで、半導体装置101
と基板電極315との電気的接続が確実になる。
In the second embodiment, at the time of forming the bump 212, a conductive material is applied only to the first hole 208 and the second hole 211 by using a plating method, and as shown in FIG. Department
Although the bump 212 was formed so that the central portion of the 104 protruded, the contact pressure acting on the central portion of the apex 104 also increased in this configuration, and the conductive adhesive between the apex 104 and the terminal electrode 316 was formed. Crushing the semiconductor device 101
And the substrate electrode 315 can be electrically connected.

【0066】また実施の形態1では、第一穴208および
第二穴211、さらに第一導電膜形成層207aおよび第二導
電膜形成層207bを形成し、第一穴208および第二穴211に
対向する部分以外の導電性材料を除去したが、実施の形
態2では第一穴208および第二穴211にのみ導電性材料を
付着させることでバンプ212を形成するので、導電性材
料を除去する必要がなく、従って、実施の形態1に比べ
て電子部品の生産性が向上する。他の作用効果は上記実
施の形態1と同様であるので省略する。
In the first embodiment, the first hole 208 and the second hole 211, the first conductive film forming layer 207a and the second conductive film forming layer 207b are formed, and the first hole 208 and the second hole 211 are formed. Although the conductive material other than the opposing portion was removed, in the second embodiment, the bump 212 is formed by attaching the conductive material only to the first hole 208 and the second hole 211, so that the conductive material is removed. There is no need, and therefore, the productivity of the electronic component is improved as compared with the first embodiment. Other functions and effects are the same as those in the first embodiment, and a description thereof will not be repeated.

【0067】(実施の形態3)次に、図6ないし図9に
基づいて本発明における実施の形態3を説明する。図6
は実施の形態3の電子部品におけるバンプ212の断面形
状を示したものである。そしてこのバンプ212は、台座
部603と頂上部604の2段形状からなる断面略L字形状で
ある。
Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIGS. FIG.
Shows the cross-sectional shape of the bump 212 in the electronic component according to the third embodiment. The bump 212 has a substantially L-shaped cross section including a two-stage shape including a pedestal portion 603 and a top portion 604.

【0068】図7(a)〜(g)は、実施の形態3おける電子
部品の製造方法を示した工程図である。以下、図面を用
いてその製造方法を説明する。
FIGS. 7A to 7G are process diagrams showing a method for manufacturing an electronic component according to the third embodiment. Hereinafter, the manufacturing method will be described with reference to the drawings.

【0069】まず、図7(a)に示すように、複数個の外
部接続端子102を設けた半導体装置101に導電膜形成層20
7を形成し、図7(b)に示すように、前記外部接続端子10
2に対向する部分の導電膜形成層207に円錐台状の穴208
を形成して、各外部接続端子102の表面を露出させる。
First, as shown in FIG. 7A, a semiconductor device 101 provided with a plurality of external connection terminals 102 is provided with a conductive film forming layer 20.
7 and the external connection terminal 10 is formed as shown in FIG.
A truncated conical hole 208 is formed in the conductive film forming layer
Is formed, and the surface of each external connection terminal 102 is exposed.

【0070】次に、図7(c)に示すように、導電膜形成
層207および各穴208に対して導電性材料を付着させて導
電膜209を形成する。続いて、図7(d)に示すように、エ
ッチングレジスト210を、導電膜209上の穴208に対向す
る箇所の一部に、各穴208の周方向に向けて途中まで形
成する。
Next, as shown in FIG. 7C, a conductive material is attached to the conductive film forming layer 207 and each hole 208 to form a conductive film 209. Subsequently, as shown in FIG. 7D, an etching resist 210 is partially formed in a part of the conductive film 209 facing the holes 208 in a circumferential direction of each hole 208.

【0071】続いて図7(e)に示すように、エッチング
レジスト210を形成した部分以外の導電性材料をエッチ
ングにより除去し、図7(f)に示すように前記エッチン
グレジスト210を除去する。最後に図7(g)に示すよう
に、導電膜形成層207を剥離することで、複数個のバン
プ212を有した電子部品が形成される。
Subsequently, as shown in FIG. 7E, the conductive material other than the portion where the etching resist 210 is formed is removed by etching, and as shown in FIG. 7F, the etching resist 210 is removed. Finally, as shown in FIG. 7G, by peeling the conductive film forming layer 207, an electronic component having a plurality of bumps 212 is formed.

【0072】なおバンプ212の形状は、台座部603および
頂上部604からなる2段形状で、台座部603の他側に導電
性接着剤を保持するための保持凹部604aを有した断面略
L字型であればよく、その大きさ等については任意であ
る。
The shape of the bump 212 is a two-stage shape consisting of a pedestal portion 603 and a top portion 604, and has a substantially cross-sectional shape having a holding recess 604a for holding a conductive adhesive on the other side of the pedestal portion 603.
Any shape may be used as long as it is L-shaped.

【0073】そしてバンプ212の形状は、エッチングレ
ジスト210と導電膜209との接触面積によって決定される
もので、図8(a)〜(d)に示すように、これらバンプ212
は場合に応じて必要な形状に形成する。なお、図8はエ
ッチングレジスト210と導電膜209との接触面積が小さい
順に並べたものである。
The shape of the bumps 212 is determined by the contact area between the etching resist 210 and the conductive film 209. As shown in FIGS.
Is formed in a required shape according to the case. Note that FIG. 8 is arranged in ascending order of the contact area between the etching resist 210 and the conductive film 209.

【0074】以下図示を一部省略するが、半導体装置10
1と基板電極315との接続するための工程を説明する。
Although not shown in the drawings, the semiconductor device 10
A process for connecting the substrate electrode 315 to the substrate 1 will be described.

【0075】すなわち、複数個のバンプ212が並べて形
成された半導体装置101を、バンプ212を下方に向けた状
態で、導電性接着剤接合層(あるいはハンダ接合層でも
よい)313が塗布された基板の上方に位置させ、バンプ2
12の頂上部604全体が導電性接着剤接合層313中に浸漬す
るよう半導体装置101を降下させ、半導体装置101を上方
に引き上げる。
That is, the semiconductor device 101 on which the plurality of bumps 212 are formed is placed on a substrate coated with a conductive adhesive bonding layer (or a solder bonding layer) 313 with the bumps 212 facing downward. And bump 2
The semiconductor device 101 is lowered so that the entire top 604 of the semiconductor device 12 is immersed in the conductive adhesive bonding layer 313, and the semiconductor device 101 is pulled up.

【0076】この一連の工程において、一度に導電性接
着剤(導電性接着剤接合層313)が複数のバンプ212の頂
上部604に転写されて、図9(a)に示すような半導体装置
101の電極構造となり、図9(b)に示すように、各バンプ
212と基板電極315側の端子電極316とを位置合わせして
基板電極315に半導体装置101を実装し、導電性接着剤を
硬化させることで両者を電気的に接続することで実装体
を製造する。
In this series of steps, the conductive adhesive (conductive adhesive bonding layer 313) is transferred onto the tops 604 of the plurality of bumps 212 at one time, and the semiconductor device as shown in FIG.
As shown in FIG. 9B, each of the bumps has an electrode structure of 101.
The semiconductor device 101 is mounted on the substrate electrode 315 by aligning the 212 and the terminal electrode 316 on the substrate electrode 315 side, and the conductive adhesive is cured to electrically connect the two, thereby manufacturing a mounted body. .

【0077】そして、一度の工程で導電性接着剤が複数
のバンプ212の頂上部604に転写されるので、生産性に優
れる。
Since the conductive adhesive is transferred to the tops 604 of the plurality of bumps 212 in one process, the productivity is excellent.

【0078】この電極構造は、バンプ212と導電性接着
剤とからなる電極構造であり、導電性接着剤(あるいは
ハンダ接合層)が頂上部604を中心に2段形状からなる
凸型のバンプ212にのみ形成されている。これにより、
バンプ212のピッチで接合部が形成でき、従ってファイ
ンピッチの電極構造が得られる。
This electrode structure is an electrode structure composed of the bump 212 and a conductive adhesive. The conductive adhesive (or the solder bonding layer) is a two-stage convex bump 212 with the top 604 as the center. Is formed only. This allows
Bonding portions can be formed at the pitch of the bumps 212, and thus a fine pitch electrode structure can be obtained.

【0079】またこの実施の形態3によれば、導電性接
着剤がバンプ212に転写される際、バンプ212は台座部60
3と頂上部604の2段形状であるのに加え、導電性接着剤
を保持するための保持凹部604aを有しているので、バン
プ212に対して導電性接着剤の転写量を十分に確保する
ことができ、従って、半導体装置101と基板電極315とを
確実に接続することができる。
According to the third embodiment, when the conductive adhesive is transferred to the bumps 212, the bumps 212
In addition to the two-stage shape of 3 and the top 604, the holding recess 604a for holding the conductive adhesive ensures a sufficient amount of conductive adhesive transferred to the bump 212. Therefore, the semiconductor device 101 and the substrate electrode 315 can be reliably connected.

【0080】さらに、各バンプ212の形状を断面L字形状
とし、これらバンプ212を同じ向きに形成するようにす
れば、半導体装置101と基板電極315とを接続する際に導
電性接着剤は片側にのみ広がり反対側には広がりにくい
ため、隣合うバンプ212に付着した導電性接着剤どうし
が接触してショートするのを防止することができる。
Further, if the shape of each of the bumps 212 is L-shaped in section and these bumps 212 are formed in the same direction, the conductive adhesive can be connected to one side when the semiconductor device 101 and the substrate electrode 315 are connected. Therefore, the conductive adhesives attached to the adjacent bumps 212 can be prevented from coming into contact with each other and causing a short circuit.

【0081】なお上記各実施の形態では、半導体装置10
1側にバンプ212を形成したがこれに限定されるものでは
なく、上記構成のバンプ212を基板電極315側に形成して
電子部品を製造してもよい。
In each of the above embodiments, the semiconductor device 10
Although the bump 212 is formed on one side, the present invention is not limited to this, and the electronic component may be manufactured by forming the bump 212 having the above-described configuration on the substrate electrode 315 side.

【0082】また上記各実施の形態では、バンプ212を
半導体装置101に形成して電子部品としたが、これに限
定されるものではなく、上記各実施の形態と同様の構成
のバンプ212を半導体装置101以外の装置に設けて電子部
品としてもよいことは勿論である。何れの場合も上記各
実施の形態と同様の作用効果を奏し得る。
In each of the above embodiments, the bump 212 is formed on the semiconductor device 101 to be an electronic component. However, the present invention is not limited to this. Needless to say, electronic components may be provided in devices other than the device 101. In any case, the same operation and effect as those of the above embodiments can be obtained.

【0083】[0083]

【発明の効果】以上の説明から明らかなように、本発明
は、接続部品側に設けた電極に固着した台座部と、この
台座部における被接続部品側に一体的に形成される頂上
部とを備え、頂上部における被接続部品側の先端部の外
径が、頂上部における台座部側の外径に比べて大きく形
成されたバンプを有する電子部品であるので、バンプの
頂上部で導電性接着剤が確実に保持され、従って、前記
接続部品と被接続部品とを確実に電気的に接続すること
ができる。
As is apparent from the above description, the present invention provides a pedestal portion fixed to an electrode provided on a connecting component side, and a top formed integrally with the connected component side of the pedestal portion. An electronic component having a bump formed such that the outer diameter of the tip on the connected component side at the top is larger than the outer diameter of the pedestal side at the top, so that the conductive property is higher at the top of the bump. The adhesive is securely held, so that the connection component and the connected component can be reliably electrically connected.

【0084】また、電極の表面に対して導電膜形成層を
施し、電極の表面を露出させるよう導電膜形成層の電極
対向箇所に穴を形成し、この穴に対して導電性材料を付
着させるようにして台座部および頂上部を形成するの
で、電子部品の製造に際して多数のバンプを一括して形
成することができ、従って電子部品の生産性を向上させ
ることができる。
Further, a conductive film forming layer is applied to the surface of the electrode, a hole is formed in the conductive film forming layer at a position facing the electrode so as to expose the surface of the electrode, and a conductive material is attached to the hole. Since the pedestal portion and the top portion are formed in this manner, a large number of bumps can be formed at once in the manufacture of an electronic component, and therefore, the productivity of the electronic component can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態1を示す電子部品における
バンプの断面図である。
FIG. 1 is a sectional view of a bump in an electronic component according to a first embodiment of the present invention.

【図2】同じく電子部品の製造方法を示す工程図であ
る。
FIG. 2 is a process chart showing a method for manufacturing an electronic component.

【図3】同じく半導体装置と基板電極との接続方法を示
す工程図である。
FIG. 3 is a process chart showing a method for connecting a semiconductor device and a substrate electrode.

【図4】本発明の実施の形態2を示す電子部品における
バンプの断面図である。
FIG. 4 is a sectional view of a bump in an electronic component according to a second embodiment of the present invention.

【図5】同じく電子部品の製造方法を示す工程図であ
る。
FIG. 5 is a process chart showing a method for manufacturing an electronic component.

【図6】本発明の実施の形態3を示す電子部品における
バンプの断面図である。
FIG. 6 is a sectional view of a bump in an electronic component according to a third embodiment of the present invention.

【図7】同じく電子部品の製造方法を示す工程図であ
る。
FIG. 7 is a process drawing showing a method for manufacturing an electronic component.

【図8】同じく電子部品におけるバンプの形状例を表す
斜視図である。
FIG. 8 is a perspective view showing an example of the shape of a bump in the electronic component.

【図9】同じく電子部品のバンプに転写された導電性接
着剤の付着状態を示す断面図である。
FIG. 9 is a cross-sectional view showing an attached state of a conductive adhesive transferred to a bump of the electronic component.

【図10】従来のSBB法での電子部品におけるバンプの形
成方法を示す工程図である。
FIG. 10 is a process chart showing a method of forming bumps on an electronic component by the conventional SBB method.

【図11】同じく半導体装置と基板電極とを接続方法を
示す工程図である。
FIG. 11 is a process drawing showing a method of connecting the semiconductor device and the substrate electrode.

【符号の説明】[Explanation of symbols]

101 半導体装置 102 外部接続端子 103 台座部 104 頂上部 207a 第一導電膜形成層 207b 第二導電膜形成層 208 第一穴 209a 第一導電膜 209b 第二導電膜 210 エッチングレジスト 211 第二穴 212 バンプ 313 導電性接着剤接合層 315 基板電極 316 端子電極 101 Semiconductor device 102 External connection terminal 103 Pedestal 104 Top top 207a First conductive film forming layer 207b Second conductive film forming layer 208 First hole 209a First conductive film 209b Second conductive film 210 Etching resist 211 Second hole 212 Bump 313 Conductive adhesive bonding layer 315 Board electrode 316 Terminal electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 竹沢 弘輝 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 北江 孝史 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 西山 東作 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5F044 KK17 LL07  ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroki Takezawa 1006 Kadoma Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Takashi Kitae 1006 Kadoma Kadoma, Kadoma City, Osaka Pref. 72) Inventor Tosaku Nishiyama 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 5F044 KK17 LL07

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 接続部品側に設けた電極に固着した台座
部と、この台座部における被接続部品側に一体的に形成
される頂上部とを備え、導電性接着剤を頂上部に付着し
た状態で前記接続部品と被接続部品とを電気的に接続す
るためのバンプを有する電子部品であって、 前記バンプの頂上部における被接続部品側の先端部の外
径が、頂上部における台座部側の外径に比べて大きく形
成されたことを特徴とする電子部品。
1. A pedestal portion fixed to an electrode provided on a connecting component side, and a top portion integrally formed on the connected component side of the pedestal portion, wherein a conductive adhesive is attached to the top portion. An electronic component having a bump for electrically connecting the connecting component and the connected component in a state, wherein an outer diameter of a tip of the connected component side at the top of the bump has a pedestal portion at the top. An electronic component characterized by being formed larger than the outer diameter of the side.
【請求項2】 バンプの頂上部における被接続部品側の
先端部の外径が台座部側の外径に比べて大きい略円錐台
状に形成されたことを特徴とする請求項1記載の電子部
品。
2. The electronic device according to claim 1, wherein the outer diameter of the tip of the bump on the connected component side at the top of the bump is formed in a substantially truncated cone shape larger than the outer diameter of the pedestal portion. parts.
【請求項3】 接続部品側に設けた電極に固着した台座
部と、この台座部における被接続部品側に一体的に形成
される頂上部とを備え、導電性接着剤を頂上部に付着し
た状態で前記接続部品と被接続部品とを電気的に接続す
るためのバンプを有する電子部品を製造するための製造
方法であって、 電極および接続部品の表面に対して第一導電膜形成層を
施す工程と、前記電極の表面を露出させるよう第一導電
膜形成層の電極対向箇所に、バンプの台座部を形成する
ための第一穴を形成する工程と、この第一穴および第一
導電膜形成層の表面に対して導電性材料を付着させて第
一導電膜を形成する工程と、前記第一穴に付着させた導
電性材料を残し他の部分の導電性材料を除去することで
第一穴に台座部を形成する工程と、前記第一導電膜形成
層の表面および前記台座部の表面に対して第二導電膜形
成層を施す工程と、 前記台座部の表面を露出させるとともにバンプの頂上部
における被接続部品側の先端部の外径が頂上部における
台座部側の外径に比べて大きくなるよう壁面を傾斜させ
た第二穴を、第二導電膜形成層の台座部対向箇所に形成
する工程と、 この第二穴および第二導電膜形成層の表面に対して導電
性材料を付着させて第二導電膜を形成する工程と、前記
第二穴に付着させた導電性材料を残し他の部分の導電性
材料を除去することで第二穴に頂上部を形成する工程
と、前記第一導電膜形成層および第二導電膜形成層を除
去する工程とを有したことを特徴とする電子部品の製造
方法。
3. A pedestal portion fixed to an electrode provided on the connection component side, and a top portion integrally formed on the connected component side of the pedestal portion, and a conductive adhesive is attached to the top portion. A method for manufacturing an electronic component having a bump for electrically connecting the connecting component and the connected component in a state, wherein the first conductive film forming layer is formed on the surface of the electrode and the connecting component. Applying, and forming a first hole for forming a pedestal portion of the bump at an electrode facing portion of the first conductive film forming layer so as to expose the surface of the electrode, and forming the first hole and the first conductive film. A step of forming a first conductive film by attaching a conductive material to the surface of the film forming layer, and removing the conductive material in the other portion while leaving the conductive material attached to the first hole. Forming a pedestal portion in the first hole, and forming the first conductive film forming layer Applying a second conductive film forming layer to the surface and the surface of the pedestal portion; and exposing the surface of the pedestal portion and the outer diameter of the tip of the connected component side at the top of the bump having the outer diameter of the top. Forming a second hole having a wall surface inclined so as to be larger than the outer diameter of the second conductive film forming layer at a position facing the pedestal portion of the second conductive film forming layer; A step of forming a second conductive film by attaching a conductive material to the surface, and removing the conductive material attached to the second hole and removing the other portion of the conductive material forms the second hole. A method for manufacturing an electronic component, comprising: forming a top portion; and removing the first conductive film forming layer and the second conductive film forming layer.
【請求項4】 第一導電膜形成層および第二導電膜形成
層を絶縁層とし、第一導電膜および第二導電膜を形成す
る際に、導電性材料をメッキにより付着させ、第一導電
膜および第二導電膜を除去する際に、導電性材料をエッ
チングにより除去し、頂上部形成後に第一導電膜形成層
および第二導電膜形成層を剥離することを特徴とする請
求項3記載の電子部品の製造方法。
4. The first conductive film forming layer and the second conductive film forming layer are used as insulating layers, and when forming the first conductive film and the second conductive film, a conductive material is attached by plating to form the first conductive film and the second conductive film. 4. The method according to claim 3, wherein, when removing the film and the second conductive film, the conductive material is removed by etching, and the first conductive film forming layer and the second conductive film forming layer are peeled off after forming the top. Electronic component manufacturing method.
【請求項5】 接続部品側に設けた電極に固着した台座
部と、この台座部における被接続部品側に一体的に形成
される頂上部とを備え、導電性接着剤を頂上部に付着し
た状態で前記接続部品と被接続部品とを電気的に接続す
るためのバンプを有する電子部品であって、 前記頂上部が台座部の一側から被接続部品側に向けて拡
径するよう傾斜して形成されるとともに、他側に前記導
電性接着剤を保持するための保持凹部が形成されたこと
を特徴とする電子部品。
5. A pedestal portion fixed to an electrode provided on a connecting component side, and a top portion integrally formed on the connected component side of the pedestal portion, wherein a conductive adhesive is attached to the top portion. An electronic component having a bump for electrically connecting the connection component and the connected component in a state, wherein the top portion is inclined so as to increase in diameter from one side of the pedestal portion toward the connected component side. And a holding recess for holding the conductive adhesive is formed on the other side.
【請求項6】 接続部品側に設けた電極に固着した台座
部と、この台座部における被接続部品側に一体的に形成
される頂上部とを備え、導電性接着剤を頂上部に付着し
た状態で前記接続部品と被接続部品とを電気的に接続す
るためのバンプを有する電子部品の製造方法であって、
電極および接続部品の表面に対して導電膜形成層を施す
工程と、 前記台座部の表面を露出させるとともにバンプの頂上部
における被接続部品側の先端部の外径が頂上部における
台座部側の外径に比べて大きくなるよう壁面を傾斜させ
た穴を、導電膜形成層の台座部対向箇所に形成する工程
と、 この穴および導電膜形成層の表面に対して導電性材料を
付着させて導電膜を形成する工程と、 前記穴に施した導電性材料の一部を残し他の部分の導電
性材料を除去することで穴に対して台座部および頂上部
を形成する工程とを有したことを特徴とする電子部品の
製造方法。
6. A pedestal portion fixed to an electrode provided on a connection component side, and a top portion integrally formed on the connected component side of the pedestal portion, wherein a conductive adhesive is attached to the top portion. A method of manufacturing an electronic component having a bump for electrically connecting the connection component and a connected component in a state,
A step of applying a conductive film forming layer to the surfaces of the electrodes and the connecting parts; and exposing the surface of the pedestal part and the outer diameter of the tip on the connected part side at the top of the bump to the pedestal side at the top. A step of forming a hole whose wall is inclined so as to be larger than the outer diameter at a position facing the pedestal portion of the conductive film forming layer; and attaching a conductive material to the hole and the surface of the conductive film forming layer. Forming a conductive film, and forming a pedestal portion and a top portion with respect to the hole by removing a portion of the conductive material applied to the hole and removing the other portion of the conductive material. A method for manufacturing an electronic component, comprising:
【請求項7】 導電膜形成層を絶縁層とし、導電膜をエ
ッチングにより除去し、頂上部形成後に導電膜形成層を
剥離することを特徴とする請求項6記載の電子部品の製
造方法。
7. The method for manufacturing an electronic component according to claim 6, wherein the conductive film forming layer is an insulating layer, the conductive film is removed by etching, and the conductive film forming layer is peeled off after forming the top.
JP2001063691A 2001-03-07 2001-03-07 Electronic component and manufacturing method therefor Pending JP2002270629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
JP2002270629A true JP2002270629A (en) 2002-09-20

Family

ID=18922637

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2002270629A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006059917A (en) * 2004-08-18 2006-03-02 Matsushita Electric Ind Co Ltd Csp-type semiconductor device and its manufacturing method
JP2007335464A (en) * 2006-06-12 2007-12-27 Nec Corp Wiring board provided with metal post, semiconductor device, semiconductor device module, and manufacturing method therefor
CN109003909A (en) * 2017-06-07 2018-12-14 三菱电机株式会社 The manufacturing method of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006059917A (en) * 2004-08-18 2006-03-02 Matsushita Electric Ind Co Ltd Csp-type semiconductor device and its manufacturing method
JP2007335464A (en) * 2006-06-12 2007-12-27 Nec Corp Wiring board provided with metal post, semiconductor device, semiconductor device module, and manufacturing method therefor
CN109003909A (en) * 2017-06-07 2018-12-14 三菱电机株式会社 The manufacturing method of semiconductor device
CN109003909B (en) * 2017-06-07 2023-01-06 三菱电机株式会社 Method for manufacturing semiconductor device

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