JP2634804B2 - Signal reading method for solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal reading method for a solid-state imaging device, and more particularly to a signal reading method suitable for a variable shutter.

[Conventional technology]

Interline frame transfer CC as an example of the prior art
The operation of the variable shutter by D (charge transfer element) will be described with reference to the structural diagram of FIG. 3 and the timing chart of FIG.

In FIG. 3, the charge as a signal accumulated in the matrix arrangement of the photodiodes 21 is transferred to the transfer gate pulse input terminal 22.
When the transfer gate pulse P ₁ in FIG. 4 C is applied to the transfer gate 23 than is transferred to the vertical transfer register 24 provided along columns of the photodiodes 21. Thereafter, the high-speed transfer pulse P ₂ (FIG. 4B) is transferred to the memory section 26 constituted by the memory register 25, and further the vertical transfer pulse P ₃
According to (FIG. 4B), the horizontal transfer register 27 is provided for each line.
And output to an output terminal 29 via an output amplifying element 28 as an output signal. FIG. 4A shows a vertical drive pulse. The matrix arrangement of the photodiodes 21 constitutes the photosensitive section 31.

In the case of a variable shutter, the photodiode 21
Accumulation period Unnecessary charge transfer pulse P ₄ in the by adding to (Fig. 4 C) a transfer gate pulse input terminal 22, unnecessary accumulated amount of charge between the transfer gate pulse P ₁ to unnecessary charge transfer pulse P ₄ Is transferred to the vertical transfer register 24, and the smear component leaked from the photodiode 21 into the vertical transfer register 24 due to the sweep pulse P ₅ (FIG. 4B) during the vertical blanking period and the darkness generated in the vertical transfer register 24. Output terminal 29 outside the vertical transfer register together with unnecessary charges such as current components
More extruded. Thereby, the effective accumulation time of the photodiode 21 is arbitrarily controlled, that is, a variable shutter is obtained.

Actually, the transfer gate 23 is
Of consists of two rows of the even Filled and odd Filled per array in the vertical scanning direction, charges of the photodiode 21a of each even-numbered line in the scanning of the even Filled is the transfer gate pulse P ₁ to the transfer gates for even Filled transferred given by the vertical transfer register 24, the odd Filled charges of the photodiode 21b of each odd line are transferred given the transfer gate pulse P ₁ to the transfer gates for odd Filled to the vertical transfer register 24. Accordingly, the transfer gate pulse input terminals 22 provided to both transfer gates 23 are also provided for the even field and the odd field.

[Problems to be solved by the invention]

In the conventional variable shutter described above, by entering the required charge transfer gate pulse P ₄ each for each Filled, 2
Since there is a time difference of one field between the exposures of the two fields, when a moving object is imaged at a high speed and viewed in the frame mode, the images of the two fields are displaced from each other as shown in FIG. Appears doubly. By the way, when looking at the frame mode, a moving object with a speed of 100 km / h will have a difference of about 45 cm between the fields. For this reason, in order to obtain a still image in which the image is not duplicated in the frame mode, only a filled image can be used, and there is a drawback that only half of the number of lines in vertical resolution can be obtained.

[Means for solving the problem]

The present invention relates to a solid-state imaging device that uses a solid-state imaging device including a photosensitive unit, a vertical transfer unit that sends a charge obtained by the photosensitive unit to a memory unit, and a memory unit, and reads out a signal in a frame mode. In the effective image period, the generation times are slightly shifted from each other, and unnecessary charges accumulated in the photosensitive portion are vertically transferred by the first and second unnecessary charge transfer gate pulses having a period of one frame. The unnecessary charges read out by the first and second unnecessary charge transfer gate pulses in the vertical transfer unit during the next vertical blanking period between the odd field and the even field are transferred to the outside by high-speed transfer via the memory unit. The first and second signal charge transfer gate pulses, which are delayed by the same time from the first and second unnecessary charge transfer gate pulses after the first and second unnecessary charge transfer gate pulses are generated after the unnecessary charge sweep, are accumulated in the photosensitive portion. The signal charge is read out to the vertical transfer unit by the earlier pulse after the earlier pulse of the first and second signal charge transfer gate pulses and before the later pulse. The signal charges are transferred to the memory unit at high speed, and the vertical transfer unit, the memory unit, and the horizontal transfer unit are driven by a vertical transfer pulse having the same period as the horizontal scanning period, so that the signal charges transferred at high speed to the memory unit are horizontally transferred. In addition to outputting to the outside via the horizontal transfer unit every scanning cycle, the signal charges read by the slower pulse in the vertical transfer unit are sequentially transferred to the memory unit.

In this way, the storage time can be controlled to an arbitrary value, and a still image with good resolution can be obtained in the frame mode.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a timing chart and the operation of each part in one embodiment of the present invention. FIG. 2 shows one embodiment of the present invention and a main part of the configuration. Parts corresponding to those in FIG. It is.

According to the present invention, the unnecessary charge transfer gate pulses P ₄ and P ₄ ′ are added at an arbitrary timing before the conventional transfer gate pulses P ₁ and P ₁ ′ only to the even fields, so that the odd and even fields have the same even number. Get an image of the effective storage time of the field. That is, the unnecessary charge transfer gate pulses P ₄ and P ₄ ′ are supplied to the even-numbered transfer gates 2 in the even-numbered field.
3, applied to the odd Filled for transfer gate 23, charge a smear component of the unnecessary accumulation amount that is transferred to the vertical transfer register 24 by the pulse P ₅ sweep the next vertical blanking interval, and unnecessary charges such as dark current component sweep It was followed, transferred by the transfer gate pulse P ₁ charges accumulated in the odd Filled side 21b of the photodiode 21 to the vertical transfer register 24, further high-speed transfer pulses so
And transferred to the memory unit 26 at P _2, then the transfer gate pulse P ₁ '
In FIG. 1D, the even-filled side 21 of the photodiode 21 is shown.
The accumulated charge of b is transferred to the vertical transfer register 24.

Then by the vertical transfer pulse P _3, with sequentially transferring the charges of each memory register 25 to the horizontal transfer register 27 every line, and transfers the charges in the vertical transfer register 24 sequentially to memory register 25. The electric charge of the horizontal transfer register 27 is output to the output terminal 29 as a frame output signal via the output amplifying element 28.

Pulse P ₅ and high-speed transfer pulses sweep in the vertical blanking period between moving from an odd Filled to even Filled
P ₂ , no transfer gate pulse P ₁ , P ₁ ′, vertical transfer register 24 and memory register 25 are transfer-controlled by vertical transfer pulse P ₃ line by line, so that an even-filled signal is output continuously Output to terminal 29.

The accumulated charge from the transfer to the vertical transfer register 24 of the photodiode 21b odd Filled As can be seen from Figure 1, during the high-speed transfer pulse P ₂ until transferring charges accumulated in the photodiode 21a of the even Filled Therefore, the phases of the unnecessary charge transfer gate pulses P ₄ and P ₄ ′ need to be shifted by the same time in order to match the accumulation time of both fields.

FIG. 2 shows a configuration example for performing the control shown in FIG. Vertical drive pulse VD applied to terminal 41 (FIG. 1A)
Sets the flip-flop circuit 42, and the output of the flip-flop circuit 42 controls the operation of the high-speed transfer pulse generation circuit 43. On the other hand, the flip-flop circuit 42 is controlled by the filled index pulse from the terminal 44 so that the high-speed transfer pulse is generated only in the odd-numbered fields.

The output pulses of the high-speed transfer pulse generating circuit 43 is counted by the high-speed transfer pulse counter 45, the sweep-out 512 pulses in the case of pulse P _5, the output of the generating 256 pulses when the high speed transfer pulses P ₂ counter 45 The flip-flop circuit 42 is reset. The vertical transfer pulse P _{3 is} output from the horizontal drive pulse from the terminal 46 to the vertical transfer pulse generation circuit 47.
Is created, the vertical transfer pulse P ₃ is mixed with pulses from the high-speed transfer pulse generating circuit 43 by the mixing circuit 48 through a driving circuit 49, is outputted as the vertical transfer pulses, for example, four phases.

On the other hand, in the transfer gate generation circuit 51, transfer gate pulses P ₁ and P ₁ ′ are generated by the phase of the vertical drive pulse from the terminal 41 and the polarity of the filled index pulse from the terminal. The horizontal drive pulse at terminal 46 is the accumulation time counter 52
The output of the accumulation time counter 52 is supplied to the transfer gate generation circuit 51 at an arbitrary timing set in advance by switching with the accumulation time changeover switch 53, and unnecessary charge transfer gate pulses P ₄ and P ₄ ′ are generated. I do.

Transfer gate pulse P ₁ In this example, P ₁ 'and the vertical transfer pulse P ₃ forwarding believes separates gate pulse P _1, P
It is also possible to cause a mixture of ₁ 'to the vertical transfer pulse P _3. In this embodiment, the unnecessary charge transfer gate pulses P ₅ , P
_{Although 5} 'has been described as a single pulse, a plurality of pulses may be used.

〔The invention's effect〕

As described above, according to the present invention, the generation times are slightly shifted from each other within the effective video period, and the first and second unnecessary charge transfer gate pulses having a cycle of one frame are used.
Unnecessary charges stored in the photosensitive unit are read out to the vertical transfer unit,
In the next vertical blanking period between odd-numbered fields and even-numbered fields, unnecessary charges read by the first and second unnecessary charge transfer gate pulses in the vertical transfer unit are swept out to the outside by high-speed transfer via the memory unit. By immediately transferring the signal charges of the photosensitive parts of the odd lines to the memory part at a high speed, it is possible to take out the image accumulated at almost the same point from the photosensitive parts of the odd lines and the photosensitive parts of the even lines, and image the high-speed moving body. However, the reproduced image is not duplicated as in the related art, but can be performed in the frame mode, and an image with high resolution can be obtained.

In addition, since unnecessary charges are swept out of the vertical transfer unit during the blanking period, the unnecessary charges can be swept out and the images of both fields obtained by accumulating at almost the same timing can be obtained without changing the structure of the image sensor. Easy to do.

Further, in the present invention, the transfer of the odd-numbered signal charges from the memory section to the outside and the transfer of the even-numbered signal charges from the vertical transfer register to the memory section are performed simultaneously. Since the driving can be performed using a pulse, the driving circuit can be simplified and the time required for outputting from imaging to the outside can be shortened.

[Brief description of the drawings]

FIG. 1 is a timing chart showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a configuration for generating various pulses according to an embodiment of the present invention, and FIG. 3 is a structure of an interline frame transfer CCD. FIG. 4 is a timing chart showing the prior art, FIG. 5 is a diagram showing an example of a frame mode image according to the prior art, and FIG. 6 is a diagram showing an example of a frame mode image according to the present invention.

Claims (1)

(57) [Claims] 1. A frame mode of a solid-state imaging device using a solid-state imaging device including a photosensitive unit, a vertical transfer unit for sending a charge obtained by the photosensitive unit to a memory unit, and the memory unit. In the signal reading method described above, the generation times are slightly shifted from each other within the effective video period, and the unnecessary charges accumulated in the photosensitive portion are removed by the first and second unnecessary charge transfer gate pulses having a cycle of one frame. The unnecessary charges read out to the vertical transfer unit by the first and second unnecessary charge transfer gate pulses in the vertical transfer unit in the next vertical blanking period between the odd field and the even field are transferred to the memory unit. The first and second unnecessary charge transfer gate pulses are delayed by the same time from the first and second unnecessary charge transfer gates, and the first and second unnecessary charge transfer gates are generated after the unnecessary charge is discharged.
The signal charges accumulated in the photosensitive section are read out to the vertical transfer section by a two-signal charge transfer gate pulse, and the signal charges are read after the earlier pulse of the first and second signal charge transfer gate pulses and later. The signal charge read out to the vertical transfer unit by the earlier pulse is transferred to the memory unit at a high speed, and the vertical transfer unit, the memory unit, and the horizontal transfer unit are transferred by the vertical transfer pulse having the same cycle as the horizontal scanning cycle. By driving
The signal charges transferred to the memory unit at high speed are output to the outside via the horizontal transfer unit every horizontal scanning cycle, and the signal charges read by the slower pulse in the vertical transfer unit are transferred to the memory unit. A signal reading method for a solid-state imaging device, wherein the signals are sequentially transferred.