JP2630408B2 - Ultrasound diagnostic equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultrasonic diagnostic apparatus that obtains a tomographic image of a diagnostic part of a subject using ultrasonic waves, and particularly to an A / D converter having a small number of bits. The present invention relates to an ultrasonic diagnostic apparatus having a digital phasing circuit including an A / D conversion circuit that can expand a dynamic range of a signal to be handled even when used.

[Conventional technology]

A conventional ultrasonic diagnostic apparatus equipped with a phasing circuit using a delay line has a large delay time error, and there is variation in the transmission direction of the ultrasonic beam and the reception direction of the reflected echo,
It was difficult to obtain good quality tomographic images. On the other hand, conventionally, IEE, Ultrasonic Symposium Proceedings 2 (1980)
Pages 22 to 31 (IEEE, Ultrasonic Symposium Procee
As described in dings2 (1980), pp. 22-31), an ultrasonic diagnostic apparatus having a digital phasing circuit has been proposed.

As shown in FIG. 8, the ultrasonic diagnostic apparatus provided with this digital phasing circuit includes a plurality of transducer elements 1a, 1b,.
A probe 2 in which 1n are arranged in a line to transmit and receive ultrasonic waves;
A pulse generator 3 for applying a predetermined delay time to each of the transducer elements 1a to 1n and applying a drive pulse for ultrasonic emission,
An A / D converter 4 for converting an analog echo signal received by each of the transducer elements 1a to 1n of the probe 2 into a digital signal, and a storage device for sequentially storing the digital signal from the A / D converter 4 5n, random access memories 5a, 5b,... 5n, an adder 6 for adding data read from the RAMs 5a to 5n, and D / A conversion of an output signal from the adder 6. And a display device 7 for displaying a tomographic image. In addition, in FIG.
Is a changeover switch, 9 is an amplifier, 10 is a D / A converter, 11 is a focus memory, and 12 is a control unit. The probe 2 transmits an ultrasonic beam, and the echo signals received by the transducer elements 1a to 1n are converted into digital signals by the A / D converter 4, and the digital signals are converted into RAMs 5a to 5d.
n, the control unit 12 and the focus memory 11 control the data address and the read timing to give a predetermined delay, and the read data is added by the adder 6 so that the phase is adjusted. ing. That is, the A / D converter 4, the RAMs 5a to 5n, and the adder 6 constitute a digital type phasing circuit. Although not shown in FIG. 8, a detector for detecting an output signal from the adder 6 is provided between the adder 6 and the D / A converter 10.

In FIG. 8, the echo signals from the transducer elements 1a to 1n of the probe 2 are sequentially switched using the changeover switch 8 such as a multiplexer, and the number of the A / D converters 4 is reduced to one. As shown, multiple A / Ds operating in parallel to perform high-speed imaging in real time
It is described in the above document that a converter 4 may be provided.

[Problems to be solved by the invention]

In the ultrasonic diagnostic apparatus having such a digital phasing circuit, each transducer element 1a, 1b,.
One A / D converter 4 for each 1n channel
Are connected. Here, the dynamic range of the echo signal is determined by the number of bits of the A / D converter 4. Therefore, to increase the dynamic range of the echo signal to be handled, the A / D converter 4 having a large number of bits is required. A / D converters with a large number of bits are expensive and hinder the practical application of the device.

Further, in recent ultrasonic diagnostic apparatuses, so-called pulsed Doppler blood flow measurement, which measures a blood flow velocity by measuring a Doppler shift frequency of a reflected echo of blood cells in the heart and blood vessels together with observation of a tomographic image, is performed. However, when trying to provide such a function to an ultrasonic diagnostic apparatus, the echo signals from blood cells in the bloodstream are very weak compared to the echo signals forming a tomographic image. The dynamic range of the signal was further widened. However, the dynamic range of the echo signal that forms the tomographic image is a large value of 40 to 60 dB, and if the function of pulse Doppler blood flow measurement is to be added to this, the dynamic range of the echo signal to be handled will be about 90 dB It will be wide up to. On the other hand, since the ultrasonic wave used in the ultrasonic diagnostic apparatus has a high frequency of 2.0 MHz to 10 MHz, the A / D converter 4 used in the digital phasing circuit samples at 10 bits or more (more preferably, 15 bits or more). A high speed grade of 4 to 30 MHz is required.
It is not easy to secure a large number of bits required by such a high-speed A / D converter 4, and even if it can be secured, it becomes very expensive. Therefore, it has been difficult to put an ultrasonic diagnostic apparatus having a digital phasing circuit into practical use.

Therefore, the present invention provides an ultrasonic diagnostic apparatus having a digital phasing circuit including an A / D conversion circuit capable of expanding a dynamic range of a signal to be handled even when an A / D converter having a small number of bits is used. The purpose is to provide.

[Means for solving the problem]

Means of the present invention for solving the above-mentioned problems include a probe in which a plurality of transducer elements are arranged and which transmits and receives ultrasonic waves, and an ultrasonic launch by giving a predetermined delay time to the plurality of transducer elements. A pulse generator for applying a drive pulse, and an A / D conversion circuit for converting a plurality of analog echo signals received by the plurality of transducer elements of the probe into digital signals, respectively. A digital phasing circuit that has a storage device for sequentially storing digital signals from the storage device and has an adder that adds data read with a predetermined delay from the storage device and aligns the phase of the digital echo signal;
A detector for detecting an output signal from the adder of the digital phasing circuit, and a D / A converter for outputting the output signal from the detector.
And a display device for converting and displaying a tomographic image.
The D conversion circuit has a magnification of 1/2 ^k (where k is an integer) and varies the dynamic range of the analog echo signal, and converts the dynamic range of the analog echo signal into a binary digital signal. A / D converter, the output data of the multiplier and the output data of the A / D converter corresponding to the magnitude of the multiplier
This is performed by an ultrasonic diagnostic apparatus including a data converter that shifts and outputs data by a digit.

[Action]

The ultrasonic diagnostic apparatus configured as described above varies the dynamic range of the analog echo signal with a magnification of 1/2 ^k using a multiplier in an A / D conversion circuit of a digital phasing circuit.
The analog converter converts the analog echo signal from the multiplier into a binary digital signal. The data converter further converts the A / D converter according to the output data of the multiplier and the magnitude of the multiplier. By shifting the output data of k by k digits and outputting it, the analog echo signal from each channel of the probe can be converted into a digital signal by an A / D converter whose conversion coefficient changes according to the magnitude of the signal. The output data of the A / D converter can be shifted and output by a predetermined number of digits.

Now, the operation of the A / D converter will be described in further detail, assuming that, for example, two A / D converters each having 10 bits, that is, 10 binary digits are used. FIG. 2 shows the relationship between the magnitude of the input signal that can be read in that case and the magnitude of the output signal. The horizontal axis and the vertical axis of FIG. 2 are represented by decimal numbers and dB, respectively. In FIG. 2, a straight line A represents a first A / D converter, and this first A / D converter corresponds to an input signal when a signal having a magnitude of 1 to 1024 in decimal is input. Then, a binary digital signal corresponding to 1 to 1024 in decimal is output. On the other hand, the magnification of the multiplier of the A / D conversion circuit is, for example, 1/3.
When the signal is set to 2, that is, approximately -30 dB, the second A / D converter indicated by the straight line B receives a signal having a magnitude of 32 to 32768 in decimal notation. To output a binary digital signal corresponding to 1024. Then, from the relation of straight lines A and B shown in FIG. 2, the first A / D converter in that a ₁ to the output signal becomes 1024 decimal (line A) a second A / D converter ( By switching to the point b ₁ on the output signal of the straight line B) and then reading along the straight line B, it is possible to read and output as a digital signal that the input signal changes as a whole in the range from 1 to 32768 in decimal. can do.
That is, in the case of the example shown in FIG.
Analog signals can be converted to digital signals with a dynamic range of dB (equivalent to 15 bits). Since the magnification of the multiplier was 1/32 = 1/2 ^5, if the A / D converter is outputted in parallel by binary numbers, corresponding to the input signal when the shift to the digit 5-bit upper A binary digital signal is output.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of an ultrasonic diagnostic apparatus according to the present invention.

This ultrasonic diagnostic apparatus obtains a tomographic image of a diagnostic part of a subject using ultrasonic waves, and utilizes a characteristic of an analog type delay circuit and can compensate for a defect of the digital type delay circuit. In this embodiment, the probe 2 and the pulse generator 3 are combined as shown in FIG.
, An analog delay circuit 13, an A / D conversion circuit 14,
A storage device (5a, 5b,... 5n), an adder 6, a detector 21,
And a display device 7.

The probe 2 transmits and receives an ultrasonic wave toward and from a diagnosis site of a subject, and has a plurality of transducer elements 1a, 1b,..., 1n formed in small strips arranged in a line. The pulse generator 3 applies a predetermined delay time to the plurality of transducer elements 1a to 1n of the probe 2 to apply a driving pulse for ultrasonic emission, and controls a transmission direction of the ultrasonic beam. For this purpose, the timing for exciting each of the transducer elements 1a, 1b,... 1n can be controlled by the control unit 12 described later.

The analog delay circuit 13 gives a predetermined delay time to the echo signal from the diagnostic part of the subject received by the transducer elements 1a, 1b,. 15, a delay circuit 16, a voltage / current converter 17, a cross point switch 18, a constant current signal source 19, and a tapped delay line 20. The amplifier 15 is for amplifying the echo signals from the transducer elements 1a, 1b,... 1n of the probe 2. The amplifier 15 increases its gain with time according to the control signal from the control unit 12, and An echo signal weakened in a deep part of the sample is compensated. The delay circuit 16 is composed of a tapped delay line and an analog switch. In this case, the echo signal from the amplifier 15 is delayed with a small delay time. For example the delay time between the taps of the tapped delay line and T _1, when the number of the tap and N _1,
T ₁ becomes possible set the delay time resolution, the maximum delay time is (N ₁ -1) T _1. The voltage / current converter 17 converts the echo signal voltage from the delay circuit 16 into a constant current signal source. Crosspoint switch 18, so as to cross the n _1-channel input signal lines and m _1-channel output signal lines as shown, which is disposed respectively analog switches to its intersection of these analog switches Opening and closing is controlled by the control unit 12. The constant current signal source 19 has a low input impedance, and is connected to the tap of the subsequent tapped delay line 20 with a signal source having as high an impedance as possible to prevent the performance of the delay line from deteriorating and to reduce the cross point. Switch 18
To prevent deterioration of the insertion loss and frequency characteristics.
In addition, there is an effect that the signal connected to and guided to the constant current signal source 19 is added. Delay line with tap
20 gives a delay larger than the delay circuit 16;
For example, if the delay time between each tap is T ₂ and the number of taps is N ₂ , the delay time can be set with a resolution of T ₂ , and the maximum delay time is (N ₂ −1) T ₂ . Here, the delay time between each tap T ₂ are, the maximum delay time of the delay circuit 16 (N ₁ -
1) it is taken less than T _1.

The A / D conversion circuit 14 converts a plurality of analog signals output from the analog delay circuit 13 into digital signals. The storage device is the A / D conversion circuit 1
The digital signals output from 4 are sequentially stored and include, for example, a plurality of RAMs 5a, 5b,... 5n. And
The data stored in the RAMs 5a to 5n is read out at an arbitrary cycle of the clock signal output from the control unit 12, thereby being given a delay with a predetermined delay time. For example, RA above
A read clock signal cycle T ₃ of M5a～5n, when any number of naturally and N _3, N ₃ T ₃ hours later each RAM5a, 5b, ... 5
By reading the data of n, a delay of N ₃ T ₃ time can be given. It should be noted that the delay caused by the read control of the RAMs 5a to 5n gives a longer delay than the above-described tapped delay line 20. The adder 6 adds the data read from the RAMs 5a to 5n, thereby phasing the data. The A / D conversion circuit 14, the RAMs 5a to 5n, and the adder 6 constitute a digital phasing circuit for aligning the phase of the digital echo signal.

The test object 21 detects an output signal from the adder 6 of the digital phasing circuit. The display device 7 D / A converts the signal output from the detector 21 to display a tomographic image, and has a D / A converter therein. In FIG. 1, reference numeral 12 denotes a control unit for controlling each of the above components. In FIG. 1, the analog delay circuit 13 is provided between the probe 2 and the A / D conversion circuit 14, but the present invention is not limited to this, and the analog delay circuit 13 is not limited thereto. The delay circuit 13 may be omitted, and all delays may be given when reading from the RAMs 5a to 5n.

Here, in the present invention, as shown in FIG. 3, the A / D conversion circuit 14 of the digital phasing circuit includes a multiplying device 22, two A / D converters 23a and 23b, converter
It consists of 24. The multiplier 22 varies the dynamic range of the analog signal output from the analog delay circuit 13 shown in FIG. 1. The multiplier is, for example, 1/2 ^k (k is an integer), and the attenuation is It has a function as a container. The multiplying device 22 makes the levels of input signals to two A / D converters 23a and 23b described later different. In addition, the multiplier 22
Is not limited to an attenuator, but may be an amplifier having a constant gain. The A / D converters 23a and 23b convert analog signals whose dynamic range is varied by the presence of the multiplier 22 into two.
A digital signal is converted into a digital signal of a binary number, both of which are of m bits, a first A / D converter 23a and a second A / D converter 23b are provided in parallel, and a second A / D converter 23b is provided. The multiplier 22 is inserted before the / D converter 23b. The data converter 24 shifts the output data of the two A / D converters 23a and 23b by k digits in accordance with the output data of the magnification unit 22 and the magnification of the magnification shift 22, and outputs the data. is there. In FIG. 3, reference numeral 25 denotes output data from the first A / D converter 23a, which is compared with a built-in reference value (equal to the number of bits of the first A / D converter 23a). This is a comparator that sends a switching signal of the first A / D converter 23a and the second A / D converter 23b to the data converter 24.

Next, the operation of the A / D conversion circuit 14 configured as described above will be described. First, the analog signal from the analog delay circuit 13 is directly input to the first A / D converter 23a, and the dynamic range of the signal is changed by the multiplier 22 to the second A / D converter 23b. input. As a result, the levels of the input signals to the first and second A / D converters 23a and 23b are made different. That is, the second A /
The analog signal is attenuated to 1 / ^2k by the multiplier 22 and input to the D converter 23b. Next, such an analog input signal is supplied to the first A / D converter 23a and the second A / D converter
The signals are converted into binary digital signals by the converter 23b and output. Here, when the analog input signal to the first A / D converter 23a is small and the number of digits of the output data from the first A / D converter 23 is small, the comparator 25 has its built-in reference value. And controls the data converter 24 to take in output data from the first A / D converter 23a. Therefore, until the number of digits of the output data from the first A / D converter 23a overflows, the output data of the first A / D converter 23a is output to the RAMs 5a to 5n via the data converter 24. . In the above, the operation of comparing the signal of the first A / D converter 23a with the reference value built in the comparator 25 has been described. However, a modification that performs the same operation with the signal of the second A / D converter 23b is also considered. Can be

Next, when the analog input signal to the first A / D converter 23a sequentially increases and the number of digits of the output data from the first A / D converter 23a increases and overflows, the comparator 25 has its built-in signal. The first A / D converter 23a detects that the number of digits of the output data of the first A / D converter 23a has overflowed by comparing with the reference value, and the second A / D converter 23a A switching signal for switching is sent to the D converter 23b. As a result, the data converter 24 takes in the output data from the second A / D converter 23b and outputs the output data of the second A / D converter 23b to the RAMs 5a to 5n. At this time, the second A / D converter 23b
Since the analog signal is attenuated to 1/2 ^k by the multiplier 22 and input, the digital signal output from the second A / D converter 23b is transmitted to the upper digit within the data converter 24 to the upper digit. The output is shifted by bits (k digits). Therefore, a (k + m) -bit digital signal is output as the entire output data from the data converter 24.

Here, the multiplier 22 shown in FIG. 3 and k = 5 and the magnification 1/2 ^5, the first and second A / D converter 23a, 2
3b shows the relationship between input data and output data from the first and second A / D converters 23a and 23b to the data converter 24 when m = 10 and the number of bits is 10 bits. As shown in FIG. That is, 10-bit A /
By using two D converters (23a and 23b), the A / D conversion circuit 14 having a 15-bit dynamic range as a whole is realized. This relationship is exactly the same as the relationship shown in FIG. The data converter 24 having the above functions can be easily realized by, for example, a combination of a gate circuit or a combination of a gate circuit and a shift register.

In FIG. 3, two A / D converters (23
a, 23b) Although the example in which they are provided in parallel has been described, the present invention is not limited to this, and three or more may be provided in parallel. For example, when a graph similar to that shown in FIG. 2 is written for a case where three A / D converters are provided in parallel, the graph shown in FIG. 5 is obtained. In the figure, a straight line A represents a first A / D converter, a straight line B represents a second A / D converter, and a straight line C represents a third A / D converter. Here, the second
In the figure, the vertical axis indicates the output signal level of the A / D converter, which is equal to the S / N due to the quantization noise of the A / D converter. Therefore, when the first A / D converter (linear A) switches to the second A / D converter (linear B), as shown in FIG. 2, point a ₁ on the line A
The operating point to b ₁ on the straight line B is when moving, so that the S / N is lowered to rise again in once from. On the other hand, as shown by the straight line C in FIG. 5, when a third A / D converter connected to a multiplier having a magnification smaller than 1/32 is further added, the first A / D converter (linear A) from the third A
Switch to / D converter (straight line C), and a third A / D
When switching from the converter (straight line C) to the second A / D converter (straight line B), the operating point moves from the point a ₁ on the straight line A to the point c ₁ on the straight line C. the operating point is to move from point c ₂ to a point b ₂ on the straight line B. At this time, since the points c ₁ and b ₂ are maintained at a relatively high output signal level, the S / N is suppressed as compared with the case of FIG. 2 and the S / N is improved as a whole. be able to. From this, as the number of A / D converters installed in parallel increases,
It is possible to improve a temporary decrease in S / N when sequentially switching the A / D converter in the process of increasing the input signal level. However, increasing the number of A / D converters increases the cost, so it is better to take into account the balance between the obtained performance and the cost in practical use.

FIG. 6 is a block diagram showing a second embodiment of the A / D conversion circuit 14. The A / D conversion circuit 14 according to this embodiment includes a sample and hold circuit 16, two voltage dividers 27a and 27b, two A / D converters 28a and 28b, and a data converter 29. . The sample and hold circuit 26 inputs and samples the analog signal output from the analog delay circuit 13 shown in FIG. 1, and holds the value for a certain period of time. The voltage dividers 27a and 27b perform the function of the multiplier 22 shown in FIG. 3, and are configured to vary the dynamic range of the analog signal output from the sample and hold circuit 26. The pressure divider 27a has a fixed voltage division ratio (1/2 ^j , where j is a constant integer), and the second voltage divider 27b has a variable voltage division ratio (1/2 ^k , where k is an integer). The second voltage divider 27b has a partial pressure ratio of 1
/ Regard 2 ^k, the integer k is adapted to be varied by a control signal from the controller 30 to be described later. Therefore, the two voltage dividers 27a and 27b can make different levels of input signals to two A / D converters 28a and 28b described later. The A / D converters 28a, 28b are connected to the voltage divider 27a,
The analog signal whose dynamic range is varied by 27b is converted into a binary digital signal. The first A / D converter 28a is of m bits, and the second A / D converter 28a is
The D converter 28b has n bits. The first voltage divider 27a is provided before the first A / D converter 28a.
And a second voltage divider 27b is inserted in front of the second A / D converter 28b. Data converter 29
Converts the output data of the two A / D converters 28a and 28b in accordance with the voltage dividing ratios of the voltage dividers 27a and 27b, and in the figure, the set value of the voltage dividing ratio of the second voltage divider 27b. the 1/2 ^k has become vary the number of digits to shift the output data of the second a / D converter 28b. In FIG. 6,
Reference numeral 30 denotes a controller for controlling each of the above components.

Next, A / D according to the second embodiment configured as described above.
The operation of the conversion circuit 14 will be described with reference to the flowchart shown in FIG. First, the analog delay circuit
The analog signal from 13 is input to the sample and hold circuit 26. Then, the sample and hold circuit 26 samples the analog input signal and holds the value for a predetermined time (step). Next, the output signal from the sample and hold circuit 26 is supplied to the first voltage divider 27.
Fill in a, are predetermined dynamic range corresponding to the number of bits of the first A / D converter 28a in the voltage dividing ratio 1/2 ^j of the fixed. Next, the output signal from the first voltage divider 27a is input to the first A / D converter 28a. Then, the analog input signal is A / D converted by the first A / D converter 28a (step). Next, the first A / D converter 2
The output data output from 8a is input to the controller 30.
The controller 30 controls the first A / D converter 28a
The digital value of the output data of m bits from is read (step). Next, the controller 30 controls the second A / D converter based on the digital value of the output data of the first A / D converter 28a.
The voltage division ratio 1/2 ^k of the second voltage divider 27b is set so that the level of the analog input signal to the converter 28b is in the full range (step). That is, the controller 30 controls the value k that determines the voltage division ratio of the second voltage divider 27b,
Controls the input signal level of the / D converter 28b. next,
The analog signal input from the sample-and-hold circuit 26 to the second voltage divider 27b has a voltage division ratio set as described above.
A predetermined dynamic range corresponding to the number of bits of the second A / D converter 28b is 1/2 ^k . Next, the output signal from the second voltage divider 27b is input to the second A / D converter 28b. Then, the analog input signal is A / D converted by the second A / D converter 28b (step). here,
The first A / D converter 28a and the second A / D converter 28b
And the voltage of the input signal in which one bit stands in the least significant digit is the same. Then, when k = 0 at the voltage dividing ratio of 1/2 ^k of the second voltage divider 27b, when the least significant digit of the first A / D converter 28a becomes 1, the second A / D converter 28b Will overflow.

Next, from the second A / D converter 28b, the data
The n-bit output data input to 29 is shifted to the upper digit by k digits, and the sample and hold circuit 26 is reset (step). The control at this time is the controller
This is performed by control signals sent from 30 to the data converter 29 and the sample and hold circuit 26, respectively. By such an operation, a digital signal of (m + n) bits is output as the entire output data from the data converter 29. That is, by using the m-bit A / D converter 28a and the n-bit A / D converter 28b, the A / D conversion circuit 14 having a (m + n) -bit dynamic range as a whole is realized. In the case of this embodiment, as shown in FIG. 2, in the embodiment of FIG. 3, the first A / D converter (straight line A) converts the second A / D
When switching to the converter (straight line B), the S / N sometimes dropped, but such a drop in S / N can be improved.

In FIG. 6, the voltage dividing ratio of the voltage dividers 27a and 27b is shown as one power of 2, but the present invention is not limited to this, and the voltage dividing ratio is 1 / Q (where Q is an arbitrary number). Even if an arbitrary numerical value is used, the same effect as described above can be obtained by executing conversion of the effective numerical value together with the digit shift in the data converter 29 at an arbitrary magnification using, for example, a ROM (read only memory). .

In FIG. 6, two A / D converters 28a, 28
Although shown as a configuration using 8b, the present invention is not limited to this, for example, a first voltage divider 27a and a first A / D converter 28a
The operation with the second voltage divider 27b and the second A / D converter 28
b and one A / D converter
The same function can be exhibited only with 28b. That is, the second voltage divider 27b first sets k = j and sets the voltage division ratio to 1/2 ^k, and converts the input analog signal from the sample and hold circuit 26 into a digital signal by the second A / D converter 28b. I do. Thereafter, the controller 30 sets the value k to set the voltage division ratio 1/2 ^k of the second voltage divider 27b so that the input signal level to the second A / D converter 28b is in the full range. What is necessary is just to control.

〔The invention's effect〕

Since the present invention is configured as described above, the A / D conversion circuit 14 of the digital phasing circuit can change the dynamic range of the analog echo signal by changing the magnification to 1/2 ^k (k is an integer). A multiplier 22; A / D converters 23a and 23b for converting the analog echo signal of which dynamic range is changed into a binary digital signal; output data of the multiplier 22 and the magnitude of the magnification of the multiplier 22 Corresponding to
A data converter 24 that shifts the output data of the A / D converters 23a and 23b by k digits and outputs it expands the dynamic range of signals handled even when using an A / D converter with a small number of bits. An A / D conversion circuit 14 that can be provided can be provided. Therefore, it is currently in practical use
By using the A / D converter, the dynamic range of the echo signal to be handled can be increased, and the practical use of an ultrasonic diagnostic apparatus having a digital phase adjustment circuit can be facilitated. Also, in pulse Doppler blood flow measurement in a recent ultrasonic diagnostic apparatus, according to the present invention, the dynamic range of a signal handled by an A / D converter with a small number of bits can be expanded, so that high-speed A / D A / D with large number of bits required by converter
It is relatively easy to secure the conversion circuit 14. Therefore,
ADVANTAGE OF THE INVENTION According to this invention, the ultrasonic diagnostic apparatus provided with the digital phasing circuit can be put into practical use at a low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an ultrasonic diagnostic apparatus according to the present invention, and FIG. 2 shows the principle of the present invention.
FIG. 3 is a graph showing the relationship between the magnitude of an input signal and the magnitude of an output signal to a D converter. FIG.
FIG. 4 is a block diagram showing a first embodiment of the conversion circuit, FIG. 4 is an explanatory diagram showing the operation of the A / D conversion circuit according to the first embodiment, and FIG. 5 is an A / D converter according to the first embodiment. 6 is a graph showing the relationship between the magnitude of an input signal and the magnitude of an output signal for three A / D converters in a modification of the conversion circuit;
FIG. 7 is a block diagram showing a second embodiment of the A / D conversion circuit, FIG. 7 is a flowchart showing the operation of the A / D conversion circuit according to the second embodiment, and FIG. FIG. 3 is a block diagram illustrating an ultrasonic diagnostic apparatus including a phase circuit. 1a to 1n: transducer element, 2 ... probe, 3 ... pulse generator,
5a to 5n RAM (storage device), 6 adder, 7 display device, 12 control unit, 13 analog delay circuit, 14 A /
D conversion circuit, 21: detector, 22: multiplier, 23a, 28a: first
A / D converter, 23b, 28b… Second A / D converter, 24, 29
... data converter, 25 ... comparator, 26 ... sample and hold circuit, 27a ... first voltage divider, 27b ... second voltage divider, 30 ... controller.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-135641 (JP, A) JP-A-60-135035 (JP, A) JP-A-58-48849 (JP, A) JP-A-59-1988 20153 (JP, A) Actually open 1986-131667 (JP, U)

Claims (1)

(57) [Claims] 1. A probe in which a plurality of transducer elements are arranged to transmit and receive an ultrasonic wave, and a pulse generator for applying a predetermined delay time to the plurality of transducer elements to apply a driving pulse for ultrasonic emission. And an A / D conversion circuit for converting a plurality of analog echo signals received by the plurality of transducer elements of the probe into digital signals, respectively, and sequentially storing digital signals from the A / D conversion circuit. A digital phasing circuit that has a storage device and has an adder that adds data read out from the storage device with a predetermined delay and that aligns the phase of a digital echo signal; An ultrasonic diagnostic apparatus comprising: a detector for detecting an output signal from an adder; and a display device for D / A converting the output signal from the detector and displaying a tomographic image. A of phase circuit The / D conversion circuit has a magnification of 1/2 ^k (where k is an integer) and varies the dynamic range of the analog echo signal, and converts the dynamic range of the analog echo signal into a binary digital signal. An A / D converter for conversion, and a data converter for shifting the output data of the A / D converter by k digits and outputting the output data of the multiplier and the output data of the A / D converter corresponding to the magnitude of the multiplier. An ultrasonic diagnostic apparatus characterized by the above-mentioned.