JP2722910B2 - Ultrasound diagnostic equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an ultrasonic diagnostic apparatus having a digital beamformer that performs / D conversion and combines reception directivity.

[0002]

2. Description of the Related Art Recently, a digital beamformer which performs A / D (analog / digital) conversion of an ultrasonic reception signal and synthesizes reception directivity has been proposed by J.I. Acoustic. Soc.
Am. Reference A described in 63 (2)
l approach todical beam
forming (hereinafter abbreviated as a cited document). The principle of operation is based on the data sequence of the received signal discretized at a sampling rate higher than the Nyquist rate.
The data rate is increased to an integral multiple of the sampling rate by an interpolation operation using a zero pad (hereinafter referred to as zero insertion) and a low-pass filter so that the delay time given to data can be finely changed.

Hereinafter, a receiving digital beamformer of the ultrasonic diagnostic apparatus of the cited example will be described with reference to FIG.

FIG. 7 is a schematic block diagram of a sector electronic scanning ultrasonic diagnostic apparatus. 7, reference numeral 104 denotes a zero inserter, 105 denotes a delay unit, 106 denotes a parallel adder, and 107 denotes an interpolator. The zero inserter 104, the delay unit 105, the parallel adder 106, and the interpolator 107 constitute a digital beamformer. I do.

First, a pulsar trigger signal from a control unit 101 is input to a pulsar receiver 102. The pulser trigger signal is subjected to phase control for performing electron focusing and sector scanning. Four pulsar receivers 102
Outputs a drive pulse for driving the oscillators T1 to T4 in response to a pulsar trigger signal. The vibrators T1 to T4 are 4
The ultrasonic wave is transmitted in the direction set by the drive pulse from one of the pulsar receivers.

The ultrasonic waves reflected in the subject are received by the same transducers T1 to T4, amplified by the pulsar receiver 102, and digitally converted by the A / D converter 103 at a sampling frequency fs equal to or higher than the Nyquist rate and a sampling interval Δt. Converted to a signal. Usually, a sampling frequency of about 20 MHz is selected for a 5 MHz ultrasonic reception signal. The digital signal output of the A / D converter 103 is zero-inserted in the zero inserter 104 as shown in FIG.
The number of zeros inserted between data is (M-1)
In this case, the data rate of the zero-inserted data output from the zero inserter 104 is M · fs. This M is called an oversampling magnification.

As an example, if M = 8, the data rate of the zero-inserted data is 20 MHz.multidot.8 = 160 M
Hz. The delay unit 105 gives a delay time to the zero-inserted data output from the zero inserter 104. The delay time given to the digital signal is an integral multiple of the minimum delay time unit (hereinafter, referred to as quantization time unit tq) that can be realized by the digital circuit system. The quantization time unit is usually selected as the reciprocal of the data rate frequency of the digital signal. In this case, since the data rate is 160 MHz, the quantization time unit is 6.
25 ns, which corresponds to 1/32 of one cycle of the sound wave.

[0008] The amount of delay time given to the digital signal is phase-controlled so that the receiving sensitivity is maximized in the direction in which the ultrasonic wave is transmitted, and is added by the parallel adder 106. When the zero inserter is not used, the data rate is 20 MHz, the quantization time unit is 50 ns, and this time corresponds to １ ／ of one cycle of the sound wave. Normally, in order to enable high-precision addition, that is, a beamform with few side lobes, in the parallel addition unit 106, the quantization time unit is a short time of about 1/10 to 1/40 or less of one cycle of the sound wave. To be elected.

An interpolation operation is performed by the interpolator 107 on the data added as described above. As the interpolation operation,
For example, low-pass filter processing by an FIR filter is performed. Since both the interpolation operation and the addition operation in the parallel addition unit 106 are linear operations, the order of the operations can be changed. That is, the addition and the interpolation operation after the zero insertion are equivalent to the case where the addition is performed after the interpolation after the zero insertion, and the case where the A / D converter that operates at the same sampling rate as the data rate in the zero insertion is used. Are equivalent to

As described above, the zero inserter 104 and the interpolator 107
By using the above, even when an A / D converter operating at a sampling frequency of about Nyquist rate is used, a quantization time unit corresponding to a data rate that is several times or more of that is realized, and a highly accurate beamform can be realized. Will be possible. The output of the interpolator 107 is converted into a video signal by a digital scan converter (hereinafter referred to as DSC) 108 and displayed on a display unit 109.

[0011]

However, in the above-described conventional ultrasonic diagnostic apparatus, it is necessary to realize a circuit which operates at high speed with an increased data rate in the zero inserter 104 and the interpolator 107 of the receiving digital beamformer. There was a problem that there is.

The present invention solves such a conventional problem, and eliminates the need for increasing the operation speed due to an increase in the data rate due to the insertion of zeros, and provides an excellent beamform that enables a highly accurate beamform. It is an object to provide an ultrasonic diagnostic apparatus.

[0013]

In order to achieve the above object, an ultrasonic diagnostic apparatus according to the first aspect of the present invention digitizes received signals from arranged transducers and stores the digitalized signals in a memory. The read data is input to a multi-phase adder constituted by adders provided in a parallel pipeline via a common data bus.

According to a second aspect of the present invention, an ultrasonic diagnostic apparatus digitizes received signals from the arranged transducers and stores the digitalized signals in a memory, and transfers data read from the memory to a common data bus having a shifter. Through a multi-phase adder constituted by adders provided in a parallel pipeline, a data selector is connected to one of the adders, and a common data is connected to one input of the data selector. The bus is directly connected, and the other inputs are connected to a common data bus via a latch. Two of these adders are added at the same time.

[0015]

Therefore, according to the first aspect of the present invention, a plurality of received signals from the arrayed oscillators are digitized, and the data stored and read out in the memory is input to the polyphase adder, whereby zero insertion is performed. There is no need to increase the operation speed with an increase in the data rate, and this has the effect of enabling a highly accurate digital beamform.

According to the second aspect of the present invention, a plurality of received signals from the arrayed vibrators are digitized, stored in a memory, and the read data is input to a polyphase adder, thereby reducing the number of zeros. There is no need to increase the operation speed due to an increase in the data rate due to insertion, and this has the effect of enabling a digital beamform with higher precision.

[0017]

【Example】

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram of a sector electronic scanning ultrasonic diagnostic apparatus. In FIG. 1, reference numeral 1 denotes an ultrasonic probe, which is composed of N transducers T1 to TN. In this example, N = 4 for simplicity of description. 2 is a main control unit for controlling the timing of each unit,
10 to 13 are pulsar receivers, 14 to 17 are A / D converters, 20 to 23 are memories, 24 to 27 are polyphase adders,
0 is an interpolator, 31 is a DSC, and 32 is a display unit. The memory and the polyphase adder connected to the transducer Ti are called an i-channel delay circuit. Memories 20 to 23, polyphase adder 24
27 and the interpolator 30 constitute a digital beamformer.

Next, the operation of the above embodiment will be described.
In FIG. 1, first, a trigger signal from the main control unit 2 is input to the pulsar receivers 10 to 13. These trigger signals are phase-controlled for electron focusing and sector scanning. The four pulsar receivers 10 to 13 generate drive pulses in response to these trigger signals, and output the oscillator T1.
To T4. The transducers T1 to T4 are driven by pulsar receivers 10 to 13 and transmit ultrasonic waves in a set direction. The ultrasonic wave reflected in the subject is the same transducer T1
〜T4 and sent to the A / D converter. The sampling frequency fs (= 1/1) is set by the A / D converters 14 to 17.
The received signal converted to digital data at [Delta] t; [Delta] t sampling interval) is written to the memories 20 to 23. The data written in the memories 20 to 23 is read out with the timing controlled so that the reception sensitivity becomes maximum in the direction in which the ultrasonic wave is transmitted. The memories 20 to 23 are used as delay elements by shifting write and read timings. The read data is added in the polyphase addition units 24 to 27. The data "zero" is input to the polyphase adder 24, and the outputs of the preceding multiphase adders 24 to 26 are input to the polyphase adders 25 to 27. The output of the polyphase adder 27 is subjected to an interpolation operation by an interpolator 30 by a low-pass filter function. The output of the interpolator 30 is the DSC 31
Is converted into a video signal and displayed on the display unit 32.

FIG. 2 is a more detailed block diagram of one of the polyphase adders 24-27. In FIG. 2, reference numeral 120 denotes a memory, CB denotes a common data bus connected to the output of the memory, 130 to 133 denote adders, s0 to s3 denote addition control signals, and are represented by sm (0 ≦ m ≦ 3). P0 to P3 are pipelines and are represented by Pm (0 ≦ m ≦ 3). 140
143 is a latch, 145 is a control unit, 146 is a gate,
mr is a read control signal of the memory 120, dd is a delay control signal, and sc is a sampling clock.

The control signal dd is input to the control unit 145,
The control unit 145 outputs an addition control signal sm and a memory read control signal mr. Common data bus CB, adder 1
30-133, pipeline Pm, latches 140-14
3. The control unit 145 and the gate 146 constitute a polyphase addition unit. The number of adders is equal to the number of pipelines,
The number is determined by the value of the oversampling magnification M as described later. Next, the operation of the first embodiment of the multi-phase addition unit will be described.

In FIG. 2, first, data RX (i, k) from the memory 120 (where i means the output from the transducer Ti and k means the k-th operation timing in the polyphase addition unit) Adder 1 via common data bus CB
30 to 133, the data P of the pipeline Pm
The following operation between D (i, k, m), that is, zero insertion, is performed at a rate equal to the sampling frequency fs.

That is, one of the adders 130 to 133,
Alternatively, in the case of zero, addition is performed with the data from the pipeline Pm.
Is output to the next pipeline Pm as it is. This state can be expressed by the following equation (1).

[0024]

(Equation 1)

Here, the right side of Equation 1 corresponds to the input of the adder, the left side corresponds to the output of the adder, and ZP (i, k, m) is a function indicating to which pipeline the addition is performed.

In general, ZP takes the following values for 0 ≦ m <M and 0 ≦ mm <M. ZP (i, k, m) = 1 For ZP (i, k, mm) = 0 mm ≠ m; add to pipeline Pm, insert zero into remaining pipeline. Or ZP (i, k, m) = 0 0 ≦ m ≦ 3; Zero insertion into all pipelines.

The zero insertion shown in Equation 1 is performed by the memory 120, the adders 130 to 133, and the control unit 145 as follows. First, the adders 130 to 133 have the following operation modes.

Addition mode Y = A + B sm =
In the case of 1, the data bus mode Y = B sm =
In the case of 0, A: input value from the common data bus CB B: input value from the pipeline Pm Y: output of the adder As described above, the operation mode is controlled by the addition control signal sm.

Table 1 shows the addition control signal sm and the memory 1
20 read control signals mr (read is possible with mr = 1,
s0, s0, etc.) are changed by the delay control signal dd at each operation timing k.
This is shown as a bit pattern of s1, s2, s3, mr.

[0030]

[Table 1]

As shown in Table 1, when dd = 0, the bit pattern does not change. When dd = 1, the bit pattern shifts to the right. When mr = 1, the reading of the memory is inhibited. Mr = 1. In the next calculation step, mr = 0
It is. sm = 0 corresponds to zero insertion. These calculation steps are performed at a speed equal to the sampling clock SC.

FIGS. 3 and 4 show how zeros are inserted in the polyphase adder and how interpolation is performed by the interpolator 30 in the first embodiment. In order to make the figure easier to understand, the input data from the pipeline Pm to the adders 130 to 133 are all set to zero.

In FIG. 3, at all operation timings k, m
= 1, ZP (i, k, m) = 1, and three "zeros" are inserted into the data RX (i, k) as shown in FIG. In this case, the data PD (i, k, m) of the outputs of the adders 130 to 133 with zero inserted.
Can be regarded as the delay time tq given to the input data RX (i, k). In this case, the oversampling magnification M is 4. Thus, the value of M matches the number of adders and the number of pipelines Pm.

The interpolation is generally performed by a low-pass FIR digital filter. It is assumed that the data rate of the output of the FIR filter is selected to be the same as the sampling frequency fs. When the order of the filter is equal to M, the output Z (k) of the filter is expressed by the following equation (2).

[0035]

(Equation 2)

Alternatively, when the order of the filter is equal to 2M, the output Z (k) of the filter is expressed by the following equation (3).

[0037]

(Equation 3)

In FIG. 4, at the same time as zero insertion, the delay time is changed and controlled with the precision of the quantization time unit tq (= 1 / M · fs) for the data RX (i, k) at each operation timing k. It shows how it works.

In the figure, when k = 1, ZP at m = 0
When (i, k, m) = 1 and m ≠ 0, ZP (i, k,
m) = 0, k = 2, ZP (i, k,
m) = 1, ZP (i, k, m) = 0, k for m ≠ 1
= 3, ZP at m = 1 as in the case of k = 2
When (i, k, m) = 1 and m ≠ 1, ZP (i, k,
m) = 0, k = 4, ZP (i, k,
m) = 1, ZP (i, k, m) = 0, k for m ≠ 2
= 5, ZP (i, k, m) = 1, m at m = 3
ZP (i, k, m) = 0 at # 3, 0 at k = 6
ZP (i, k, m) = 0 when ≦ m ≦ 3, ZP (i, k, m) = 0 when m ≠ 2, ZP (i, k, m) = 1 when m = 0 when m = 2 , M ≠ 3, ZP
(I, k, m) = 0.

As described above, a constant delay time is given in FIG. 3, whereas in FIG.
Quantization time unit tq for data RX (I, K)
M (0 ≦ m ≦ 3) times the delay time can be added.

On the other hand, the writing and reading control of the memory 120 gives a delay time which is an integral multiple of the sampling interval.

In this way, the quantization time unit tq 0 to 0
The sum of (M-1) times the delay time and the integer times the sampling interval, that is, a delay time that is an arbitrary integer times the quantization time unit tq is added to the data of the received signal of each channel at each operation timing. Can be done. As described above, the method of changing the delay time for each operation timing, that is, for each sampling timing of the A / D converters 14 to 17, is extremely difficult in the dynamic focus method in which the focal length such as electron focusing is changed according to the depth of the received echo. It is a useful technique.

As described above, according to the first embodiment, as shown in FIGS. 1 and 2, a plurality of reception signals from the arrayed transducers are digitized and stored in the memory, and are read out from the memory. By inputting data to the polyphase adder,
There is no need to increase the operation speed due to an increase in the data rate due to zero insertion, and this has the effect that a highly accurate digital beamformer can be realized.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIGS.

FIG. 4 is a block diagram showing the configuration of the polyphase addition unit. In FIG. 5, 145 is a control unit, 160 is a shifter, 161 is a latch, 162 is a data selector, sm is an addition control signal, mr is a memory read control signal, sh
Is a shifter control signal, se is a selector control signal, dd is a delay control signal, and the other parts are the same as those in FIG. The control signal dd is input to the control unit 145, and the control unit 145 outputs the addition control signal s
m, memory read control signal mr, shifter control signal s
h, outputs a selector control signal se. A polyphase adder is constituted by the common data bus CB, the adders 130 to 133, the pipeline Pm, the latches 140 to 143, the controller 145, the gate 146, the shifter 160, the latch 161, and the data selector 162.

Next, the operation of the second embodiment of the multi-phase addition unit will be described. In FIG. 5, first, the memory 120
From the data RX (i, k) (where i is the transducer Ti, 1
≤i≤N, and k means the k-th operation timing in the multi-phase addition unit) is input to the adders 130 to 133 via the common data bus CB, and the data of the pipeline Pm With respect to the PD (i, k, m), the following calculation represented by Expression 4 or Expression 5 or Expression 6 is performed at a speed equal to the sampling frequency fs.

[0047]

(Equation 4)

[0048]

(Equation 5)

[0049]

(Equation 6)

Where the right side of Equations 4 to 6 is the input of the adder,
The left side corresponds to the output of the adder, and ZP (i, k, m) is a function corresponding to zero insertion. ZP takes the following values.

ZP (i, k, 0) = 1 ZP (i, k, m) = 0, m ≠ 0 or ZP (i, k, 1) = 0.5 ZP (i, k, 2) = 0.5 ZP (i, k, m) = 0 m {1, m}
2 or ZP (i, k, 2) = 1 ZP (i, k, m) = 0, m ≠ 2 or ZP (i, k, 2) = 0.5 ZP (i, k, 3) = 0.5 ZP (i, k, m) = 0 m {2, m}
3 or ZP (i, k, M−1) = 0.5 ZP (i, k + 1, 1) = 0.5 ZP (i, k, m) = 0 m ≠ M−1,
m ≠ 1 The zero insertion shown in the above equations 4 to 6 is performed by the memory 120, the adders 130 to 133, the control unit 145, the shifter 160, the latch 161, and the data selector 162 as follows. First, the adders 130 to 133 have the following operation modes.

Addition mode Y = A + B sm =
In the case of 1, the data bus mode Y = B sm =
In the case of 0, A: input value from the common data bus CB B: input value from the pipeline Pm Y; output of the adder The shifter 160 has the following operation modes.

Data bus mode Y = E sh =
In the case of 1, the shifter mode Y = E / 2 sh =
In the case of 0, E; input value from memory output Y; output value of shifter The combination of latch 161 and data selector 162 has the following operation modes.

One clock delay Y (k) = E (k−1) where
se = 1 Zero clock delay Y (k) = E (k) where
se = 0, where E (k-1); input value of the data selector that passed through the latch E (k); input value of the data selector that did not pass through the latch Y; output value of the data selector The signal sm, the read control signal mr of the memory 120 (read is possible when mr = 1, read is prohibited when mr = 0), the shifter control signal sh, and the selector control signal se are changed by the delay control signal dd at each operation timing k. One example is s0, s1, s2, s3, m
This is shown as a bit pattern of r.

[0055]

[Table 2]

As shown in Table 2, when dd = 0, the bit pattern does not change, when dd = 1, the bit pattern shifts to the right, when mr = 1, memory reading is inhibited, and mr = 1. In the next calculation step, mr = 0
It is. sm = 0 corresponds to zero insertion.

FIG. 6 shows the manner in which zeros are inserted in the polyphase addition section and interpolation is performed in the interpolator 30 in the second embodiment. In order to make the figure easier to understand, the input data from the pipeline Pm to the adders 130 to 133 are all set to zero.

Simultaneously with the insertion of zero, half of the quantization time unit, t
This shows how the delay time is changed and controlled with an accuracy of q / 2, (= １ ／ M · fs).

In the figure, when k = 1, ZP at m = 0
When (i, k, m) = 1 and m ≠ 0, ZP (i, k,
m) = 0, k = 2, ZP (i,
k, m) = 0.5, ZP (i, k, m) when m ≠ 1
= 0, k = 3, ZP (i, k, m) = 0.5 at m = 0,1 and ZP (i, k, m) = m ≠ 0.1, as in the case of k = 2 0.5, k = 4, ZP (i, k, m) = 1 at m = 1, ZP (m, 1)
(I, k, m) = 0, and similarly, when k = 8, m =
3, ZP (i, k, m) = 1, and m ≠ 3, ZP
When P (i, k, m) = 0 and k = 9, Z = m = 3
P (i, k, m) = 0.5, and m ≠ 3, ZP (i, k, m)
k, m) = 0, k = 10, ZP at m = 0
When (i, k, m) = 0.5 and m ≠ 0, ZP (i,
k, m) = 0, k = 11, ZP at m = 0
When (i, k, m) = 1 and m ≠ 0, ZP (i, k,
m) = 0.

As described above, in FIG. 6, a half of the quantization time unit and a delay time of 0 to 2M-1 times tq / 2 are added to the data RX (I, K) at each operation timing. Can be done.

On the other hand, the writing and reading control of the memory 120 gives a delay time which is an integral multiple of the sampling interval.

In this way, half of the quantization time unit, t
The sum of the delay time of 0 to (2M−1) times q / 2 and the delay time of an integer multiple of the sampling interval, that is, a delay time of an arbitrary integral multiple of half the quantization time unit tq / 2, is calculated for each operation timing. Can be added to the data of the received signal of each channel. As described above, the method of changing the delay time for each calculation timing is a very useful technique in the dynamic focus method in which the focal length of electron focusing or the like is changed according to the depth of the received echo.

As described above, according to the second embodiment, as shown in FIG. 5, a plurality of received signals from the arrayed vibrators are digitized and stored in the memory, and the data read from the memory is multiplied. By inputting the data to the phase adder, it is not necessary to increase the speed of the operation due to the increase in the data rate due to zero insertion, and this has the effect that a highly accurate digital beamform can be realized.

[0064]

According to the first aspect of the present invention, as is apparent from the above embodiment, a plurality of received signals from the arrayed transducers are digitized and stored in a memory, and the data read from the memory is shared with a common data. By inputting to the polyphase adder composed of adders provided in the parallel pipeline via the bus, high-precision digital This has the effect of enabling beamforming.

According to the second aspect of the present invention, the received signals from the arranged transducers are digitized and stored in a memory, and the data read from the memory is transferred to a common data bus having a shifter. Through a multi-phase adder constituted by adders provided in a parallel pipeline, in particular, one of the adders is connected to a data selector, and one input of the data selector is connected to a common input. The data bus is directly connected, and the other inputs are connected to a common data bus via a latch. By simultaneously adding these two adders, the data rate increases due to zero insertion. This eliminates the need for increasing the calculation speed, and has the effect of enabling a highly accurate digital beamform with a fine quantization time unit.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an ultrasonic diagnostic apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration of a polyphase addition unit according to the first embodiment.

FIG. 3 is a diagram for explaining how a polyphase adder inserts zeros in the first embodiment;

FIG. 4 is a view for explaining a state of zero insertion of a polyphase addition unit in the first embodiment.

FIG. 5 is a block diagram showing a detailed configuration of a polyphase adder according to a second embodiment of the present invention.

FIG. 6 is a diagram for explaining an operation in zero insertion of a polyphase addition unit in the second embodiment.

FIG. 7 is a schematic block diagram of a conventional ultrasonic diagnostic apparatus.

FIG. 8 is a diagram for explaining a state of zero insertion in a digital beamformer of a conventional device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Probe 14-17 A / D converter 20-23 Memory 24-27 Polyphase addition part 30 Interpolator 31 DSC 32 Display part CB Common data bus P0-P3 Pipeline 130-133 Adder 140-143 Latch 145 Control part 160 shifter 161 latch 162 selector

Continuation of front page (56) References JP-A-3-103787 (JP, A) JP-A-54-136135 (JP, A) JP-A-2-164352 (JP, A) JP-A-5-146441 (JP, A) , A) JP-A-61-52864 (JP, A) JP-A-5-7587 (JP, A)

Claims (2)

(57) [Claims] 1. An array oscillator is driven to move in a set direction.
Means for transmitting a sound wave, and a memory for storing the received signal from the transducer array, wherein a multi-phase addition section connected to the output of the memory, the multi-phase addition unit and a plurality of pipelines, wherein An adder provided in each of the pipelines, a common data bus commonly connected to the adder, the common data bus is connected to the memory, and the polyphase adder is connected via the pipeline Connected in series,
Have a control unit which controls the zero insertion and reading of the memory in the multi-phase addition section, the control section sending ultrasound
Of the memory so that the receiving sensitivity increases in the
An ultrasonic diagnostic apparatus which controls reading . 2. A multi-phase adder comprising: a shifter connected to a common data bus; a latch connected to the shifter; an output of the shifter and a data selector connected to an output of the latch. 2. The ultrasonic diagnostic apparatus according to claim 1, wherein an input of the adder is connected to an output of the selector.