JP2628311B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a one-chip microcontroller having a processor (hereinafter, referred to as a “CPU”), an address bus, a data bus, and a built-in peripheral bus interfaced with system control signals. About computers.

[Summary of the Invention]

According to the present invention, a CPU and a peripheral can be individually tested by incorporating a control circuit for a data bus in a one-chip microcomputer having a built-in peripheral with a bus interface.

[Conventional technology]

 FIG. 2 shows a block diagram of a conventional example.

In the conventional one-chip microcomputer, the peripheral 20 and the CPU 19 shown in FIG. 1 cannot be separated from the external data bus 1, so that it is impossible to test each of them independently. Was done indirectly.

[Problems to be solved by the invention]

In the prior art, as shown in FIG.
And the peripheral 20 cannot be individually tested, and the peripheral 20 can be tested only by the CPU 19.

The present invention solves these problems, and aims to realize a function of directly controlling the bus and the read / write signal of the CPU 19 from the outside, thereby enabling individual tests of the CPU 19 and the peripheral 20. In this way, the aim is to reduce the test time in LSI testers and improve the productivity of test programs.

[Means for solving the problem]

A microcomputer according to the present invention is a microcomputer comprising a single chip including a processor and a peripheral that interfaces with the processor via a bus line. The microcomputer is provided between an external bus line and a first internal bus line. A first control logic for transmitting data input from one bus line to the other bus line via a latch circuit and controlling a transmission direction and high impedance of the data; and a first internal bus line; A second internal bus line that interfaces with the peripheral, transmits data input from one bus line to the other bus line via a latch circuit, and transmits the data in the transmission direction and high impedance A second control logic for controlling the first internal bus line; A connection to a third internal bus line that interfaces to the processor;
No connection in peripheral test mode
And in the peripheral test mode, based on a latch clock signal of the latch circuit of the first control logic and the latch clock signal of the latch circuit of the second control logic. Is switched to a through operation.

[Operation] Since the present invention has the above configuration, it is possible to individually test the peripheral 20 and the CPU 19 which are internally bus-interfaced with the CPU 19.

〔Example〕

FIG. 3 shows a block diagram of one embodiment of the present invention. The external data bus 1 is connected to the first control logic 2, and the other end is connected to the second control logic 4 and the third control logic 16 as the first internal data bus 3. The other end of the second control logic 4 is a data bus to a plurality of peripherals 20 and 21 as a second internal data bus 5. The other end of the third control logic is the third
Connected to the internal data bus 17 of the
8 is output to the external address bus 11 via the fourth control logic 15. Address bus 11 is address decoder 12
To generate peripheral selection signals 13 and 14.
Reference numeral 10 denotes a peripheral test mode signal, which is connected to all control logics and has an address bus 11, a data bus, and an external bus.
Control R / 6. Reference numeral 7 denotes an output of R / from the CPU 19, which is input to the fifth control logic 8. An external R / 6 is connected to the fifth control logic 8, and the peripheral test mode signal 10 makes the R / 6 an input terminal. The fifth control logic output 9 controls the input / output of the first control logic 2 and the second control logic 4 together with the peripheral test mode signal 10 and simultaneously becomes a read / write signal of the peripheral. I have.

Reference numerals 13 and 14 denote chip select signals to the peripherals 20 and 21. In the peripheral test mode, the clocked gates 41 and 42 are inactive and are directly selected from the outside. In the non-test mode, the peripherals are output by the output of the address decoder 12. 20, 21 are selected.

4 to 8 show circuit diagrams for one bit of the control logic.

FIG. 4 is a circuit diagram of the first control logic 2 in FIG. The external data bus 1 is a bidirectional bus whose direction changes according to the internal R / 9, and a clocked gate is connected to the outputs of the external read latch 22 and the first write latch 25 in FIG. Therefore, the read, write, and high impedance states can be controlled using the peripheral test mode signal and the internal R / 9. The external data bus 1 is input to the external read latch 22 and is controlled by the external read latch enable 32. The output of the external read latch 22 is input to a first clocked gate 23, and the output of the first clocked gate is controlled by an internal R / 9 that is inverted only in a peripheral test mode by a first exclusive OR 33. Being
Output to the first internal data bus 3.

The first internal bus 3 is input to a second write latch 26 and is controlled by a second write latch enable 36. Second
The output of the write latch 26 is input to the first write latch 25, and the first write latch 26 is controlled by the first write latch enable 35. The output of the first write latch 25 is input to the second clocked gate 24,
The clocked gate 24 of the second exclusive OR 34
Is controlled by the internal R / 9 which is inverted only in the peripheral test mode.

FIG. 5 is a circuit diagram of the second control logic 4 in FIG. Since a clocked gate is connected to the output of the internal read latch 31 and the output of the fourth write latch 28 in FIG. 5, read, write, and high impedance are performed using the signal of the peripheral test mode and the internal R / 9. You can control the state of. The first internal bus 3 is input to a third write latch 27, and the third write latch 27 is controlled by the second write latch enable 36.
The output of the third write latch 27 is input to a fourth write latch 28, and the fourth write latch 28 is controlled by a first write latch enable 35.

The output of the fourth write latch 28 is input to a third clocked gate 29, and the third clocked gate
29 is controlled by the internal write signal 9 and is output to the second internal data bus 5. The second internal data bus 5 is input to the internal read latch 31, and the internal read latch 31
Is controlled by the internal read latch enable 37. The output of the internal read latch 31 is input to a fourth clocked gate 30, and the fourth clocked gate 30 is controlled by the internal R / and outputs to the first internal data bus.

FIG. 6 is a circuit diagram of the third control logic 16 in FIG. The third control logic 16 is a logic for disconnecting the third internal data bus 17 of the MPU 19 from the first internal data bus 3 in the peripheral test mode. First
The transmission gate 38 connecting the internal data bus 3 and the third internal bus 17 is controlled by the peripheral test mode signal 10.

FIG. 7 is a circuit diagram of the fourth control logic 15 in FIG. The fourth control logic 15 is a logic for setting the internal address bus 18 of the CPU 19 to high impedance in the peripheral test mode. The output 11 of the sixth clocked gate 39 connected to the internal address bus 18 is controlled by the peripheral test mode signal 10.

FIG. 8 is a circuit diagram of the fifth control logic 8 in FIG. The fifth control logic 8 usually has an output terminal R /
Reference numeral 6 denotes a logic for setting an input / output terminal in the peripheral test mode. 7 is the read / write (R
/) Output, which is the seventh clocked gate 4
Entered as 0. The seventh clocked gate 40 is controlled by the peripheral test mode signal 10 and receives an external R /
6 and internal R / 9.

In the normal mode, the sixth control logic of the sixth
The peripheral test signal 10 in the figure is inactive (LO
W), the transmission gate in the figure becomes active, the clocked gate in the figure becomes active in FIG. 7 as well, and the clocked gate in the same figure becomes active in FIG. /
For writing, the CPU 19 becomes the bus master.

In the read in the normal mode, the data flow direction of the data bus in the first control logic 2 and the second control logic 4 is the direction from the external data bus 1 to the first internal data bus 3, respectively. 2 from the internal data bus 5 to the first internal data bus 3. At that time, the external read latch enable 32 and the internal read latch enable 37 are active and enabled in synchronization with the respective read signals. Latch input data.

In the write in the normal mode, the data flow directions of the data bus in the first control logic 2 and the second control logic 4 are respectively the direction from the first internal data bus 3 to the external data bus 1 and the first internal logic bus. The direction is from the data bus 3 to the second internal data bus 5, and at that time, the write latches 26 and 25 and the write latches 27 and 28 each operate as a master-slave type flip-flop, and output data to the end of the latch signal. Synchronously, external data bus 1
Output to

In the peripheral test mode, the third to fifth control logics are all inactive, the CPU 19 is released from all buses, and external devices and LSIs connected to the external address bus 11, the external data bus 1, and the external R / 6.
A tester or the like becomes the master of the bus.

In the read in the peripheral test mode, the data flow direction of the data bus in the first control logic 2 and the second control logic 4 is the first internal data bus 3 respectively.
And the direction from the second internal data bus 5 to the first internal data bus 3, and the first and second write latch enables 35 and 36 and the internal read latch enable 37 at that time are Becomes active and each latch is through.

In the write in the peripheral test mode, the data flow direction of the data bus in the first control logic 2 and the second control logic 4 is the direction from the external data bus 1 to the first internal data bus 3, respectively. The direction is from the first internal data bus 3 to the second internal data bus 5, and at that time the external read latch enable 32 and the third and fourth write latches 35 and 36 are active and each latch is through.

In the peripheral test mode, the clocked gates 41 and 42 become inactive in FIG. 3 and the chip select signals 13 and 14 become input / output signal lines in the peripheral test mode. Control directly from outside. When the peripheral test mode is not set, the clocked gates 41 and 42 become active, so that the internal peripherals 20 and 21 are selected by the output of the address decoder 12.

In the non-test mode, the chip select signals 13 and 14 indicating the address of the peripheral are connected to the outside, so that they can be used as an inhibit signal for preventing a bus conflict with the external peripheral.

〔The invention's effect〕

The microcomputer of the present invention is provided between an external bus line and a first internal bus line in a microcomputer formed of a single chip including a processor and a peripheral that interfaces with the processor via a bus line. A first control logic for transmitting data input from one bus line to the other bus line via a latch circuit and controlling a transmission direction and high impedance of the data; A second internal bus line that interfaces with the peripheral, transmits data input from one bus line to the other bus line via a latch circuit, and transmits the data in the transmission direction and high impedance A second control logic for controlling, the first internal bus line, A third control logic for disconnecting a connection between the third internal bus line interfacing with the processor and the third internal bus line in the peripheral test mode, wherein a latch circuit of the first control logic and a second control logic are provided. In the peripheral test mode, the operation of the latch circuit is switched from a latch operation to a through operation based on a latch clock signal of a latch circuit of the control logic. A pulse having a small phase difference from the clock signal can be received as data, thereby preventing a problem of reading erroneous data. In addition, since data is latched based on the latch clock signal, a bus at the time of switching of the transmission direction is used. Conflicts are prevented.

On the other hand, in the peripheral test mode, the peripheral can be tested independently of the processor.
Further, in the peripheral test mode, data is transmitted from one bus line to the other bus line regardless of the timing of the latch clock signal. Therefore, not only can test data be transmitted to peripherals at high speed,
By shifting the phase of the data input to the external bus line when writing data to the peripheral, a test (so-called AC test) of the timing margin of writing data to the peripheral can also be performed.

Therefore, the microcomputer of the present invention can operate in the normal mode only by controlling the latch clock signal of the latch circuit, even if the microcomputer includes a microprocessor for transmitting data on the bus line via the latch circuit and a peripheral. It is not possible to test peripherals at high speed independently of the processor, and it also enables AC testing.

In addition, in a one-chip microcomputer having a built-in peripheral with a bus interface, each of the CPU and the peripheral can be individually tested, so that the microcomputer can be independently tested by the CPU and the peripheral. Therefore, for a series of microcomputers with various peripherals for one MPU, the test program development period for sharing the test method can be shortened, and the test time itself can be reduced without using the peripheral via the CPU. Since they can be controlled in series, they can be made very short.

Further, even if the number of peripherals is plural, it is possible to easily and independently perform a test by separating the peripheral from the CPU as in the present invention.

[Brief description of the drawings]

 FIG. 1 is a block diagram of the present invention. FIG. 2 is a block diagram according to a conventional technique. FIG. 3 is a block diagram showing one embodiment of the present invention. In the figure, 1 is an external data bus, 2 is a first control logic, 3 is a first internal data bus, 4 is a second control logic, 5 is a second internal data bus, 10 is a peripheral. Test mode signal In the figure, 16 is the third control logic. In the figure, 17 is the third internal data bus. In the figure, 19 is the CPU. FIG. 4 is a circuit diagram of the first control logic 2 in FIG. FIG. 5 is a circuit diagram of the second control logic 4 in FIG. FIG. 6 is a circuit diagram of the third control logic 16 in FIG. FIG. 7 is a circuit diagram of the fourth control logic 15 in FIG. FIG. 8 is a circuit diagram of a fifth control logic 8 in FIG.

Continuation of the front page (56) References JP-A-61-54470 (JP, A) JP-A-60-245052 (JP, A)

Claims (1)

(57) [Claims] A microcomputer comprising a single chip including a processor and a peripheral interfacing with the processor via a bus line, the microcomputer being provided between an external bus line and a first internal bus line. A first control logic for transmitting data input from a bus line to the other bus line via a latch circuit, and controlling a transmission direction and high impedance of the data; the first internal bus line and the peripheral And a second internal bus line interfacing with the first bus line, and transmits data input from one bus line to the other bus line via a latch circuit to control the transmission direction and high impedance of the data. A second control logic for interfacing with the first internal bus line and the processor. A third control logic for disconnecting a connection with the third internal bus line to be connected in the peripheral test mode, wherein a latch circuit of the first control logic and the second control logic are provided. A microcomputer that switches an operation of the latch circuit from a latch operation to a through operation in the peripheral test mode based on a latch clock signal of the latch circuit.