JP2622138B2 - Information processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to a data flow type in which an operation is performed upon arrival of data, and a program memory for storing a data flow program. The present invention relates to an information processing device provided outside.

[Prior Art] FIG. 3 is a schematic block diagram of a conventional data flow type information processing apparatus, and FIG. 4 is a diagram showing a part of contents stored in a program memory.

First, a configuration and a schematic operation of a conventional data flow type information processing apparatus will be described with reference to FIGS. In FIG. 3, a program storage unit 1 includes a program memory (not shown), and stores a data flow program including the contents (destination information) of a destination field of an input data packet and instruction information in the program memory. doing. Then, the program storage unit 1 reads out the destination information and the instruction information by specifying an address based on the destination information, and stores and outputs each information in the destination field and the instruction field of the input data packet.

The paired data detection unit 2 waits for a data packet input from the program storage unit 1, and replaces the operand data of one of the two data packets having the same destination information with the data field of the other data packet. And output it. Arithmetic processing section 3 decodes the instruction information of the data packet input from paired data detecting section 2, performs predetermined arithmetic processing on the two operand data, and stores the result in the data field of the input data packet. And the program storage unit 1
Is output to

In the data flow type information processing apparatus shown in FIG. 3, the data packets continue to rotate in the order of program storage unit 1 → data detection unit 2 → operation processing unit 3 → program storage unit 1 →. The arithmetic processing based on the program stored in the program storage unit 1 proceeds.

FIG. 5 is a diagram showing a schematic configuration of the program storage unit 1 shown in FIG. In FIG. 5, the input data latch unit 4 holds the current destination information, and erases the instruction information. The input data latch unit 4 also latches operand data. The destination information latched by the input data latch unit 4 is supplied to an address calculation unit 5, and the address of the program memory 6 is calculated from the destination information. The program memory 6 stores a data flow program including destination information and instruction information as shown in FIG. The new destination information and instruction information calculated from the program memory 6 are provided to the output data latch unit 7 and latched. The output data latch unit 7 directly latches the operand data latched by the input data latch unit 4.

[Problems to be Solved by the Invention] In the conventional data flow type information processing apparatus shown in FIGS. 3 to 5, all of the instruction information readout portion of the program is built in the apparatus (in advance, It is necessary to provide in advance a memory having a capacity enough to store all programs. However, in general, it is difficult to optimize the capacity of the program memory, regardless of whether the information processing device is composed of a plurality of semiconductor components or one LSI, and the A flexible hardware configuration cannot be taken.

Therefore, it is conceivable to externally attach the program instruction 6 to the program storage unit 1 to appropriately increase or decrease the capacity of the program memory 6. However, in the data flow type information processing apparatus, even if data is provided from the arithmetic processing unit 3 to the program storage unit 1, the data must be processed one by one. When it is sent, while processing the first data, it is necessary to wait for the subsequent data, and there is a problem that the waiting time for the data is increased and the processing speed is reduced. Was.

Therefore, a main object of the present invention is to provide an information processing apparatus capable of performing data processing without waiting time even when data is sequentially output from an arithmetic processing unit.

[Means for Solving the Problems] An information processing apparatus according to the present invention is a data flow type information processing apparatus in which a program memory for storing a data flow program in which destination information and instruction information are set is provided outside the apparatus. Input storage means for storing the operand, destination information, and generation information among the operands, instruction information, destination information, and generation information included in the input data packet; Based on the destination information and generation information stored in the input storage means, and an address for specifying the output storage means for storing the operand, destination information, and generation information stored in the input storage means. Read address calculating means for calculating information; and address information specified by the read address calculating means. Means for storing the operands, destination information and generation information of the input storage means in the output storage means, and calculating a read address of the program memory based on the destination information and generation information stored in the output storage means Address calculation means, and address information specifying output storage means for storing destination information and instruction information read from the read address of the program memory based on the destination information and generation information given to the address calculation means. A write address calculating means for calculating; a destination information and instruction information read from the program memory in the output storage means specified by the address information calculated by the write address calculating means; The operand, instruction information, destination information, Means for outputting proxy information as an output data packet; and contention arbitration means for arbitrating contention between the calculation result of the read address calculation means and the calculation result of the write address calculation means. .

FIG. 1 is a block diagram showing the contents of a program storage unit included in an embodiment of the present invention.

First, the configuration of one embodiment of the present invention will be described with reference to FIG. The program storage unit shown in FIG.
The program providing unit 11 is provided inside the apparatus, and the program memory unit 12 is provided outside the apparatus.

The program providing unit 11 includes an input data latch unit 13, a read address calculation unit 14, a write address calculation unit 15, and a contention arbitration mechanism.
16 and an output data latch unit 24. The input data latch unit 13 latches not only the operand data together with the current destination information but also the generation number in the same manner as the input data latch unit 4 shown in FIG. The command information is deleted. The destination information and generation number information latched by the input data latch unit 13 are given to the read address calculation unit 14. The read address calculator 14 calculates the address of the output data latch 24 corresponding to the generation number information on a one-to-one basis, based on the generation number information and the destination information. On the other hand, the write address calculation unit 15 receives the destination information and the generation number information latched by the data latch unit 25 described later from the output data latch unit 24 via the address calculation unit 21 described later, and On the basis of the generation number information and the generation number information, an address for writing the destination information and the instruction information read from the program memory 12 is calculated.

The read address calculated by the read address calculation unit 14 and the write address calculated by the write address calculation unit 15 are given to the contention arbitration mechanism 16. The contention arbitration mechanism 16 is configured such that the read address and the write address
When the same area is designated, access conflict is avoided. If there is a conflict, only one of the write address and the read address is output with priority and the other is put on standby. The output data latch unit 24 includes a latch unit 17 that latches a plurality of generation number information, a latch unit 18 that latches destination information corresponding to each generation number, and a latch unit that latches instruction information corresponding to each generation number. 19, and a latch unit 20 for latching operand data corresponding to each generation number. The latch unit 17 latches the generation number information latched by the input data latch unit 13 in an area specified by the read address calculated by the read address calculation unit 14. The latch units 18 and 19 latch the new destination information and instruction information read from the program memory unit 12 in an area specified by the write address calculated by the write address calculation unit 15. The latch unit 20 latches the operand data latched by the input data latch unit 13 in an area specified by the read address calculated by the read address calculation unit 14. The address calculator 21 has a latch 17 and
A set of generation number information and destination information latched at 18 is input, and based on them, the address of the program memory 23 is calculated. The address calculated by the address calculation unit 21 is given to the program memory unit 12.

The program memory unit 12 includes an address latch unit 22, a program memory 23, and a data latch unit 25. The address latch unit 22 latches the address calculated by the address calculation unit 21. As shown in FIG. 4, the program memory 23 stores destination information and instruction information as one set, and is specified by the output of the address latch unit 22. The program memory 23 reads out the destination information and the instruction information from the specified address, and supplies it to the data latch unit 25. Data latch unit 25 is an address calculation unit
The destination information and generation number information input to 21 and the destination information and instruction information read from the program memory 23 are latched for one set. The generation number information and the destination information latched by the data latch unit 25 are supplied to the write address calculation unit 15, and the destination information and the instruction information read from the program memory 23 are supplied to the latch units 18 and 19.

FIG. 2 is a diagram for explaining an access method in one embodiment of the present invention.

Next, the operation of one embodiment of the present invention will be described with reference to FIG. 1 and FIG. The input data packet is latched by the input data latch unit 13 from the arithmetic processing unit 3. That is, the operand data, the destination information, and the generation number information are latched by the input data latch unit 13, but the instruction information is erased. The read address calculation unit 14 calculates a read address based on the destination information and the generation number information, specifies the addresses of the latch units 17, 18 and 20 in the data output latch unit 24, and outputs the generation latched by the input data latch unit 13. The number information is latched in the latch section 17, the destination information is stored in the latch section 18 corresponding to the generation number information, and the latch section
Latch the operand data to 20. Thus, the input data latch unit 13 can receive the next input data packet.

Generation number information latched by the latch unit 17 and the latch unit 18
Address calculation unit based on the destination information latched in
21 calculates the address of the program memory 23. The address is latched in the address latch 22. The program memory 23 reads out destination information and instruction information corresponding to the address latched by the address latch 22 and performs data latching.
Output to 25.

On the other hand, the write address calculation unit 15 is based on the generation number information and the destination information given to the address calculation unit 21, and outputs the output data latch unit for latching the instruction information and the destination information latched by the data latch 25. Latch section at 24
Calculate the addresses of 18,19 areas. Then, the instruction information and the destination information read from the program memory 23 are latched at that address. The output data packet composed of the operand data, the instruction information, the destination information, and the generation number information latched by the output data latch unit 24 is supplied to the paired data detection unit 2.

Therefore, according to one embodiment of the present invention, the input data packets are sequentially input from the arithmetic processing unit 3 to the input data latch unit.
Even if the input data packet is given to the input data packet 13, the operand data, the instruction information, the destination information, and the generation number information are sequentially stored in the output data latch unit 24 in the order of the generation number, so that the input data packet waits on the input side of the program storage unit 1. And the waiting time is reduced accordingly, and the processing speed can be increased.

[Effects of the Invention] As described above, according to the present invention, each time an input data packet is provided, the corresponding destination information and instruction information are read from the program memory and sequentially stored in the output storage means. Even if input data packets are sequentially input, the waiting time can be reduced and the processing speed can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. FIG. 2 is a diagram for explaining an access method in one embodiment of the present invention. FIG. 3 is a block diagram of a conventional data flow type information processing apparatus. FIG. 4 is a diagram showing a part of the contents stored in the program memory.
FIG. 5 is a block diagram showing a program storage section of a conventional information processing apparatus. In the figure, reference numeral 2 denotes a paired data detection unit, 3 denotes an operation processing unit,
Is a program adding unit, 12 is a program memory unit, 13 is an input data latch unit, 14 is a read address calculation unit, 15 is a write address calculation unit, 16 is a contention arbitration mechanism, 17 to 20 are latch units, and 21 is an address calculation. , 22 is an address latch, 23 is a program memory, 24 is an output data latch, and 25 is a data latch.

Claims (1)

(57) [Claims] 1. A data flow type information processing apparatus provided with a program memory for storing a data flow program having destination information and instruction information as a set, the operand being included in an input data packet, instruction information ,
Of the destination information and the generation information, an input storage means for storing operands, destination information, and generation information; a plurality of output storage means for storing operands, instruction information, destination information, and generation information; Read address calculating means for calculating address information for specifying an output storage means for storing operands, destination information and generation information stored in the input storage means, based on the destination information and generation information stored in the input storage means; Means for storing operands of the input storage means, destination information, and generation information in the output storage means specified by the address information calculated by the calculation means; and destination information and generation information stored in the output storage means. Address calculation means for calculating a read address of the program memory based on the program memo; Write address calculating means for calculating address information for specifying output storage means for storing destination information and instruction information read from the read address based on the destination information and generation information provided to the address calculating means; Means for storing destination information and instruction information read from the program memory in the output storage means specified by the address information calculated by the write address calculation means; Means for outputting an operand, instruction information, destination information and generation information of the output storage means as an output data packet; and contention arbitration means for arbitrating contention between the calculation result of the read address calculation means and the calculation result of the write address calculation means. An information processing apparatus comprising: