JP2614618B2 - Signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device, and more particularly to a device that processes both an audio signal and a video signal.

[Prior Art] As a conventional video signal processing device, for example, CY (cyan), Mg (magenta), Ye (yellow), Bk (black)
It has four frame memories corresponding to each color by decomposing video signals of so-called four colors or three colors of R, G and B using a plate.

In recent years, on the other hand, an electronic still video (SV) device that stores one (one screen) of video information on one track of a magnetic sheet has appeared, and this magnetic sheet can store audio information in addition to video. . In such an electronic still video device, a video signal or an audio signal of a predetermined time length can be selectively recorded on one track.

[Problems to be Solved by the Invention] In order to reproduce a video signal and an audio signal as described above, it is necessary to consider a signal loss.

However, conventionally, when performing a reproduction process from a storage medium in which a video signal and an audio signal are mixedly stored, a process considering the above-described signal loss has not been sufficiently considered.

[Means for Solving the Problems] The present invention provides a determination unit that determines whether an input signal is a video signal or an audio signal, a storage unit that stores both the video signal and the audio signal, Detecting means for detecting a signal missing portion of the video signal and the audio signal; missing information storing means for storing information indicating the signal missing portion detected by the detecting means; and missing signal stored in the missing information storing means. When compensating for the signal loss of the signal stored in the storage means in accordance with the information indicating the portion, if the signal determined by the determination means is a video signal, the first signal is obtained by using the signals before and after the signal loss section. A compensating unit that performs a compensation process and performs a speech compensation process different from the first compensation process if the read signal is an audio signal.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of an information signal correction device in an SV transmitter having a signal processing device to which the present invention is applied.

An input terminal 1 receives an FM signal (video signal or audio signal) reproduced from a magnetic sheet 35 rotated by a spindle motor 39 by a head 37 (reproducing means). The input signal is guided to the envelope detector 2, and the envelope signal of the input signal detected here is input to the comparator 3. In the comparator 3, when the level of the input envelope signal falls below a predetermined dropout detection level, the output goes to a low level. An output signal from the comparator 3 is inverted by an inverter 22 to generate a signal E.
Becomes That is, when the comparator 3 detects a dropout, the signal E becomes high level. The dropout signal E is input to the data selector 21 and also to the dropout latch 10.

The dropout latch 10 is composed of a DF / F, and is 1H (horizontal scanning period) from the memory controller 15.
After the clear, the high-level signal F is input to the data selector 21 from the Q output terminal by the first drop-out signal E, and the Q output terminal is latched at the high level until it is cleared. I do.

Reference numeral 16 denotes a CPU which receives a signal from the sync separation circuit 11, determines a video signal or an audio signal from the output of the audio and video discrimination circuit 32, and outputs a signal from the SW 102 for selecting each mode (still video or audio). It operates based on the information or calculates Bk (black) data from the R, G, B data in the memory 8. 30 is a ROM storing a control program as shown in FIG. 4, 31 is a RAM having a work area for the program, and the CPU 16 executes the program. The audio / video determination circuit 32 determines whether the reproduced signal is an audio signal or a video signal based on the presence / absence of the synchronization signal separated by the synchronization separation circuit 11.

On the other hand, the FM signal input from the input terminal 1
The signal is demodulated into a demodulated signal C, and is input to the A / D converter 6 and the sync separation circuit 11. In the circuit 11,
When the input signal C is a video signal, a vertical synchronizing signal (V-SYNC) and a horizontal synchronizing signal (H-SYNC) are separated therefrom (when the input signal C is an audio signal, a synchronizing signal such as a video signal No synchronization signal is generated. Therefore, the CPU 16 can determine whether the signal input to the input terminal 1 is a video signal or an audio signal based on the signal from the sync separation circuit 11.

A timing generator 12 controls the timing of A / D conversion of the A / D converter 6 based on a clock from the oscillation circuit 13 and a synchronization signal from the synchronization separation circuit 11 or a signal from the CPU 16. . When the signal C input to the A / D converter 6 is a video signal, the A / D timing generation circuit 12 controls the synchronization from the synchronization separation circuit 11 based on the clock from the oscillation circuit 13 under the control of the CPU 16. A timing pulse B responding to the signal is input to the A / D converter 6. In the A / D converter 6, the demodulator 5 synchronizes with the fall of the timing pulse B.
A / D-converts the video signal from the A / D converter and outputs a digital signal D.

On the other hand, when the signal C input to the A / D converter 6 is an audio signal, the A / D timing generation circuit 12 outputs a timing pulse B which responds to a control signal from the CPU 16 to the A / D converter 6. To enter. The A / D converter 6 A / D converts the audio signal and outputs a digital signal D in synchronization with the falling of the pulse B. Digital signal D from A / D converter 6
Is input to the I / O controller 14.

Reference numeral 15 denotes a memory controller, which generates an address signal for reading and writing data from and to the memory 8 based on a clock from the oscillation circuit 13, performs switching with an address signal from the CPU 16, and clears every 1H. Or generate a signal. An address signal is applied from the memory controller 15 to the memory 8.

The memory 8 has areas for storing R (red), G (green), and B (blue) color information. If the signal D is a video signal (color 3 primary color signal), for example, the I / O controller 14
The R, G, and B regions are selected, and the video signal D is written into the R, G, and B regions of the memory 8 for each color information. Also,
If the signal D is an audio signal, for example, the I / O controller 14
Only the area is selected, and the audio signal D (audio information for one track of the magnetic sheet) is written to the R area of the memory 8.

On the other hand, simultaneously with the video or audio signal information being written into the memory 8, the latched dropout signal F and dropout signal E are written into the Bk version memory 20 via the data selector 21 controlled by the CPU 16.
At this time, the latched dropout signal F is added to the lower bit, for example, bit φ, of the data line of the Bk version memory 20, and the dropout signal E is applied to the upper bit, for example, bi.
In addition to t7, the other bits 1 to 6 are fixed at Low.

FIG. 2 shows the timings of the signals BG.

The video signal, audio signal and dropout signal in the memory 8 and the Bk version memory 20 are converted into analog signals by the D / A converter 18 and output from the output terminal 19. By monitoring the analog signal from the output terminal 19, a video signal, an audio signal, and a dropout signal can be confirmed. FIG. 3 shows a dropout on the monitor. From this figure, the dropout signal E added to the upper bits of the Bk version memory 20 appears to have high luminance as shown by L (shown thick in the figure), and it can be seen where the dropout occurs. Also, the latched dropout signal F
Is added to the lower bits of the Bk version memory 20.
As shown by M, the brightness is low (shown thinly in the figure) until the end of the memory (dropout latch after 1H ends)
Thin lines are visible (until 10 is cleared).

After the video signal or the audio signal and the dropout signal E are input to the memory 8 and the Bk version memory 20, the CPU 16 controls the I / O controller 14, the memory controller 15 and the data selector 21 to The Bk version memory 20 is connected to the CPU 16 and the dropout is corrected as follows. That is, according to the dropout information in the Bk version memory 20, if it is a video signal, the data before and after the dropout portion of the memory 8 is used to interpolate the dropout portion of the video signal. The data immediately before the dropout portion 8 replaces the dropout portion of the audio signal.

Next, the details of the correction process of the dropout of the information in the memory 8 by the CPU 16 will be described with reference to FIG.

In step S1, the address counter _XSX for counting the addresses of the Bk version memory 20 is set as the end address in the X direction of the memory, and the Y address counter _YSN is set as φ. Furthermore, initialized data register D _S, to initialize the YCN counter for counting the dropout buffer.

Next, in step S2, in the Bk version memory 20,
To find the Y coordinate with the dropout, the data of the address of the coordinate (X _SX , Y _SN ) is read from the memory 20 by the X coordinate of the address counter X _SX fixed at the end in the X direction.
Read the D _S. Next, in step S3, the value of the counter Y _SN (Y coordinate) is incremented by 1 to read the next data. Next, in step S4, it is checked whether the data read in step S2 is dropout data (other than φ) or not (φ). If not, in step S38, in step S38, the counter Y _SN (Y coordinate)
It is determined whether or not has been completed, and if not completed, the process returns to step S2, while if completed, the process proceeds to step S9.

In step S4, if it is other than the data D _S is phi, since a dropout in either the X direction at the Y-coordinate, in step S5, finds the start address of the drop-out buffer according to the value of YCN counter, the drop The value of the corresponding Y coordinate (Y
_SN ).

Next, in step S6, the value of the YCN counter is incremented by 1 to prepare for the next dropout buffer address. In step S7, whether the value of the YCN counter is equal to or less than the maximum number N1 in which dropout is allowed in the Y direction. Is checked, and if N1 or less, the process returns to step S2 to search for a line with a dropout and store the Y coordinate in a dropout buffer. In step S7, if the number of dropouts in the Y direction is N1 or more, the process proceeds to step S8, where it is determined whether or not the value of the counter YSN has _ended.If not, the process returns to step S2, and the process ends. If so, the process proceeds to step S9. In step S9, the Y coordinate _YSN of the line with the dropout previously stored in the dropout buffer is read. Next, in step S10, to find the X-direction of drop-out at the read Y coordinate Y _SN, and initializes the X coordinate address (the value of the address counter of memory 20) X _D, in step S11, the drop-out registers and Drop Initialize the out counter DCN.

Next, in step S12, the coordinates (X _D , Y
_SN ) and read the data _DOC into the dropout register. Next, in step S13, the address _XD is incremented by 1 to make the next X coordinate, and in step S14
, The content of the data D _OC read in step S12 is
Check if it is 81H. (Note that the dropout pulse is stored in the MSB of the dropout register, and the latched dropout pulse is stored in the LSB of the register.
It is. When there is no dropout, the data D _OC
Is (OOH), so when D _OC is not 81H, it is understood that it is not a dropout pulse.) Therefore, unless D _OC = 81H, the process proceeds to step S16, checks whether address X _D is completed in the X direction, if not completed, the next address
To investigate the dropout X _D, the flow returns to step S12. When the operation is completed in the X direction in step S16, step S24
Proceed to.

If a dropout is found in step S14 (D _OC
= 81H), in step S15, the address X _D as the start address X _DS of the dropout, the address Y _SN
Are sequentially stored as shown in FIG. Next, (because in step S13 the address X _D is incremented) in step S17, it reads the next address (X _D, Y _SN) the data dropout register D _OC, read the next data at step S18 Therefore, after incrementing the address X _D, in step S19, examines the contents of the read data D _OC at step S17, if it is 81H, since the drop-out is continuous, the address X _D is terminated at step S20 Check if you've gone, and if you're not done,
Since examines again next address data X _D, step S1
Return to 7. If the address X _D went up to the end in the step S20 advances to step S21.

If the data D _OC is not 81H in step S19, it means that the dropout pulse has disappeared.
The address X _D in S21, the end address X _DE of one dropout, the dropout is an area that contains the appropriate address Y _SN in the buffer, the start address of the drop-out stored earlier in step S15 X Store sequentially in the part following _DS .

Next, in step S22, since the dropout was found one in the sequence so far, is incremented by one dropout counter DCN, if no address X _D is completed in step S23, returns to step S12 again, the address if X _D is completed, the process proceeds to step S24, the number of dropouts found until now the (DCN) as shown in FIG. 5 in the storage portion of the number of dropouts of the address Y _SN of the dropout buffer To be stored.

Subsequently, in step S25, the address of the dropout buffer is incremented by 1 (YCN = YCN + 1) in order to search for a dropout in the X direction of the next line (Y coordinate).
Calculate the start address of the end of the dropout buffer,
In step S26, if the YCN counter has not ended (unless all the dropout buffers have been ended), the flow returns to step S9, and the sequence up to this point is repeated.
The operation of searching for the dropout in the direction and storing the address and the number in the dropout buffer is performed for all the lines having the dropout.

On the other hand, if the YCN counter has ended in step S26,
That is, if a dropout in the X direction is found for all lines with a dropout, the step
In S40, it is determined whether the signal being handled is audio or video from the output of the audio / video determination circuit 32.
Proceed to 7.

In step S27, after the YCN counter is initialized (YCN = 0), the process proceeds to step S28, where the YCN =
The number of dropouts (DCN) and the Y coordinate address _XSN with the dropout are read from the dropout buffer at 0, and based on this, in step S29,
Reads the start address X _DS in the X direction of drop-out at address Y _SN, in step S30, the X coordinate of the start address X _DS, before and after the Y-coordinate Y _SN-1 and Y
The data of _{SN + 1} is read out from the image memory 8 as A ₁ = (X _DS , Y _{SN -1} ) line data and A ₂ = (X _DS , Y _{SN + 1} ) line data, respectively. The data A ₁ and A ₂ before and after the read are added, the average value is obtained by halving the average value, and the average value is taken as the average value interpolation data A (X _DS , Y _SN ) of the dropout. Replace with data (X _DS , Y _SN ). This implements dropout average value interpolation.

Next, incremented by 1 in the X direction address X _DS in step S32 (for the next dropout interpolation), at step S33, if it has not been completed to the end of the dropout (X _DS <X _DE), following Then, the process returns to step S30 to perform interpolation of the dropout, and steps S30 to S32 are repeated until the interpolation of one dropout is completed.

Next, in step S34, the dropout counter DCN is set to 1
If the number of dropouts is not completed (DCN ≠ 0) in step S35, the process returns to step S29 to perform interpolation for the next dropout.
In step S35, the dropout counter DCN is set to 0
Then, in step S36, the counter YCN of the dropout buffer is incremented by one, and in step S37, the process has been completed for all the lines with dropout (YC
N) is checked, and if not completed, the process returns to step S28 again and repeats until dropout interpolation of all lines is completed. On the other hand, this sequence ends when all the processes are completed.

On the other hand, in step S40, if the signal being handled is audio, the process proceeds to step S41, where the YCN counter is initialized, and then proceeds to step S42. In step S42, reads the Y coordinate address X _SN with dropout number DCN and dropped out of the drop-out-buffer in YCN = 0, in step S43 based on this, the start address in the X direction of drop-out at address X _SN The _XDS and the end address _XDE are read, and in step S44, the R in the memory 8 containing the audio signal is read.
Regarding the area, the data that has not been dropped out at the X coordinate immediately before the dropout start address X _DS is A ₁ =
(X _DS-1 , Y _SN ), and in step S45, data A ₁ is dropped out data A = (X _DS ,
Y _SN ). As a result, the interpolation of the dropout portion of the audio signal is realized.

Next, the address X _DS in the X direction is incremented by 1 at step S46, in step S47, the If not completed until the end of the dropout (X _DS <X _DE), and the interpolation of the following drop-out as previously described Step S45
And S46 are repeated.

Next, in step S48, the dropout counter DCN is set to 1
The value is decremented, and it is determined in step S49 whether DCN = 0. If it is not 0, the process returns to step S43. If it is 0, that is, if all the dropouts have been completed, the counter Y of the dropout buffer is set at step S50.
The CN is incremented by one, and it is checked in step S51 whether all the lines with dropouts have been completed (YCN end). If not, the process returns to step S42 and repeats until all the dropout interpolations have been completed. . On the other hand, this sequence ends when all the operations are completed.

In the above embodiment, the dropout interpolation is performed by replacing the dropout data of the audio signal with the data immediately before the dropout. However, the dropout part can be removed. Interpolation with higher accuracy can be performed by averaging the surrounding data before and after and before and after the part.

In the above embodiment, the dropout pulse is input to the MSB of the memory, and the latched pulse of the dropout is input to the LSB of the memory. Not.

As described above, in the SV transmitter with the conventional function, the dropout position is left in the Bk version memory in one-to-one correspondence with the memory that stores the video signal or audio signal. , All dropout interpolation is possible, and no dedicated memory for dropout is required. Further, a wide variety of interpolation methods can be applied, and more accurate interpolation can be performed.

In this embodiment, a semiconductor memory is used as the memory.

Further, in this embodiment, since the audio data is written in the memory storing the specific color data, the memory storing the other color data can be used freely.

In addition, since the method of correcting the lack of a signal is determined so as to be appropriate for each of the audio signal and the video signal, an excellent correction can always be performed.

As described above, according to the present embodiment, it is possible to reliably correct the absence of information signals such as video signals and audio signals with a simple configuration.

[Effects of the Invention] As described above, according to the present invention, loss compensation can be performed for both input video signals and audio signals, and compensation according to each of the video signals and audio signals can be performed. Will be possible.

In addition, since the storage means for storing the video signal and the audio signal is shared, it is not necessary to provide a storage means for each, so that the configuration of the apparatus can be simplified and the storage capacity can be reduced.

In addition, since the configuration is such that the video signal, the audio signal, and the signal indicating the signal missing portion are all stored, synchronization at the time of performing the compensation processing can be easily obtained, and the compensation processing can be performed satisfactorily.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a waveform diagram of each part of the embodiment, FIG. 3 is a dropout on a Bk version memory having a dropout input, and its address relationship. FIG. 4 is a diagram for explaining the operation of dropout correction, and FIG. 5 is a diagram showing the storage state of a dropout buffer. DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2 ... Envelope detection circuit, 3 ... Comparator, 5 ... Demodulator, 6 ... A / D converter, 8 ... Memory, 10 ... Dropout pulse latch, 11 ... SYNC separator, 12 ...
A / D timing generation circuit, 13 oscillator, 14 I / O controller, 15 memory controller, 16 CPU, 18 D / A converter, 19 output terminal, 20 Bk version memory, 21 data selector , 22… Inverter, 102… Mode SW.

Claims (1)

(57) [Claims] 1. A determination means for determining whether an input signal is a video signal or an audio signal, a storage means for storing both the video signal and the audio signal, and a lack of the video signal and the audio signal Detecting means for detecting a portion; a missing information storing means for storing information indicating a signal missing portion detected by the detecting means; and a storing means for storing the information indicating the signal missing portion stored in the missing information storing means. When compensating for the signal loss of the stored signal, if the signal determined by the determination means is a video signal, a first compensation process is performed using signals before and after the signal loss portion, and the readout is performed. A compensating means for performing a compensation process for speech different from the first compensation process if the signal is a speech signal.