JP2594132B2 - Line switching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for time division multiplex digital transmission.

The present invention relates to a line switching system for switching an active line or transmission line for transmitting an information sequence in units of cells in a time division multiplex digital transmission to a protection line or transmission line. Line or transmission line switching includes switching and switching back of transmission lines in the event of a node or transmission line failure, transfer and switchback of transmission line failure for node addition or transmission line construction, load distribution of transmission lines, or new addition of lines. It is necessary when changing the accommodation of the line for the purpose.

[Conventional technology]

FIGS. 10 and 11 are block diagrams showing an example of a conventional digital transmission apparatus. FIG. 10 shows a first conventional example in which a transmission line is switched, and FIG. The case of switching is shown.

First, FIG. 10 will be described. 1 is a transmitting side device, 2 is a cross connect switch (XSW) for exchanging time slots, 3 is a multiplex conversion device (MUX), 4 and 14 are transmission line switching switches (LSW), and 5 and 15 are transmission line switching, respectively. Switch (LSW) 4 and 14 control circuit (CT),
6 is an interface circuit (IF) for electric-optical conversion, 7a,
7b and 7d are working transmission lines, 8 is a protection transmission line, 9 and
10 is a data link, 11 is a center device (CNT) that sends control signals to the control circuits (CT) 5 and 15, 12 is a receiving device, 13
Is an interface circuit (IF) for optical-to-electric conversion and bit synchronization, and 16 is a demultiplexer (D-MUX).

In the transmitting device 1, the multiplexing / conversion device (MUX) 3 multiplexes the digital information stream from the cross-connect switch (XSW) 2 and transmits the multiplexed data via the transmission line switch (LSW) 4 and the interface circuit (IF) 6. Working transmission line 7
a, 7b and 7d.

In the receiving side device 12, the signals of the working transmission lines 7a, 7b and 7d are received by the interface circuit (IF) 13 and demultiplexed (D-MUX) 16 via the transmission line switch (LSW) 14.
To supply. A demultiplexing device (D-MUX) 16 separates the multiplexed information sequence and outputs a cross-connect switch (XS).
W) Send to 2.

In the case of a failure of a line or a transmission device in the working transmission lines 7a, 7b, and 7d, a need to stop operation for maintenance, a case of switching back after repairing a failed part, and the like,
In accordance with an instruction from the center device (CNT) 11, the transmission line switching switches (LSW) 4 and 14 switch the working transmission line to the standby transmission line 8 via the data links 9 and 10 and the control circuits (CT) 5 and 15. . In the figure, the working transmission line 7d
To the backup transmission line 8.

Next, FIG. 11 will be described. Reference numeral 17 denotes a control circuit (CT) of the cross-connect switch (XSW) 2 of the transmitting apparatus 1;
And 19 are repeaters (REP), 20 and 21 are data links, 22 is a cross-connect switch (XS
W) The control circuit (CT) 2 and other circuits are the same as those in FIG.

In the transmitting device 1, the signal of the working transmission path 7 is received by the interface circuit (IF) 13, and the signal is demultiplexed by the demultiplexer (D-MU).
X) Supply to 16. The demultiplexer (D-MUX) 16 separates the multiplexed information sequence and sends it to the cross-connect switch (XSW) 2 as a highway signal multiplexed in a frame by a time slot. In the cross-connect switch (XSW) 2, the current transmission line 7 is fixedly output in one time slot or a plurality of time slots (corresponding to a line) in accordance with the time slot position in the frame.
Is connected to the multiplexing conversion device (MUX) 3 corresponding to. The connection destination of the line can be changed under the control of the control circuit (CT) 17. The multiplexing conversion device (MUX) 3 multiplexes the highway signal from the cross-connect switch (XSW) 2 and sends the multiplexed signal to the working transmission line 7 via an interface circuit (IF) 9.
To send to. Receiving device 12 and repeater (REP) 18
And 19 have the same configuration as the transmitting apparatus 1.

In the current transmission line, when it is necessary to stop operation for maintenance, when switching back after repairing a faulty part, when it is necessary to change the load of the transmission line or change the accommodation of the line for the addition of a new line, etc. Needs to switch the working line to the protection line. In the figure, the working transmission lines 7e-7f-7g
Switching from a working line passing through -7h to a protection line passing through working transmission lines 7e-7i-7j-7h is shown. In this case, the line switching is performed by first sending a control signal to the repeater (REP) 19 via the data link 20 according to the instruction of the center device (CNT) 11, and arranging the idle lines in the active transmission line 7i and the active transmission line 7j. Connecting. Next, a control signal is sent to the control circuits (CT) 17 and 22 via the data links 9 and 10 in accordance with an instruction from the center device (CNT) 11, and the cross-connect switch (XSW) 2 is transmitted by the control circuits (CT) 17 and 22. Is changed to and the connection is made to the empty line in the set working transmission lines 7i and 7j.

[Problems to be solved by the invention]

However, in the transmission line switching method described with reference to FIG. 10, the switching from the working transmission line 7d to the protection transmission line 8 is performed independently of the main signal. Therefore, at the time of switching, the transmission-side device 1
Even if it is transmitted in parallel to the working and protection transmission lines,
The delay difference between the working transmission line 7d and the protection transmission line 8 cannot be absorbed, and instantaneous interruption occurs at the time of switching, loss of synchronization due to loss or duplication of the main signal, etc., and a normal transmission state can be maintained. There was a disadvantage that disappeared. In particular, in a high-speed optical fiber communication device, there is a propagation time difference of more than the frame length or the cell length between the working transmission line and the protection transmission line, and frames or cells are dropped or duplicated when switching between the working and protection lines. there is a possibility. This results in an instantaneous interruption of the transmission path. For example, in the case of a backbone transmission line of several hundred Mb / s or more, even if there is a very short interruption during transmission line switching, all lower-level devices and terminals are greatly affected, and transmission quality is degraded. was there.

In the line switching method described with reference to FIG. 11, switching from the working line to the protection line is performed independently of the main signal. For this reason, even if the transmitting device 1 performs parallel transmission to the working line and the protection line at the time of switching, the delay difference between the working line and the protection line cannot be absorbed, and instantaneous interruption occurs at the time of switching. However, there is a disadvantage that the main signal is lost or duplicated. In this case, insertion and removal of the frame synchronization pattern are performed by the multiplexer / demultiplexer (MUX) 3 and the demultiplexer (DM).
UX) 16, there is no loss of synchronization on the transmission line due to line switching, but loss or duplication of the main signal causes loss of synchronization at the terminal, which has the disadvantage of deteriorating transmission quality.

The object of the present invention is to eliminate the disadvantages mentioned above,
It is an object of the present invention to provide a line switching system capable of eliminating a momentary interruption caused by switching and always maintaining a normal transmission state.

[Means for solving the problem]

The present invention provides a line switching system including a transmitting device and a receiving device including switching means for switching a working line or a transmission line for transmitting an information sequence in units of cells to a protection line or a transmission line, The transmitting-side device includes at least a switching signal insertion unit that inserts a switching signal indicating the end of an information sequence into a real cell immediately before switching in a working line or a transmission line, and the real cell in which the switching signal is inserted is First line switching control means for switching a working line or a transmission line to a protection line or a transmission line by the switching unit at the break of a cell after passing through the switching unit; and Switching signal detecting means for detecting the switching signal of the information sequence sent from the line or transmission line of the real cell, and a real cell of the information sequence sent from the protection line or transmission line to one After the real cell containing the switching signal is detected by the switching signal detecting means and the real cell containing the switching signal passes through the switching means, the actual line or transmission line is switched by the switching means at the cell division. A second line switching control means for switching to a protection line or transmission line, and thereafter controlling to read out the actual cells in the cell storage means and send the read out cells to the switching means.

[Action]

In the transmitting apparatus, the switching signal insertion means inserts a switching signal indicating the end of the information sequence into a real cell immediately before switching in a working line or transmission line. Then, after the actual cell into which the switching signal has been inserted has passed through the switching means by the first line switching control means, the switching means switches the working line or transmission line to the protection line or transmission line at the cell division. Switch to.

Then, in the receiving device, the switching signal detecting means detects the switching signal of the information sequence sent from the working line or transmission line. On the other hand, the real cells in the information sequence transmitted through the protection line or the transmission line are stored in the real cell storage means. Then, by the second line switching control means, the switching signal is detected by the switching signal detecting means, and after the real cell containing the detected switching signal passes through the switching means, the switching means The current line or transmission line is switched to the backup line or transmission line, and thereafter, the real cells stored in the real cell storage unit are read and transmitted to the switching unit.

Therefore, the switching of the line or the transmission line is performed at the boundaries of the cells that do not include the actual cells, and the actual cells are temporarily stored in the actual cell storage means, and the line or the transmission line is switched from the working to the standby. After the transmission of the real cell, the instantaneous interruption due to the switching of the line or the transmission path can be eliminated.

The real cell storage means may be configured such that, for example, the number of real cells stored in the real cell storage means becomes a certain value or less, and the real cell arrival interval in the transmitted information sequence passes through the cell storage means. When the information sequence in the route extends for a time longer than a predetermined delay time, it can be disconnected from the line.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, and shows a basic configuration of the present invention. FIG. 2 is an explanatory diagram showing a format of an information sequence (cell) on a transmission line.

In the first embodiment, changeover switches (CSW) 24 and 3 serving as switching means for switching a working line (transmission line) 26 for transmitting an information sequence in units of cells to a protection line (transmission line) 27 are provided.
In the line switching system including the transmitting device 1 and the receiving device 12 each including the communication device 9, the transmitting device 1 performs switching to indicate the end of information in a real cell immediately before switching in the working line (transmission line) 26. Switching signal insertion circuit (SIN) 23 as switching signal insertion means for inserting a signal
After the actual cell into which the switching signal has been inserted passes through the changeover switch (CSW) 24, the changeover switch (C
SW) 24 and a control signal 25 as first line switching control means for switching the working line (transmission line) 26 to the protection line (transmission line) 27. A switching signal detection circuit (SDT) 30 as switching signal detecting means for detecting the switching signal of the information sequence sent from 26, and a realization of the information sequence sent from the protection line (transmission line) 27. A buffer memory (BUF) 36 as a real cell storage means for temporarily storing cells, and the switching signal is detected by a switching signal detection circuit (SDT) 30. A real cell including this switching signal switches its switching switch (CSW) 39. After passing, the working line (transmission line) 26 is switched to the protection line (transmission line) 27 by the changeover switch (CSW) 39 at the break of the cell, and then the real cell in the buffer memory (BUF) 36 is read and the changeover switch (CSW) ) 39
It includes an actual cell separation circuit (RCS) 32, a selector (S) 34, and a control circuit (CT) 41 as second line switching control means for performing control for sending to the control circuit.

Further, the receiving side device 12 includes a real cell arrival interval detecting circuit (RC) for detecting the arrival interval of the real cells in the information sequence transmitted through the working line (transmission line) 26 and the protection line (transmission line) 27.
DT) 28.

It should be noted that two paths of the real cell arrival interval detection circuit (RCDT) 28 → the switching signal detection circuit (SDT) 30 → the real cell separation circuit (RCS) 32 are formed, and the real cells in these two paths are selected by the selector (S ) And one of them is transmitted to one input terminal of a changeover switch (CSW) 39 via a buffer memory (BUF) 36.

The feature of the present invention is that, in FIG. 1, in particular, the transmitting device 1 includes a switching signal insertion circuit (SIN) 23 and a control signal 25 as first line switching control means, and the switching signal is transmitted to the receiving device 12. A detection circuit 30, a buffer memory (BUF) 36 as real cell delay means, a real cell separation circuit (RCS) 32, a selector (S) 34 and a control circuit (CT) 41 as second line switching control means; Has been established.

 Next, the operation of the first embodiment will be described.

The switching signal insertion circuit (SIN) 23 of the transmitting side device 1 inserts a switching signal indicating the end of the information sequence into an empty bit position in the header of an arbitrary real cell in the working line (transmission line) 26 that has arrived. The switching signal insertion circuit (SIN) 23 sends out a control signal 25 immediately after the cell into which the switching signal is inserted has passed through the switching switch (CSW) 24. Switch to spare.

The real cell arrival interval detection circuit (RCDT) of the receiving side device 12 normally passes the arriving cell as it is. However, when the real cell arrival interval designation signal 29 is received from the control circuit (CT) 41, the arriving real cell arrives thereafter. When the cell interval is measured and the specified real cell arrival interval is detected, the control circuit (CT) 41
Then, the real cell arrival interval detection signal 29 is transmitted, and thereafter, the operation returns to the normal state.

The switching signal detection circuit (SDT) 30 constantly monitors the vacant bit position in the header of each arriving real cell, and when the switching signal indicating the end of the information sequence is detected at that position, the control circuit (CT) ) 41, the switching signal detection signal 31 is transmitted. The real cell separation circuit (RCS) 32 normally passes each cell that has arrived and sends it to the changeover switch (CSW) 39.
When a control signal 33 indicating real cell separation is received from the control circuit (CT) 41, real cells arriving thereafter are separated and sent to the selector (S). When the real cell separation circuit (RCS) 32 receives the control signal 33 indicating the real cell separation release from the control circuit (CT) 41, it returns to the normal state thereafter.

The selector (S) 34 connects one of the two inputs to the output by a control signal 35. The buffer memory (BUF) 36
When the read clock 37 has not arrived, the written real cell is stored, and when the read clock 37 has arrived, the real cell stored by the read clock 37 is read. When the number of actual cells in the buffer memory (BUF) 36 becomes equal to or less than a predetermined number, a switchable signal 38 indicating this is sent to the control circuit (CT) 41. Selector switch (CSW) 39
Sets and releases a path by the control signal 40.

Next, a procedure for switching from the working line (transmission line) 26 to the protection line (transmission line) 27 will be described.

First, in the receiving device 12, the control circuit (CT) 41
The transmission of the read clock 37 is stopped, the control signal 35 is transmitted, and the selector (S) 34 is switched to the real cell separation circuit (RC
S) 32 and the buffer memory (BUF) 36 are set to be connected, and a control signal 33 indicating real cell separation is sent to the spare real cell separation circuit (RCS) 32.

Next, in the transmitting device 1, the switching signal insertion circuit (SI
N) 23 inserts a switching signal indicating the end of the information sequence into an empty bit position in one header of any real cell that has arrived,
A control signal 25 is sent out, and in the changeover switch 24, immediately after the actual cell into which the switching signal has been inserted has passed, the cell is separated from the working line (transmission line) 26 to the protection line (transmission line).
Switch to 27.

Next, in the receiving device 12, the control circuit (CT) 41
After receiving the switching signal detection signal 31 from the working side switching signal detection circuit (SDT) 30, the control signal 40 is sent out, and the real cell into which the switching signal indicating the end of the information sequence is inserted is switched by the switching switch (CSW). Immediately after passing through 39, changeover switch (CSW) 39
, After switching from pass to pass at a cell break, transmission of the read clock 37 is started. After that, the control circuit (CT) 41 issues a switch enable signal 38 indicating from the buffer memory (BUF) 36 that the actual number of cells in the memory is equal to or less than a certain value.
After receiving the actual cell arrival time, the time longer than the delay time from the spare real cell separation circuit (RCS) 32 to the output terminal of the changeover switch (CSW) 39 via the buffer memory (BUF) 36 is used as the real cell arrival interval. An interval designation signal 29 is sent to a real cell arrival interval detection circuit (RCDT) 28 on the standby side. After that, the control circuit (CT) 41 detects the actual cell arrival interval detection circuit (RCDT) on the spare side.
Immediately after receiving the real cell arrival interval designating signal 29 from 28, a control signal 33 indicating real cell separation release is sent to the real cell separation circuit (RCS) 32 on the standby side, and a control signal 40 is sent out. At 39, switching from path to path completes the line or transmission path switching.

Switching back of a line or a transmission line can be performed in the same manner. However, in this case, the selector is set to the working side.

Since the first embodiment operates as described above,
In the switching of the line or the transmission line, no instantaneous interruption of the information sequence occurs.

In the above description of the switching principle, an example in which only the switching signal indicating the end of the information sequence is transmitted from the transmission side has been described.
A switching signal indicating the beginning of the information sequence may be inserted into the first real cell after switching from working to protection on the transmitting side and sent to the protection line or transmission line. This is done by detecting at the output of the cross-connect switch of the receiving device that a cell containing a switching signal indicating the beginning of an information sequence passes immediately after a cell including a switching signal indicating the end of the information sequence. , Can be used to confirm that the switching has been performed normally.

Further, the above principle can also be applied to route switching in a cross connect switch that performs switching on a cell basis.

Next, FIG. 2 will be described. In FIG. 2, VC
I ₀ , VCI ₁ and VCI ₃ are call identifiers (hereinafter referred to as VCI) assigned to each call indicating a destination, and VPI ₀ and VPI ₁ are route identifiers (VPI hereinafter) assigned to each line indicating a transmission route. ), H is a header, I is main information, E is an empty cell identification bit string for identifying an empty cell, and empty is a bit string that is not used, and the format of the information string is a real cell and an empty cell. Be composed. Different subscripts in the VCI or VPI indicate different calls or lines. Same
The flow of cells to which VPI has been assigned becomes a line.

The VPI assigns the same call to a plurality of calls transmitted to the same destination, so that the relay device handles a plurality of calls in a unified manner. The transmission speed of the line can be arbitrarily selected according to the number of calls to which the same VPI is assigned.

The same VCI is assigned to the main information of the same call from the outgoing call to the end of the call. Therefore, a flow of cells to which the same VCI is assigned can be regarded as one line. In addition, since the transmission line handles one line or a plurality of lines in a unified manner, it can be regarded as one line.

The line constituted by the VCI or VPI is not a physical line which always exists on the transmission line, but a logical line which exists only when a call is generated. Therefore, only when a cell arrives, the relay device transmits the cell to a target outgoing route according to the VCI or VPI in the header of each cell. For this reason,
Each relay device has a table in which an outgoing route number is written for each VCI or VPI.

The cell configuration to which the switching principle described above can be applied may be not only a fixed length but also a variable length cell.

Although the switching principle of the present invention has been described above, in order to make this practical, in order to separate the buffer memory 36 from the route of the backup line or transmission line, the information is continuously transmitted in the line or the transmission line information sequence. There must be an empty cell.
Table 1 and Table 2 show the time intervals at which continuous empty cells occur when the probability of occurrence of real cells including main information added to a transmission line or line follows the Poisson distribution.
It is shown in the table. Table 1 shows the average continuous empty cell generation interval when the average actual cell occupancy of the transmission line is 0.2, 0.5, and 0.8 when the transmission line speed is 150 Mb / s and the cell length is 500 bits. It is a thing. Table 2 shows average continuous empty cells when the average line utilization rate is 0.2, 0.5, and 0.8 with respect to the maximum line transmission rate for a fixed-length cell with a maximum transmission rate of 1.5 Mb / s and a cell code length of 500 bits. It shows the occurrence interval.

As described above, since a line is constituted by real cells only when a call is generated, empty cells are not included, but continuous empty cells shown in this table constitute a line to be switched from a transmission line. The figure shows continuous empty cells appearing on a highway when real cells are extracted and arranged on a highway operating at a clock speed corresponding to the maximum transmission speed of the line.

Tables 1 and 2 also show the number n of consecutive empty cells and the transmission delay time difference between the active spare transmission line or line that enables switching of the corresponding transmission line or line. In the case of line switching, the occupation time of the actual cells constituting the line on the transmission line differs depending on the transmission speed of the multiplexed transmission line, and therefore the switchable transmission delay time difference also differs.

Table 2 shows a case where a line is multiplexed onto a transmission line having a transmission speed of 6 Mb / s or 100 Mb / s when the maximum transmission speed of the line is equal to the transmission speed of the transmission line.

From these tables, it can be seen that the smaller the average actual cell occupation rate of the transmission line or the average utilization rate of the line and the smaller the transmission speed of the transmission line or the maximum transmission speed of the line, the wider the applicable range of the line switching system of the present invention. I can understand. Alternatively, in the case of line switching, it can be understood that the applicable range becomes wider as the transmission speed of the multiplexed transmission line with respect to the maximum transmission speed of the line to be switched becomes higher.

Next, an actual embodiment based on the switching principle described with reference to FIGS. 1 and 2 will be described.

FIG. 3 is a block diagram showing a second embodiment of the present invention, in which the above-described principle is applied to transmission line switching between nodes.

In FIG. 3, reference numeral 42 denotes a cross connect switch (XSW) for switching on a cell basis, reference numeral 44 denotes a switching signal insertion instruction signal or switching signal insertion completion signal, reference numeral 45 denotes a cell synchronization pattern insertion circuit (PI), and reference numeral 46 denotes an empty cell generation circuit. (CG), 47 is a transmission line switch (LSW), 48 is a transmission line switch (L
SW) 47 control signal, 49 is a control circuit (CT), 50 is an interface circuit (IF) such as electric-optical conversion, 51 is a data link transmission / reception circuit (DTR), 52 and 53 are data links, and 54 is a center device. (CNT), 55 is an interface circuit (IF) for optical-electric conversion, bit synchronization, etc., 56 is a reproduction clock, 57 is a cell synchronization circuit (SY), 58 is a cell phase pulse, 59 is an empty cell detection circuit (CD) , 60 are write clocks, 61 is a first-in first-out memory (hereinafter referred to as FIFO), 62
Is a selector (S), 63 is a control signal of the selector (S) 62,
64 is FIFO, 65 is read clock, 66 is empty signal,
67 is a transmission line switch (LSW), 68 is a control signal of the transmission line switch (LSW) 67, and 69 is a control circuit (C
T), and the other circuits are the same as those used in the above-mentioned figure.

The feature of the present invention is that in FIG.
Switching signal insertion circuit (SIN) 23 as switching signal insertion means
And a control circuit (CT) 49 that outputs a control signal 48 as first line switching control means. The receiving-side device 12 includes a switching signal detection circuit (SDT) 30 as switching signal detection means,
It comprises a FIFO 64 as real cell delay means, a real cell separation circuit (RCS) 32, a selector (S) 62 and a control circuit (CT) 69 as second line switching control means.

 Next, the operation of the second embodiment will be described.

In the configuration shown in FIG. 3, switching from any working transmission line to a protection transmission line, switching back, and if the working transmission line is not used, the transmission line is used as a protection transmission line and any other working transmission line is used. Switching from the path and switching back can be performed without instantaneous interruption. Here, switching and switching back from the working transmission path 7d to the protection transmission path 8 will be described.

The switching signal insertion circuit (SIN) 23 of the transmitting apparatus 1 normally passes the cell received from the cross-connect switch (XSW) 42 as it is, and inserts the cell synchronization pattern insertion circuit (P
I) is sent to 45, but when the switching signal insertion instruction signal 44 is received from the control circuit (CT) 49, a switching signal indicating the end of the information sequence is placed in an empty bit position in the header of the first real cell arriving thereafter. The actual cell is inserted and transmitted to a cell synchronization pattern insertion circuit (PI) 45, and a switching signal insertion completion signal 44 is transmitted to a control circuit (CT) 49. Thereafter, the state returns to the normal state.

The empty cell generating circuit (CG) 46 constantly outputs empty cells. The cell synchronization pattern insertion circuit (PI) 45 inserts a cell synchronization pattern into an empty cell in the arrived information sequence. If an empty cell does not arrive even after exceeding a certain number of cells, the arriving information sequence is delayed by one cell, and the cell in which the cell synchronization pattern is inserted is inserted into the information sequence. The delay is removed by removing empty cells from the information sequence when empty cells arrive.

In the transmission path changeover switch (LSW) 47, a path and a path are normally set, and at the time of transmission path switching, the path is switched at high speed at a cell division by a control signal. In the interface circuit (IF) 50, the input signal is
The light is converted and sent to the optical transmission line.

The control circuit (CT) 49 transmits the switching signal insertion instruction signal 44 and the control signal 48, receives the switching signal insertion completion signal 44, and transmits the data signal to the center device (DTR) 51 and the data link 52 via the data link 52. CNT) 54 and transmission / reception of transmission line switching information.

The interface circuit (IF) 55 of the receiving side device 12 performs optical-to-electric conversion on the received signal, synchronizes the bits, reproduces the reproduction clock 56, and outputs the optical-electrically converted information sequence. In the cell synchronization circuit (SY) 57, the recovered clock
A cell phase pulse 58 is output by synchronizing cells with the cell synchronization pattern 56 and the cell synchronization pattern in the received information sequence.

An empty cell detection circuit (CD) 59 detects an empty cell in the received information sequence by using the reproduced clock 56 and the cell phase pulse 58,
The write clock 60 is output so that only the real cells are written into the FIFO 61. Since the bit string for identifying the empty cell and the cell synchronization pattern are the same bit string, the empty cell detection circuit (CD) 59 determines that the cell including the cell synchronization pattern is an empty cell.

The real cells written in the FIFO 61 are read by a station clock (not shown). Since the write clock and the read clock can operate independently of each other in the FIFO 61, the clock and the cell phase of the information sequence received from each transmission path can be matched with the phase of the station clock source (not shown) by the FIFO 61.

The selector (S) 62 connects a target input terminal to an output terminal by a control signal 63. FIFO64 is the read clock
While the actual cell 65 is not arriving, the written real cell is stored. While the read clock 65 is arriving, the real cell stored by the clock is continuously read out and the transmission path switch ( LSW) to 67. Writing of real cells to the FIFO 64 is intermittent and reading is continuous, so that the number of real cells once accumulated gradually decreases. When there are no more real cells in the FIFO 64, an empty signal 66 indicating this is transmitted.

In the transmission path changeover switch (LSW) 67, a path is normally set, and at the time of transmission path switching, the path is switched at high speed at the break of cells by the control signal 68. Control circuit (CT)
Reference numeral 69 denotes a transmission of the real cell arrival interval designation signal 29, the control signals 33, 63 and 68 and the read clock 65, a reception of the switching signal detection signal 31, the real cell arrival interval detection signal 29 and the empty signal 66, and a data link transmission / reception. Transmission / reception of transmission line switching information with a center device (CNT) 54 via a circuit (DTR) 51 and a data link 53 is performed.

Next, a procedure for switching from the working transmission line 7d to the protection transmission line 8 will be described.

First, a transmission path switching signal is transmitted from the center device (CNT) 54 to the control circuit (CT) 69 of the receiving device 12. Upon receiving the transmission path switching signal, the control circuit (CT) 69 stops transmitting the read clock 65, transmits a control signal 63, and switches the selector (S) 62 to the real cell corresponding to the protection transmission path 8. After setting the separation circuit (RCS) 32 and the FIFO 64 to be connected, and sending the control signal 33 indicating the real cell separation to the real cell separation circuit (RCS) 32, the transmission path is sent to the center device (CNT) 54. A switch preparation completion signal is transmitted. After receiving the transmission path switching preparation completion signal, the center apparatus (CNT) 54 sends a transmission path switching signal to the control circuit (CT) 49 of the transmitting apparatus 1.

Upon receiving the transmission path switching signal, the control circuit (CT) 49 switches the switching signal insertion circuit (SIN) 2 corresponding to the working transmission path 7d.
In response to 3, a switch signal insertion instruction signal 44 is transmitted. Thereafter, the control circuit (CT) 49 receives the switching signal insertion completion signal 44 from the switching signal insertion circuit (SIN) 23 corresponding to the working transmission path 7d, and then the switching signal insertion circuit (SIN) 23 ends the information sequence. Immediately after the actual cell into which the switching signal indicating the above is inserted passes the transmission line switch (LSW) 47, the control signal 48 is sent out, and the cell is switched at high speed from path to path at the cell division. Thereafter, the control circuit (CT) 49 sends a transmission path switching completion signal to the center device (CNT) 54.

On the other hand, after receiving the switching signal detection signal 31 from the switching signal detection circuit (SDT) 30 corresponding to the working transmission line 7d, the control circuit (CT) 69 of the receiving side device 12 sends out the control signal 68, Immediately after the real cell into which the switching signal indicating the end of the signal has been inserted has passed through the transmission path switch (LSW) 67, the transmission path switch (LSW) 67 switches the path from path to path at a high speed at the cell division. Then, transmission of the read clock 65 is started.

Thereafter, the control circuit (CT) 69 receives the empty signal 66 from the FIFO 64, and then controls the real cell separation circuit (RC
S) From 32 through FIFO64, transmission path switch (LSW) 67
The actual cell arrival interval designating signal 29 is set as the actual cell arrival interval with the time longer than the delay time up to the output terminal of the protection transmission line 8.
To the actual cell arrival interval detection circuit (RCDT) 28 of FIG. After that, immediately after receiving the real cell arrival interval detection signal 29 from the real cell arrival interval detection circuit (RCDT) 28, the control circuit (CT) 69 sends the control signal 33 indicating the real cell separation release to the protection transmission line 8
To the real cell separation circuit (RCS) 32 and the control signal 68, and the transmission path switch (LSW) 67 switches from the path to the path.
A transmission path switching completion signal is sent to T) 54, and the transmission path switching is completed. The switching back of the transmission path can be performed in the same manner as the switching by changing the selection of the selector (S) 62.

Since the second embodiment operates as described above,
There is no instantaneous interruption of the information sequence due to transmission path switching and switching back.

FIG. 4 is a block diagram showing a third embodiment of the present invention, in which the above principle is applied to line switching between nodes.

In FIG. 4, 7, 7e to 7j are working transmission lines, and 69 is an optical transmission line.
Interface circuits (IF) for electrical conversion, bit synchronization, cell synchronization, etc., 70a, 70b and 70c are cell arrival interval detection circuits (CDT) of specified VPI, 71a, 71b and 71c are cell arrival interval specification signals or specification of specified VPI A VPI cell arrival interval detection signal 72a, 72b and 72c is a switching signal insertion detection circuit (SID) 73 for inserting or detecting a switching signal in a cell of a designated VPI.
a, 73b and 73c are switching signal insertion detection circuits (SI
D) Control signals for 72a, 72b and 72c, switching signal insertion completion signal or switching signal detection signal, and 74a, 74b and 74c are designated V
The PI cell separation circuits (CS), 75a, 75b and 75c are control signals for the cell separation circuits (CS) 74a, 74b and 74c, respectively.
6a, 76b and 76c are header decryption tagging circuits (HRG), 7
7a, 77b and 77c are memory read signals or memory output signals, 78 is a tag assignment circuit (TG), 79 is a tag rewrite signal, 80
a, 80b and 80c are tag map memories (TM) per VPI,
81a, 81b and 81c are the respective tag map memories (TM) 8
0a, 80b and 80c memory rewrite signals, 82a, 82b and 82
c is a tag removal circuit (TR), 83 is a cell synchronization pattern insertion,
Interface circuit (IF) for electric-optical conversion, etc., 84 is a control circuit (CT), 85 and 86 are repeaters (REP), and 8
7 and 88 are data links, and the other circuits are the same as those used in the above-mentioned figure.

The feature of the present invention is that, in FIG.
A switching signal insertion detection circuit (SI
D) It includes 72a, 72b and 72, and a control circuit 84 as first line switching control means, and the receiving side device 12 includes a switching signal insertion detection circuit (SID) 72a, 72b as switching signal detection means.
And 72, a FIFO 64 as an actual cell delay means, and a cell separation circuit (CS) 74a, 74b as a second line switching control means.
And 74c, selector (S) 62 and control circuit (CT) 84
And to include.

 Next, the operation of the third embodiment will be described.

In the interface circuit (IF) 69, after optical-to-electric conversion of the optical signal from the working transmission line, bit synchronization and cell synchronization are established, and only an actual cell from the received information sequence is written into the FIFO 61 by an empty cell detection circuit (not shown). The real cells written in the FIFO 61 are read out with a clock synchronized with the phase of a station clock source (not shown). By this FIFO 61, as in the case of FIG. 3, the clock of the information sequence received from each transmission line and the cell phase can be made to coincide with the phase of the station clock source.

The cell arrival interval detection circuits (CDTs) 70a, 70b and 70c of the designated VPI normally pass the arriving real cells as they are, but the control circuit (CT) 84 identifies the VPI for identifying the line to be switched, and its VPI. When receiving the cell arrival interval designation signals 71a, 71b and 71c of the designated VPI indicating the arrival time interval of the real cell having the following, the cell arrival interval of the designated VPI is measured thereafter, and during the designated time, The specified VPI
When no cell arrives, the control circuit (CT) 84
The cell arrival interval detection signals 71a, 71b and 71c of the designated VPI are transmitted, and after the transmission, the cell returns to the normal state.

Switching signal insertion detection circuit (SID) 72a, 7 for cell of specified VPI
Normally 2b and 72c pass the arriving real cells as they are, but control signals 73a, 73b and 73 indicating a switching signal insertion instruction to the cell of the designated VPI from the control circuit (CT) 84, respectively.
When c is received, a switching signal indicating the end of the actual cell sequence is inserted into an empty bit position in the header of the cell of the first designated VPI arriving thereafter, and the cell is inserted into the cell separation circuit (C
S) The switching signal insertion completion signals 73a, 73b and 73a are transmitted to the control circuit (CT) 84 while being transmitted to 74a, 74b and 74c.
73c is sent out and thereafter returns to the normal state.

Switching signal insertion detection circuits (SID) 72a, 72b and 7
2c are control signals 73a, 73b and 73c indicating a switching signal detection instruction of the cell of the designated VPI from the control circuit (CT) 84, respectively.
Is received, the bit at the empty bit position in the header of the cell of the designated VPI arriving thereafter is constantly monitored, and when the switching signal indicating the end of the information sequence is detected, the control circuit (CT)
The switching signal detection signals 73a, 73b and 73c are sent to 84.

The cell separation circuit (CS) 74a, 74b and 74c of the specified VPI
Normally, each arriving real cell is passed through as it is and sent to the header decryption tagging circuits (HRG) 76a, 76b and 76c, respectively, but the control circuit (CT) 84 controls the control signals 75a, When receiving the cells 75b and 75c, the received cell of the designated VPI is separated and transmitted to the selector (S) 62 thereafter. Then, the control circuit (CT) 84 controls the control signal 7 indicating the cell separation release of the designated VPI.
Upon receipt of 5a, 75b and 75c, thereafter returns to the normal state.

Tag map memory (TM) 80a, 80b and 80c per VPI
Are provided for each incoming transmission line, and each tag map memory (T
M) 80a, 80b, and 80c each include a VPI for identifying all lines included in each transmission path, and a tag bit string indicating an output path for each VPI. The memory rewrite signals 81a, 81b and 81c are used to identify the line to be switched.
This is a rewrite signal of a tag bit string corresponding to PI, or a VPI for identifying a line to be added to a corresponding transmission path and a write signal of the tag bit string. The tag map memory (TM)
Rewriting of 80a, 80b and 80c is performed when there is no access to the memory from the header decoding tag assignment circuits (HRG) 76a, 76b and 76c.

Header Decoding Tag Assignment Circuit (HRG) 76a, 76b and 76c
Respectively read the VPI in the header of the arriving real cell and read the VPI into the tag map memories (TM) 80a, 80b and 80c for each VPI of the corresponding transmission line, and read the memory read signal 77a,
77b and 77c, read the tag bit string corresponding to that VPI from the same memory, and read it
Take back as a, 77b and 77c, and insert the tag bit string into the empty bit position in the header of the real cell. The real cell into which the tag bit string has been inserted is sent to the cross-connect switch (XSW) 42. The tag assigning circuit (TG) 78 has a memory for one tag bit string, and in response to a tag rewrite signal 79, the tag bit string written in the memory and indicating the departure route of the line to be switched is received. After the insertion into the empty bit position in the header of the cell, the real cell is transmitted to the cross-connect switch (XSW) 42.

The cross-connect switch (XSW) 42 transfers each real cell to the outgoing route indicated by the tag bit string according to the tag bit string inserted in the empty bit position in the header of each arrived real cell. In the cross connect switch (XSW) 42,
For real cells input from the same transmission path and transferred to the same output path, the order of the real cells does not reverse. The tag removal circuits (TR) 82a, 82b and 82c remove the tag bit sequence inserted into the empty bit position of the header of each real cell of the arriving information sequence, and empty the information sequence when no real cell arrives. The cell is inserted, and the information sequence is sent to the interface circuit (IF) 83. The interface circuit (IF) 83 inserts a cell synchronization pattern into an empty cell in the transmitted information sequence, performs electro-optical conversion on the received information sequence, and sends it out to the working transmission line.

The control circuit (CT) 84 includes cell arrival interval designating signals 71a, 71b and 71c of the designated VPI, control signals 73a, 73b and 73c, control signals 75a, 75b and 75c, control signal 63, and read clock 6
5, Tag rewrite signal 79, and memory rewrite signals 81a, 81b
And 81c, and the cell arrival interval detection signal 71 of the specified VPI
a, 71b and 71c, a switching signal insertion completion signal or a switching signal detection signal 73a, 73b and 73c, and reception of an empty signal 66, and the data transmission and reception circuit (DTR) 51 via the data link 52 and 53, the center device (CNT) 54
And transmission / reception of line switching information to / from the terminal.

The transmitting device 1, the receiving device 12, and the relay devices 85 and 86 all have the same configuration. However, VP in each device
The contents of the tag map memories (TM) 80a, 80b and 80c for each I correspond to the lines passing through the device.

Next, in FIG. 4, a switching procedure in the case of switching the line from the working line passing through the working transmission lines 7e-7f-7g-7h to the protection line passing through the working transmission lines 7e-7i-7j-7h will be described below. .

First, a line switching signal is sent from the center device (CNT) 54 to the control circuit (CT) 84 of the receiving device 12 via the data link 53 and the data link transmitting / receiving circuit (DTR) 51. Upon receiving the line switching signal, the control circuit (CT) 84 first sends out a tag rewrite signal 79 to store the cell in the memory in the tag provision circuit (TG) 78 in the cross-connect switch (XSW) 42. A tag having a bit string to be transferred like a path is written in the tag removal circuit (TR) 82a, and then a control signal 63 is transmitted to specify the selector (S) 62
A control signal 7 indicating the cell separation of the VPI for identifying the working line to be switched while the transmission of the read clock 65 is stopped while setting the cell separation circuit (CS) 74c to be connected to the FIFO 64.
After transmitting the control signal 73a indicating the switching signal detection instruction of the VPI cell for identifying the working line to be switched to the cell switching signal insertion detection circuit (SID) 72a of the designated VPI, the center device (CNT) 54 is transmitted. To send a line switching preparation completion signal.

After receiving the line switching preparation completion signal, the center device (CNT) 54 transmits the signal via the data link 88 to the relay device (REP) 8.
Send a line switching signal to 6. In the repeater (REP) 86,
When the line switching signal is received, the VPI for identifying the working line to be switched and the cross connect switch (XS) are stored in the tag map memory (TM) for each VPI corresponding to the working transmission line 7i.
W) Write a tag having a bit string in which cells are transferred to the working transmission path 7j in 42 in association with the VPI.

Next, the center device (CNT) 54 transmits a line switching signal to the control circuit (CT) 84 of the transmission side device 1 via the data link 52 and the data link transmission / reception circuit 51. Upon receiving the line switching signal, the control circuit (CT) 84 sends out a control signal 73a indicating a switching signal insertion instruction indicating the end of the information sequence to a VPI cell for identifying a working line to be switched. Then, after receiving the switching signal insertion completion signal 73a, the control circuit (CT) 84 sends out the memory rewriting signal 81a immediately after the cell into which the switching signal has been inserted passes the header decoding tag attaching circuit (HRG) 76a. , Tag map memory (TM) for each VPI
The tag corresponding to the VPI that identifies the working line to be switched in 80a is replaced with a tag having a bit string whose cells are transferred to the tag removal circuit (TR) 82c in the cross-connect switch (XSW) 42, that is, as a path. rewrite. Thereafter, in the control circuit (CT) 84, the center device (CNT) 54 sends out a line switching completion signal.

On the other hand, after receiving the switching signal detection signal 73a, the control circuit (CT) 84 of the receiving device 12 sends out the read clock 65 immediately after the cell in which the switching signal is inserted passes the cross connect switch (XSW) 42. Start. Thereafter, the control circuit (C
After receiving the empty signal 66, the T) 84 receives the tag removal circuit (T) from the cell separation circuit (CS) 74c of the designated VPI via the FIFO 64.
R) The cell arrival interval designating signal 71c of the designated VPI is transmitted using the delay time to the input terminal of the switch 82a as the cell arrival interval of the VPI for identifying the working line to be switched.

After that, immediately after receiving the cell arrival interval detection signal 71c of the designated VPI, the control circuit (CT) 84 sends out a control signal 75c indicating the release of the VPI cell separation for identifying the working line to be switched and the memory. A rewrite signal 81c is transmitted, and the VPI for identifying the working line to be switched and the cell corresponding to the VPI are stored in the tag map memory (TM) 80c for each VPI, and the cell is tabbed in the cross-connect switch (XSW) 42. Removal circuit (TR) 8
A tag having a bit string to be transferred like a path is written to 2a. The setting of the path, that is, the rewriting of the tag map memory (TM) 80c for each VPI may be performed in advance. Thereafter, the control circuit (CT) 84 operates the center device (CN).
A line switching completion signal is sent to T) 54, and the line switching is completed. Switching back the line can be performed in the same manner as the line switching.

In the third embodiment, since the operation is performed as described above, an instantaneous interruption of the information sequence due to switching and switching back of the line does not occur.

For example, when it is desired to stop the operation of the working transmission line 7f, all the lines passing through the working transmission line 7f may be switched to the lines passing through other transmission lines in the same manner as described above.

FIG. 4 shows the line switching identified by the VPI. However, in each device, instead of the tag map memories (TM) 80a, 80b and 80c for each VCI, a tag map memory for each VPI and a cell for the designated VPI are used. Arrival interval detection circuit (C
DT) Cell arrival interval detection circuit of specified VCI in place of 70a, 70b and 70c, cell separation circuit (CS) of specified VPI instead of cell separation circuit (CS) 74a, 74b and 74c, cell switching signal of specified VPI Insertion detection circuit (SID) 72a, 72b and 72c
Instead of inserting a switching signal into the cell of the specified VCI or specifying the V
It has a switching signal insertion detection circuit for detecting a switching signal of a CI cell, and the header decoding tag attaching circuits (HRG) 76a, 76b and 76c read the VCI in the header of the arriving real cell and correspond to the VCI. By adding a tag bit string, line switching for each call identified by VCI is also possible.

FIG. 5 is a block diagram showing a fourth embodiment of the present invention.
The case where the above principle is applied is shown, and the case of line switching from a normal state is shown.

In FIG. 5, 89R and 89L are line separation circuits (L
S), 90R and 90L are line insertion circuits (LI), 91a and 91
b is a cell multiplexing circuit (PM), 92 is a decoding conversion separation / insertion circuit (RCSI) that performs header decoding, header conversion, line separation, and inserts a switching signal into a cell of a specified VPI, and 93 is an R / L for each VPI
Route identification bitmap memory (LDM), 94 is a memory read signal, 95 is a memory output signal, 96 is a switch signal insertion instruction signal, 97 is a switch signal insertion completion signal, 98 is a memory rewrite signal,
99 is a control circuit (CT), 100 is a header conversion circuit (HC), 101
Is a cell multiplexing highway on the transmitting side, 102 is a cell multiplexing highway on the receiving side, 103 is a cell separation circuit (CS) of a designated route identification bit of a designated VPI, 104 is a cell separation instruction signal or a cell separation cancellation instruction signal, 105 Is a switching signal detection circuit (SDT) of the cell of the designated VPI, 106 is a switching signal detection instruction signal or a switching signal detection signal, 107 is a control circuit (CT), 108 is a data ring transmission / reception circuit (DTR), 109 and 110 are data Link, 111 is a center device (CNT), 112 is a clockwise working ring transmission line, 113 is a counterclockwise working ring transmission line, 114 is a working line, and 115 is a protection line. It is the same as that used in the above-mentioned figure.

The transmitting device 1 and the receiving device 12 have the same configuration, and are referred to as ADD-DROPMUX. In the configuration of FIG. 5, one AD
Although only D-DROPMUX is shown, a large number of ADD-DROPMUXs are usually connected to the ring transmission line, and each ADD-DROPMUX is connected to a center (CNT) device 111 via a data link. Further, in FIG. 5, the interface circuit of the ring transmission line and the circuits necessary for cell synchronization are omitted, but the same circuits as those shown in FIGS. 3 and 4 are used. The above-described points are the same in FIG. 6 showing the line switching in the ring transmission path described later.

The feature of the present invention is that in FIG.
Decoding conversion separation insertion circuit (RCS
I) 92 and a control circuit (C
T) 99, the receiving apparatus 12 includes a switching signal detection circuit (SDT) 105 as switching signal detection means, a FIFO 64 as actual cell delay means, and a cell separation circuit as second line switching control means. (CS) 103 and a control circuit (CT) 107.

Next, the operation of the fourth embodiment will be described. The line separation circuits (LS) 89R and 89L are connected to the ring transmission lines 112 and 1
13) Read the VPI in the header of each cell of the information sequence sent on the upper side, and if the VPI identifies the line to be received by the ADD-DROPMUX of the own station, which ring transmission path Even cells sent from 112 or 113,
The cell is separated and sent to a cell multiplexing circuit (PM) 91a. Further, a reception information sequence in which empty cells are inserted at cell positions separated by the cell multiplexing circuit (PM) 91a is transmitted to the line insertion circuit (LI) 90R or 90L. The line insertion circuit 90R or 90L inserts an actual cell sent from the decoding conversion separation / insertion circuit (RCSI) 92 into a vacant cell position in the received information sequence and sends it out to the ring transmission line. If there is no empty cell in the received information sequence, the real cell transmitted from the decoding conversion separation / insertion circuit (RCSI) 92 is delayed until an empty cell arrives.

Cell multiplexing circuits (PM) 91a and 91b multiplex real cells received from two inputs for each cell and output the multiplexed cells. Each real cell on the cell multiplexing highway 102 on the receiving side is transmitted to a subscriber transmission path connected to a terminal corresponding to each VCI according to the VCI in the header of each cell. To the cell multiplexing highway 101 on the transmitting side, an information sequence in which actual cells transmitted from a plurality of subscriber transmission paths are multiplexed for each cell is transmitted. Only the VCI for identifying the call is inserted in the header in the real cell sent from the subscriber transmission line. Header conversion circuit (HC) 1
At 00, the VCI in the header of each arriving real cell is read, and the VCI for identifying the line containing the call indicated by the VCI is read.
The PI is inserted at the VPI position in the header of the cell, and sent to the decoding separation conversion insertion circuit (RCSI) 92.

R / L route identification bitmap memory (LDM) for each VPI 9
3 indicates that all the lines transmitted from the ADD-DROPMUX of the own station are transmitted to the right-hand ring transmission line 112 or left-hand ring transmission corresponding to the VPI for identifying each line. It has a route identification bit R / L indicating whether or not to transmit to the path 113. R indicates clockwise and L indicates counterclockwise.
The route identification bit R / L is used for the decryption separation conversion insertion circuit (RCS
I) When there is no access from 92, the memory is rewritten from R to L or from L to R by the memory rewrite signal 98. The decoding conversion separation / insertion circuit (RCSI) 92 normally reads the VPI in the header of each arriving real cell, and uses the VPI as a memory read signal 94 to read the R / L route identification bitmap memory (LD
M) 93, route identification bit R / L corresponding to the VPI
As a memory output signal 95, and inserts the route identification bit R / L into an empty bit position in the header of the real cell, and inserts the real cell into a line insertion circuit (LI) 90R when the root identification bit is R. , L, it is sent to the line insertion circuit (LI) 90L. In addition, decoding conversion separation insertion circuit (R
When the control circuit (CT) 92 receives from the control circuit (CT) 99 a switching signal insertion instruction signal 96 indicating a switching signal insertion instruction indicating the end of the information sequence in a VPI cell for identifying a line to be switched, the signal subsequently arrives. After inserting the switching signal into the first cell of the specified VPI, the switching signal insertion completion signal 97 is sent to the control circuit (CT).
Send to 99.

Cell separation circuit for specified route identification bit of specified VPI (C
The S) 103 normally passes the arriving cell as it is and sends it out to the cell multiplexing circuit (PM) 91b. When the cell separation instruction signal 104 is received, the V) 103 identifies the protection line to be switched.
Separate cells of PI and a predetermined route identification bit into FIFO
Send to 64. Upon receiving the cell separation release instruction signal 104, the cell separation circuit (CS) 103 returns to the normal state. The switching signal detection circuit (SDT) 105 of the cell of the designated VPI
Normally, nothing is performed simply by passing the arriving cell as it is, but when the switching signal detection instruction signal 106 is received, the vacant bit position in the header of the VPI cell identifying the switching target circuit arriving thereafter is determined. It constantly monitors and detects a switching signal indicating the end of the information sequence, and then detects a switching signal detection signal.
Send out 106.

Next, a line switching procedure from the working line 114 to the protection line 115 will be described.

First, a line switching signal is sent from the center device (CNT) 111 to the control circuit (CT) 107 of the receiving device 12 via the data link 110 and the data link transmitting / receiving circuit (DTR) 108. Upon receiving the line switching signal, the control circuit (CT) 107 stops transmitting the read clock 65, and indicates a cell having a VPI for identifying the protection line 115 to be switched and a cell having the route identification bit L. After transmitting the separation instruction signal 104 and further transmitting the switching signal detection instruction signal 106 indicating the detection of the switching signal indicating the end of the information sequence of the VPI cell for identifying the working line 114 to be switched, the center device (CNT) A line switching preparation completion signal is sent to 111.

After receiving the line switching preparation completion signal, the center device (CNT) 111 transmits the control circuit (C) of the transmission side device 1 via the data link 109 and the data link transmission / reception circuit (DTR) 108.
T) Send a line switching signal to 99. The control circuit (CT) 9
9 receives the line switching signal and sends a switching signal insertion instruction signal 96 indicating the end of the information sequence to the VPI cell for identifying the working circuit 114 to be switched. After that, immediately after receiving the switching signal insertion completion signal 97, the control circuit (CT) 99 sends out a memory rewriting signal 98 to switch the switching target in the R / L route identification bitmap memory (LDM) 93 for each VPI. Working line 114
After rewriting the route identification bit corresponding to the VPI identifying R to L or L, a line switching completion signal is sent to the center device (CNT) 111.

On the other hand, after receiving the switching signal detection signal 106, the control circuit (CT) 107 of the receiving side device 12 reads the read clock 6 immediately after the cell into which the switching signal is inserted passes the cell multiplexing circuit (PM) 91b.
Start sending 5. Thereafter, the control circuit (CT) 107
Indicates the delay time from the cell separation circuit (CS) 103 of the designated route identification bit of the designated VPI to the output terminal of the cell multiplexing circuit (PM) 91b via the FIFO 64 after the reception of the empty signal 66. As the cell arrival interval of the VPI for identifying the line, the cell arrival interval designation signal 71a of the designated VPI is transmitted. Then, immediately after receiving the cell arrival interval detection signal 71a of the designated VPI, the control circuit (CT) 107 sends a cell separation release instruction signal 104, and then sends a line switching completion signal to the center device (CNT) 111. The line switching is completed.

Since the fourth embodiment operates as described above,
There is no instantaneous interruption of the information sequence due to line switching. By performing the line switchback in the same manner as the line switching, the switchback can be performed without an instantaneous interruption.

At the point in FIG. 5, if it is desired to stop the operation of one or both of the ring transmission lines, the transmission side of each of the lines of one or both of the ring transmission lines whose operation through the point is to be stopped is stopped. ADD-DROPMUX and receiver
In ADD-DROPMUX, by performing line switching in the same manner as described above, each line can be switched without an instantaneous interruption. In this respect, the switching back of each line after the ring transmission line whose operation has been stopped is returned to the normal state can be performed without an instantaneous interruption in the same manner as described above.

FIG. 6 is a block diagram showing a fifth embodiment of the present invention. The fifth embodiment is similar to the fourth embodiment of FIG.
The case where the above principle is applied to the line switching in the subscriber system double ring transmission line is shown, and the line switching from the loopback state of the ring transmission line is shown.

6, reference numerals 116 and 117 denote loop-back routes, 118 denotes a working line, 119 denotes a protection line, and other circuits are the same as those in FIG. Therefore, the features of the present invention are the same as those in FIG.

FIG. 6 shows a state in which the loopback transmission line switching is performed in the ADD-DROPMUX at both ends due to the disconnection of both ring transmission lines. In this case, the working line shown in FIG. 114 is a working line 118 shown in FIG.
Automatically switches to. The work line 118 and the protection line 119 are identified by a route identification bit R / L inserted at an empty bit position in the cell header. Working line 1
Switching from 18 to the protection line 119 is the same as that in FIG. 5 except that the route through which the line passes is changed. Therefore, there is no instantaneous interruption of the information sequence due to line switching.

FIG. 6 shows an example in which the loopback position is within the ADD-DROPMUX on the transmission side of the line. Can be used for line switching. For all the lines passing through the loopback routes 116 and 117, line switching is performed in the same manner as described above, and after expelling all the lines passing through the loopback routes 116 and 117, both ring transmission lines at the point are restored, and the loop is restored. Back route 116
After switching back to the original state only for the transmission path and 117,
The ring transmission is performed for all the lines evicted from the loopback routes 116 and 117 by switching back the lines in the same manner as the line switching back from the protection line 115 to the working line 114 shown in FIG. The transmission path can be switched back from the loopback state of the path without instantaneous interruption.

FIGS. 5 and 6 show the case where the line identified by the VPI is switched. In FIGS. 5 and 6, the cell arrival interval detection circuit (SDT) 70a of the designated VPI is designated by the designated VPI.
A cell switching signal detection circuit (SDT) 105 for a cell with a specified VPI is used as a cell arrival interval detection circuit for a CI, and a cell separation circuit (CS) 103 for a specified route identification bit of a specified VPI is used as a cell switching signal detection circuit for a specified VCI. The R / L route identification bitmap memory (LDM) 93 for each VPI is stored in the cell separation circuit for the specified root identification bit of the specified VCI, and the R / L route identification bitmap memory for each VCI is converted to the decoding conversion separation / insertion circuit (RCSI). Decrypt header 92,
Change to a header separation, line separation, and decoding / separation / conversion insertion circuit that inserts a switching signal into the cell of the designated VCI, and perform cell processing in each circuit in the VCI in the header of each cell.
, Line switching for each call identified by the VCI is also possible.

FIG. 7 is a block diagram showing a sixth embodiment of the present invention, in which the above principle is applied to line switching in a subscriber ring transmission line. Note that the fourth and fifth embodiments insert the root identification bit R / L at an empty bit position in the header of the cell, whereas the sixth embodiment includes:
This method does not insert the route identification bit R / L.

In FIG. 7, reference numeral 91c denotes a cell multiplexing circuit (PM); 120, a control circuit (CT); 121, a decoding / separation / insertion circuit (RSI) for performing header decoding, line separation, and insertion of a switching signal into a cell of a designated VPI; Reference numeral 122 denotes a working line and reference numeral 123 denotes a protection line, and other circuits are the same as those used in the above-described drawing.

The feature of the present invention is that in FIG.
Decoding separation insertion circuit (RSI) 121 as switching signal insertion means
And a control circuit (CT) 99 as first line switching control means.
The receiving-side apparatus 12 includes a switching signal detection circuit (SDT) 105 as switching signal detection means, a FIFO 64 as actual cell delay means, and a cell separation circuit (CS) 74a as second switching control means. And a control circuit (CT) 120.

 Next, the operation of the sixth embodiment will be described.

The decryption / separation / insertion circuit (RSI) 121 shown in FIGS. 5 and 6 except that the root identification bit R / L is not inserted into an empty bit position in the header of an arriving cell. ) Perform the same operation as 92. The cell multiplexing circuit (PM) 91c corresponds to the cell multiplexing circuit (P) shown in FIGS.
M) Similar to 91a and 91b, the input real cells are multiplexed for each cell and output.

Next, a line switching procedure from the working line 122 to the protection line 123 will be described.

First, a line switching signal is sent from the center device (CNT) 111 to the control circuit (CT) 120 of the receiving device 12 via the data link 110 and the data link transmission / reception circuit (DTR). Upon receiving the line switching signal, the control circuit (CT) 120 stops sending the read clock 65, sends out a control signal 63, and outputs a cell separation circuit (designated VPI corresponding to the left-handed ring transmission line). CS) 74a is set to connect the FIFO 64 with the selector (S) 62, and then a control signal 75a indicating the separation of the cell having the VPI for identifying the protection line 123 to be switched is transmitted. A switching signal detection instruction signal 106 indicating the detection of a switching signal indicating the end of the information sequence of the VPI cell identifying the target working line 122, and a switching signal detection circuit for a cell of the designated VPI corresponding to the clockwise ring transmission line. After transmitting to the (SDT) 105, a line switching preparation completion signal is transmitted to the center device (CNT) 111.

After receiving the switching preparation completion signal, the center device (CNT) 111 transmits the control circuit (CT) 99 of the transmission side device 1 via the data link 109 and the data link transmission / reception circuit (DTR) 108.
To send a line switching signal. Upon receiving the line switching signal, the control circuit (CT) 99 sends a switching signal insertion instruction signal 96 indicating insertion of a switching signal indicating the end of the information sequence to a VPI cell for identifying a working line to be switched. Then, immediately after receiving the switching signal insertion completion signal 97, the control circuit (CT) 99 sends out the memory rewriting signal 98, and the switching target in the R / L route identification bitmap memory (LDM) 93 for each VPI is output. After rewriting the route identification bit corresponding to the VPI for identifying the working line 122 to R or L, a line switching completion signal is sent to the center device (CNT) 111.

On the other hand, the control circuit (CT) 120 of the reception-side device 12 transmits the switching signal detection signal 106 to the designated V corresponding to the clockwise ring transmission path.
After receiving from the switching signal detection circuit (SDT) 105 of the PI cell, the transmission of the read clock 65 is started immediately after the cell into which the switching signal is inserted passes the cell multiplexing circuit (PM) 91c. Thereafter, after receiving the empty signal 66, the control circuit (CT) 120 transmits the signal from the cell separation circuit (CS) 74a of the designated VPI corresponding to the counterclockwise ring transmission line to the cell multiplexing circuit (PM) 91c via the FIFO 64. Specify the delay time to the output terminal as the VPI cell arrival interval that identifies the protection line 123 to be switched
The cell arrival interval detection circuit (CDT) 70a of the designated VPI corresponding to the ring transmission line of the counterclockwise direction corresponding to the cell arrival interval designation signal 71a of the VPI
To send to. Thereafter, the control circuit (CT) 120
The cell arrival interval detection circuit (CDT) 70a of the designated VPI corresponding to the ring transmission line going counterclockwise with the PI cell arrival interval detection signal 71a
Immediately after receiving the control signal, a control signal 75a indicating the release of cell separation is sent to the cell separation circuit (CS) 74a of the designated VPI corresponding to the left-handed ring transmission line, and then a line switching completion signal is sent to the center device (CNT) 111. And the line switching is completed.

Since the sixth embodiment operates as described above,
There is no instantaneous interruption of the information sequence due to line switching. Switching back the line is also performed in the same manner as the line switching,
Switchback is possible without interruption.

At the point in FIG. 7, if it is desired to stop the operation of one or both of the ring transmission lines, the transmission side of each line is stopped for one or both of the ring transmission lines whose operation through the point is stopped. ADD-DROPMUX and receiver
In ADD-DROPMUX, by performing line switching in the same manner as described above, each line can be switched without an instantaneous interruption. Further, at the point a, the switching back of each line after the ring transmission line whose operation has been stopped is returned to the normal state can also be performed without an instantaneous interruption in the same manner as described above.

FIG. 7 shows a case where the line identified by the VPI is switched. In FIG. 7, the cell arrival interval detection circuit (CDT) 70a of the designated VPI is designated as the cell arrival interval detection circuit of the designated VCI. VPI cell switching signal detection circuit (SDT) 105 to designated VCI cell switching signal detection circuit, designated VPI cell separation circuit (CS) 74a to designated VCI cell separation circuit, R / L route for each VPI The identification bitmap memory (LDM) 93 decodes the header into the R / L route identification bitmap memory for each VCI, and decodes the header into a decoding / separation / insertion circuit (RSI) 121 that performs header decoding, line separation, and insertion of a switching signal into the cell of the designated VPI. By changing to a decoding separation / insertion circuit that inserts a switching signal into the cell of the line separation and the designated VCI, respectively, and performs cell processing in each circuit according to the VCI in the header of each cell, V
Line switching for each call identified by CI is also possible.

FIG. 8 is a block diagram showing a seventh embodiment of the present invention, in which the above-described principle is applied to line switching in a subscriber ring transmission line, and loopback switching and switchback are instantaneously interrupted for each line. It is made to do in.

In FIG. 8, 132 is a control circuit (CT) and 124 is a designated VP
A switching signal insertion circuit (SI
N), 125 is a control signal of the switching signal insertion circuit or a switching signal insertion completion signal, 127 is an operation start signal or an operation stop signal, 126 is a header decoding line separation circuit (HRS), 128 is an R / L route identification for each VPI Bitmap memory (LDM), 129 is a memory read signal, 130 is a memory output signal, 131 is a memory rewrite signal, 133 and 134 are line loopback circuits, 135
Is a working line, 136 is a protection line, and 137 is a header decryption line separation circuit (HRS), and the others are the same as those used in the above-mentioned figure.

The feature of the present invention is that, in FIG.
Switching signal insertion circuit (SIN) 124 as switching signal insertion means
And a control circuit (CT) 13 as first line switching control means
2, the receiving-side device 12 includes a switching signal detection circuit (SDT) 105 as switching signal detection means, a FIFO 64 as real cell delay means, and a cell separation circuit (CS) as second line switching control means. 74a and a control circuit (CT) 120.

 Next, the operation of the seventh embodiment will be described.

R / L route identification bitmap memory (LDM) for each VPI 1
Reference numeral 28 denotes a VPI for identifying all of the lines passing through the header decoding line separation circuit (HRS) 126 in a state where loop back is not performed in all ADD-DROPMUXs connected to the ring transmission line. Correspondingly, a route identification bit R / L indicating whether each line transmits to the clockwise ring transmission line 112 or to the counterclockwise ring transmission line 113.
have. R indicates clockwise and L indicates counterclockwise. The route identification bit R / L is determined by the header decoding circuit separation circuit (HRS) 126.
When there is no more access, the memory is rewritten from R to L or from L to R by the memory rewrite signal 131. Route identification bit R / L of R / L route identification bitmap memory (LDM) 128 for each VPI of line loopback circuit (LBC) 133
Are normally set to L in preparation for disconnection of the clockwise ring transmission line 112 on the output side of the ADD-DROPMUX of the own station. On the other hand, the route identification bit R / L of the R / L route identification bitmap memory (LDM) 128 for each VPI of the line loopback circuit (LBC) 134 is normally set to the right side of the output side of the ADD-DROPMUX of the own station. All are set to R in preparation for disconnection of the surrounding ring transmission line 113.

In a normal state, the header decoding circuit separation circuit (HRS) 126 passes each cell that has arrived as it is and sends it out to the ring transmission line. However, arriving empty cells are always passed through and sent to the ring transmission line. Upon receipt of the operation start signal 127, the header decoding line separation circuit (HRS) 126 reads the VPI in the header of each real cell in the information sequence arriving thereafter, and uses the VPI as a memory read signal 129 to set the R / L A route identification bit map memory (LDM) 128 receives the route identification bit R / L corresponding to the VPI as a memory output signal 130, and arriving each real cell by the route identification bit R / L. In the case of a cell to be separated, the cell is transmitted to the separated line insertion circuit (LI) 90L or 90R, and the separated cell position is transmitted to the ring transmission line side with an information sequence in which empty cells are inserted. I do. Upon receiving the operation stop signal 127, the header decoding line separation circuit (HRS) 126 returns to the normal state.

The switching signal insertion circuit (SIN) 124 for the cell of the designated VPI normally passes the arriving cell as it is, but indicates the insertion of the switching signal indicating the end of the information sequence in the cell of the VPI identifying the working line to be switched. When the control signal 125 is received, the switch signal indicating the end of the information is inserted into the first cell of the specified VPI arriving thereafter, and at the same time, the switch signal insertion completion signal 125 is sent to the control circuit (CT) 132. The header decoding circuit separation circuit (HRS) 137 reads the VPI in the header of each arriving real cell, and uses the VPI as a memory read signal 94 as R /
L route identification bitmap memory (LDM) 93
Route identification bit R / L corresponding to VPI is output to memory output signal 95.
When the route identification bit R / L is R, the real cell is sent to a line insertion circuit (LI) 90R,
On the other hand, in the case of L, it is sent to the line insertion circuit (LI) 90L.

Next, a line switching procedure from the working line 135 to the protection line 136 will be described.

First, a line switching signal is sent from the center device (CNT) 111 to the control circuit (CT) 120 of the transmission side device 12 via the data link 110 and the data link transmission / reception circuit (DTR).
Upon receiving the line switching signal, the control circuit (CT) 120 stops sending the read clock 65, sends out a control signal 63, and outputs a cell separation circuit (designated VPI corresponding to the left-handed ring transmission line). CS) The selector (S) 62 is set to connect the 74a and the FIFO 64, and then the protection line 136 to be switched is set.
A control signal 75a indicating the separation of the cell having the VPI for identifying the switch, and a switch signal detection instruction signal indicating the detection of the switch signal indicating the end of the information sequence of the cell of the VPI identifying the working line 135 to be switched After transmitting 106 to the switching signal detection circuit (SDT) 105 of the cell of the designated VPI corresponding to the clockwise ring transmission line, the line switching preparation completion signal is transmitted to the center device (CNT) 111.

After receiving the switch preparation completion signal, the center device (CNT) 111 controls the control circuit of the loop-back circuit (LBC) 133 of the line of the transmitting device 1 via the data link 109 and the data link transmitting / receiving circuit (DTR) 108. (CT) Sends a line switching signal to 132. Upon receiving the line switching signal, the control circuit (CT) 132 sends a memory rewrite signal 131 when the header decoding line separation circuit (HRS) 126 is not in operation,
After rewriting all the route identification bits R / L in the / L route identification bitmap memory (LDM) 128 to R, an operation start signal 127 is sent to the header decoding line separation circuit (HRS) 126. If the header decoding circuit separation circuit (HRS) 126 is already in operation, the above operation is not performed.

Next, the control circuit (CT) 132 sends a control signal 125 indicating insertion of a switching signal indicating the end of the information sequence to a VPI cell for identifying the working line 135 to be switched. Thereafter, the control circuit (CT) 132 sends the memory rewrite signal 131 immediately after the cell into which the switch signal is inserted passes the header decoding line separation circuit (HRS) 126 after receiving the switch signal insertion end signal 125. R / L route identification bitmap memory (LD
M) After changing the route identification bit R / L corresponding to the VPI for identifying the working line 135 to be switched in 128 from R to L, a line switching completion signal is sent to the sector device (CNT) 111.

On the other hand, the control circuit (CT) 120 of the reception-side device 12 transmits the switching signal detection signal 106 to the command V corresponding to the clockwise ring transmission path.
After receiving from the switching signal detection circuit (SDT) 105 of the PI cell, the transmission of the read clock 65 is started immediately after the cell into which the switching signal is inserted passes the cell multiplexing circuit (PM) 91c. Thereafter, after receiving the empty signal 66, the control circuit (CT) 120 transmits the signal from the cell separation circuit (CS) 74a of the designated VPI corresponding to the counterclockwise ring transmission line to the cell multiplexing circuit (PM) 91c via the FIFO 64. Specify the delay time to the output terminal as the VPI cell arrival interval that identifies the protection line 136 to be switched
A cell arrival interval detection circuit (CDT) 70a of the designated VPI corresponding to the ring transmission line of the counterclockwise direction corresponding to the VPI cell arrival interval designation signal 71a
To send to. Thereafter, the control circuit (CT) 120
The cell arrival interval detection circuit (CDT) 70a of the designated VPI corresponding to the ring transmission line going counterclockwise with the PI cell arrival interval detection signal 71a
Immediately after receiving from, a control signal 75a indicating cell separation release is sent to the cell separation circuit (CS) 74a of the designated VPI corresponding to the counterclockwise ring transmission line, and then a line switching completion signal is sent to the center device (CNT) 111 Then, the line switching is completed.

Since the seventh embodiment operates as described above,
There is no instantaneous interruption of the information sequence due to line switching. The switching back of the line is performed in the same manner as the line switching, so that the switching back can be performed without an instantaneous interruption.

At the point in FIG. 8, if it is desired to stop the operation of one or both of the ring transmission lines, the loopback circuit of the line on the transmission side of the line for all lines in the ring transmission line for which the operation passing through the point is stopped. , Line switching is performed without interruption in the same manner as described above. As a result, loopback of all lines in the ring transmission line whose operation is to be stopped can be performed without instantaneous interruption. Further, after returning the ring transmission line whose operation has been stopped to the normal state, the switching back of each line is performed without interruption in the same manner as described above, so that the switching back of the ring transmission line in the loopback state is completed. This can be done with a momentary interruption.

The control circuit (CT) 132 sends out the operation stop signal 127 when the loopback circuit of the line to which the own circuit belongs does not perform any loopback of the line, and then sends the memory rewrite signal 131 Is transmitted, and all the route identification bits R / L in the R / L route identification bit map memory (LDM) 128 are rewritten to the values prepared for the ring transmission path disconnection as described above. As a result, when a ring transmission path disconnection occurs, all the lines can be shifted to the loopback state only by transmitting the operation start signal 127 from the control circuit (CT) 132. If the transmission line disconnection occurs while the header decoding line separation circuit (HRS) 126 is operating, all the route identification bits R that do not indicate the loopback state in the R / L route identification bitmap memory (LDM) 128 It is necessary to rewrite / L to the loopback state at high speed.

In the above description, an example in which the line identified by the VPI is switched is shown. In FIG. 8, the cell arrival interval detection circuit (CDT) 70a of the designated VPI is designated as the cell arrival interval detection circuit of the designated VCI. VPI cell switching signal detection circuit (SDT) 10
5 is used as the specified VCI cell switching signal detection circuit, the specified VPI cell separation circuit (CS) 74a is used as the specified VCI cell separation circuit,
R / L route identification bitmap memories (LDMs) 93 and 128 for each VCI as R / L route identification bitmap memories for each VCI, and cell switching signal insertion circuit (SIN) 124 for the specified VPI cell switching for the specified VCI Change each to the signal insertion circuit,
By processing each cell according to the VCI in the header of each cell in each circuit, it is also possible to perform line switching for each call identified by the VCI.

FIG. 9 is a block diagram showing an eighth embodiment of the present invention, in which the above-described principle is applied to line switching in a subscriber ring transmission line, and a line is connected using a cross-connect switch in an ADD-DROPMUX. Each time, loopback switching and switching back are performed without instantaneous interruption.

In FIG. 9, 157 is a control circuit (CT), 142 is a memory rewrite signal, 141R and 141L are line separation map memories (SM), 138 is a header decoding line separation circuit (HRS), 139 is a memory read signal, and 140 Is the memory output signal, 144R and 144
L is a map memory (LM) for a loopback line, 143R and 143L are header conversion circuits (HC), 145 is a memory read signal, 146 is a memory output signal, 147 is a cross-connect switch (XSW) that switches on a cell basis, 148 , 149 and 150 are the input terminals of the cross-connect switch (XSW) 147, and 151, 152 and 153 are the cross-connect switches (XS).
W) 147 output terminal, 154 is a header conversion, header conversion and decoding conversion insertion circuit (RCI) for inserting a switching signal into a cell of a designated VPI, 155 is a working line, and 156 is a protection line, and other circuits Is the same as that shown in the figure.

The feature of the present invention is that in FIG.
Switching signal insertion circuit (SIN) 124 as switching signal insertion means
And a decoding conversion insertion circuit (RCI) 154, and switching control circuits (CT) 157 and 99 as first line switching control means. SDT) 105 and FI as real cell delay means
The FO 64 includes a cell separation circuit (CS) 103 and a control circuit (CT) 107 as a line switching control means.

 Next, the operation of the eighth embodiment will be described.

The line separation map memories (LSM) 141R and 141L are
Normally, a VPI for identifying all lines to be received by the ADD-DROPMUX of the own station is written, and a line separation map memory (S
M) The contents of 141R and 141L match. ADD-DR of own station
If it becomes necessary to loop back the line in the OPMUX, the memory rewrite signal 142 causes the VPI for identifying the line to be looped back to the line separation map memory (S
M) Added to 141R or 141L. On the other hand, when returning the line in the loopback state to the normal state, the VPI for identifying the loopback state is deleted from the line separation map memory (SM) 141R or 141L by the memory rewrite signal 142.

The header decoding line separation circuit (HRS) 138 passes an empty cell as it is among the cells of the arriving information sequence, reads the VPI in the header of the real cell, and uses the VPI as a memory read signal 139 as a memory read signal 139. Separated map memory (SM) 1
41R or 141L, and receives a memory output signal 140 indicating whether the VPI is in the line separation map memory (SM) 141R or 141L. Thereby, when the VPI is in the line separation map memory (SM) 141R or 141L,
The actual cell is separated and a header conversion circuit (HC) 143R and
143L, and an information sequence in which an empty cell is inserted at a cell position where the real cell is separated is inserted into a line insertion circuit (LI) 90R.
Or send to 90L. On the other hand, when the VPI is not in the line separation map memory (SM) 141R or 141L, the real cell is passed as it is.

The loop-back line map memories (LM) 144R and 144L for transmitting and receiving switching information are provided in a loop-back line map memory (LM) when all ADD-DROPMUXs connected to the ring transmission line do not loop back the line. L
M) For all lines passing through the header decoding line separation circuit (HRS) 138 corresponding to 144R and 144L, VPI for identifying each line is written. The header conversion circuits (HC) 143R and 143L read the VPI in the header of the real cell that has arrived, and use the VPI as a memory read signal 145 for the loop-back line map memory (LM) 1
44L or 144L, and receives a memory output signal 146 indicating whether or not the VPI is in the loopback line map memory (LM) 144R or 144L.

As a result, in the header conversion circuits (HC) 143R and 143L, the VPI corresponds to the loopback line memory (LM) 144.
R or 144L, the root identification bit R / L inserted at an empty bit position in the header of the real cell.
Is rewritten from R to L and from L to R, respectively, and the real cell is sent to the cross-connect switch (XSW) 147.
On the other hand, when the VPI is not in the loop-back line map memory (LM) 144R or 144L, the real cell is passed as it is.

The cross-connect switch (XSW) 147 transfers each real cell to a target output terminal according to a route identification bit R / L inserted into an empty bit position in the header of each real cell input from each input terminal. The real cell input from the input terminal 148 is transferred to the output terminal 152 when the root identification bit R / L is R, and to the output terminal 151 when the root identification bit R / L is L. The real cell input from the input terminal 149 has its root identification bit R
Output terminal 153 when / L is R, output terminal 1 when / L
Transferred to 52. The real cell input from input terminal 150 is
If the route identification bit R / L is R, the output terminal 153
In the case of L, it is transferred to the output terminal 151.

Since the operation is performed as described above, the route identification bits R / L in the headers of all the real cells are R on the clockwise ring transmission line 112 and are L on the clockwise ring transmission line 113. Header conversion, header conversion and decoding conversion insertion circuit (RCI) 154 for inserting the switching signal into the cell of the designated VPI
Operates in the same manner as the decoding conversion separation / insertion circuit (RCSI) 92 except that line separation is not performed.

Next, a line switching procedure will be described. Regarding the line switching in the ADD-DROPMUX of the line transmission source, the circuit for separating the line is changed from the decryption conversion separation / insertion circuit (RCSI) 92 to the cross connect switch (XSW) 147, and the fifth line is switched.
It can be performed in the same manner as in the case of the drawing. Here, as an example of line loopback switching, a procedure for switching from the working line 155 to the protection line 156 will be described.

First, the center device (CNT) 111 sends a line switching signal to the control circuit (CT) 107 of the receiving device 12 via the data link 110 and the data link transmission / reception circuit (DTR) 108. Upon receiving the line switching signal, the control circuit (CT) 107 stops sending the read clock 65, and indicates the separation of the cell having the VPI and the route identification bit L for identifying the protection line 156 to be switched. After transmitting the separation instruction signal 104 and further identifying the working line 155 to be switched, and transmitting the switching signal detection instruction signal 106 indicating the detection of the switching signal indicating the end of the information sequence of the cell of the VPI, the center device (CNT) 111 To send a line switching preparation completion signal.

After receiving the line switching preparation completion signal, the center device (CNT) 111 transmits the control circuit (C) of the transmission side device 1 via the data link 109 and the data link transmission / reception circuit (DTR) 108.
T) Send a line switching signal to 157. The control circuit (CT)
157, upon receiving the switching signal, the working line 1 to be switched
A control signal 125 indicating a switching signal insertion indicating the end of the information sequence is transmitted to the VPI cell identifying 55. Thereafter, the control circuit (CT) 157 sends the memory rewrite signal 142 immediately after the cell into which the switching signal is inserted passes the header decoding line separation circuit (HRS) 138 after receiving the switching signal insertion completion signal 125. Then, the VPI for identifying the active line 155 to be switched is written in the line separation map memory (SM) 141R. Thereafter, the control circuit (CT) 157 sends a line switching completion signal to the center device (CNT) 111.

On the other hand, after receiving the switching signal detection signal 106, the control circuit (CT) 107 of the receiving side device 12 reads the read clock 6 immediately after the cell into which the switching signal is inserted passes the cell multiplexing circuit (PM) 91b.
Start sending 5. Thereafter, the control circuit (CT) 107
Indicates the delay time from the cell separation circuit (CS) 103 of the designated route identification bit of the designated VPI to the output terminal of the cell multiplexing circuit (PM) 91b via the FIFO 64 after the reception of the empty signal 66. As the cell arrival interval of the VPI for identifying the line, the cell arrival interval designation signal 71a of the designated VPI is transmitted. Then, immediately after receiving the cell arrival interval detection signal 71a of the designated VPI, the control circuit (CT) 107 sends a cell separation release instruction signal 104, and then sends a line switching completion signal to the center device (CNT) 111. The line switching is completed.

Since the eighth embodiment operates as described above,
There is no instantaneous interruption of the information sequence due to line switching. Switching back the line is also performed in the same manner as the line switching,
Switchback is possible without interruption.

In the point of FIG. 9, when it is desired to stop the operation of one or both of the ring transmission lines, the line whose transmission source device 1 or the reception side device 12 is the transmission source in the ring transmission line whose operation is to be stopped is changed. From the point of view, the ADD-DROPMUX on the transmission side of the line for all the lines except for the line loop-back switching is performed without interruption in the same manner as described above. Further, with respect to a line included in the ring transmission line whose operation is stopped at a point, and whose transmission source is the transmitting device 1 or the receiving device 12, the transmitting device 1 or the receiving device 12
, Line switching is performed without an instantaneous interruption so as to be inserted into a ring transmission line different from the ring transmission line into which the line is inserted. As described above, it is possible to remove all lines from the ring transmission line whose operation is to be stopped without instantaneous interruption. Further, after returning the ring transmission line whose operation has been stopped to the normal state, the switching back of each line is performed without instantaneous interruption in the same manner as described above, so that the switching back of the ring transmission line in the loopback state is completed. This can be done with a momentary interruption.

In the case of ring transmission path disconnection, a line separation map memory (VPI) that includes VPIs for identifying all lines that need to be looped back is provided separately from the line separation map memory (SM) 141R or 141L, and ring transmission is performed. When the line is disconnected, the line separation map memory (SM) 141R or 141L is switched to the line separation map memory for use. However, when the ring transmission path is disconnected, it is necessary to loop back to the line separation map memory (SM) 141R or 141L. What is necessary is just to write the VPI for identifying all the lines at high speed.

In the above description, an example of line switching identified by the VPI has been described. In FIG. 9, the cell arrival interval detection circuit (CDT) 70a of the designated VPI is replaced with the cell arrival interval detection circuit of the designated VCI. The cell switching signal detection circuit (SDT) 105 of the designated VCI is used as the switching signal detection circuit of the cell of the designated VCI, and the cell separation circuit (CS) 103 of the designated route identification bit of the designated VPI is designated as the cell separation circuit of the designated route identification bit of the VCI. The R / L route identification bitmap memory (LDM) 93 for each VPI is stored in the R / L for each VCI.
A decryption conversion insertion circuit (RCI) 154 that performs header decoding, header conversion, and insertion of a switching signal into cells of the designated VPI in the route identification bitmap memory performs header decoding, header conversion, and insertion of switching signals into cells of the designated VCI. A switching signal insertion circuit (SIN) 124 for the cell of the designated VPI is inserted into the decoding conversion insertion circuit.
The contents of the line separation map memories (SM) 141R and 141L from the VPI to the VCI
In addition, map memory (LM) 144R for loopback circuit and
By converting the contents of 144L from VPI to VCI and processing each real cell in each circuit according to the VCI in the header of each real cell, it is also possible to perform line switching for each call identified by VCI.

Although the embodiments of the line switching in the subscriber ring transmission line have been described with reference to FIGS. 5 to 9, these embodiments can be applied to the line switching in the relay ring transmission line as they are. In that case, the header conversion circuit (HC) 10
0 becomes unnecessary.

〔The invention's effect〕

As described above, the present invention, in the transmitting device, after inserting a switching signal indicating the end of the information sequence in the actual cell of the working line immediately before the line switching, switches the line or transmission line from working to protection, In the receiving side device, until the switching signal is detected from the working line or the transmission line, the real cells in the information sequence sent to the protection line or the transmission line are stored in the delay memory, and the working line or the transmission line is stored. After the switching signal is detected, at the end of the cell containing the switching signal, switching from the working line or transmission line to the protection line or transmission line is started, and then reading of the real cells stored in the delay memory is started. As a result, instantaneous interruption switching can be performed without causing an instantaneous interruption of an information sequence due to line switching, and there is an effect that deterioration of transmission quality due to instantaneous interruption can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is an explanatory diagram showing a format of an information sequence (cell) on the transmission line. FIG. 3 is a block diagram showing a second embodiment of the present invention. FIG. 4 is a block diagram showing a third embodiment of the present invention. FIG. 5 is a block diagram showing a fourth embodiment of the present invention. FIG. 6 is a block diagram showing a fifth embodiment of the present invention. FIG. 7 is a block diagram showing a sixth embodiment of the present invention. FIG. 8 is a block diagram showing a seventh embodiment of the present invention. FIG. 9 is a block diagram showing an eighth embodiment of the present invention. FIG. 10 is a block diagram showing a first conventional example. FIG. 11 is a block diagram showing a second conventional example. 1 ... Transmission-side device, 2, 42,147 ... Cross-connect switch (XSW), 3 ... Mux converter (MUX), 4,14,
47, 67 ... Transmission path changeover switch (LSW), 5, 15, 17, 2
2, 41, 49, 69, 84, 99, 107, 120, 132, 157 ... Control circuit (CT), 6, 13, 50, 55, 69, 83 ... Interface circuit (IF), 7, 7a- 7j: working transmission line, 8: protection transmission line, 9, 10, 20, 21, 52, 53, 87, 88, 109, 110
…… Data link, 11, 54, 111 …… Center equipment (CN
T), 12: receiving side device, 16: demultiplexing device (D-MU)
X), 18, 19, 85, 86 ... Repeater (REP), 23, 124 ...
… Changeover signal insertion circuit (SIN), 24, 39 …… Changeover switch (CSW), 25, 33, 35, 40, 48, 63, 68, 75a, 75b, 75c
Control signal, 26 Working line (transmission line), 27 Protection line (transmission line), 28 Real cell arrival interval detection circuit (RC
DT), 29 ... real cell arrival interval designation signal or real cell arrival interval detection signal, 30, 105 ... switching signal detection circuit (SDT),
31: Switching signal detection signal, 32: Real cell separation circuit (RC
S), 34, 62 ... Selector (S), 36 ... Buffer memory (BUF), 37, 65 ... Read clock, 38 ... Switchable signal, 44 ... Switch signal insertion instruction signal or switch signal insertion completed Signal, 45 …… Cell synchronization pattern insertion circuit (PI), 46…
… Empty cell generation circuit (CG), 51, 108… data link transmission / reception circuit (DTR), 56… recovered clock, 57… cell synchronization circuit (SY), 58… cell phase pulse, 59… empty cell Detection circuit (CD), 60: Write clock, 61, 64: First in first out memory (FIFO), 66: Empty signal, 70a, 70b, 70c: Cell arrival interval detection circuit (CDT), 71a , 71b, 71c ... cell arrival interval designation signal or cell arrival interval detection signal, 72a, 72b, 72c ... switching signal insertion detection circuit (SID), 73a, 73b, 73c ... control signal,
Switching signal insertion completion signal or switching signal detection signal, 74a, 7
4b, 74c, 103: Cell separation circuit (CS), 76a, 76b, 76c
…… Header decoding tag assignment circuit (HRG), 77a, 77b, 77c…
... memory read signal or memory output signal, 78 ... tag assignment circuit (TG), 79a, 79b, 79c ... tag rewrite signal, 80a,
80b, 80c: Tag map memory (TM), 81a, 81b, 81
c, 98, 131, 142 ... memory rewrite signal, 82a, 82b, 82c ...
… Tag removal circuit (TR), 89R, 89L …… Line separation circuit (L
S), 90R, 90L ... Line insertion circuit (LI), 91a, 91b, 91c
…… Cell multiplexing circuit (PM), 92 …… Decoding conversion separation insertion circuit (RCSI), 93, 128 …… R / L route identification bitmap memory (LDM), 94, 129, 139, 145 …… Memory reading signal,
95, 130, 140, 146 ... memory output signal, 96 ... switching signal insertion completion signal, 97 ... switching signal insertion completion signal, 100 ...
... Header conversion circuit (HC), 101, 102 ... Multiplexing highway, 104 ... Cell separation instruction signal or switching signal detection signal, 106 ... Switching signal detection instruction signal, 112, 113 ... Ring transmission path, 114, 118, 122, 135, 155 ... Working line, 11
5, 119, 123, 136, 156 ... stand-by line, 116, 117 ...
Loopback route, 121: Decoding separation / insertion circuit (RS
I), 125 ... Control signal or switching signal insertion complete signal, 12
6, 137, 138: Header decoding circuit separation circuit (HRS), 127
…… Operation start signal or operation stop signal, 133, 134 …… Loop back circuit (LBC), 141R, 141L …… Line separation map memory (SM), 143R, 143L …… Header conversion circuit (H
C), 144R, 144L ... Map memory (LM) for loopback line, 148, 149, 150 ... Input terminals, 151, 152, 153 ...
... output terminal, 154 ... decoding conversion insertion circuit (RCI).

Continuation of the front page (56) References JP-A-61-89728 (JP, A) JP-A-59-122042 (JP, A) JP-A-61-20449 (JP, A) JP-A-2-56133 (JP) JP-A-1-270427 (JP, A) JP-A-1-286645 (JP, A) IEICE Technical Report CS88-55 IEICE Technical Report OCS88-32

Claims (1)

(57) [Claims] 1. A line switching system comprising a transmitting device and a receiving device including switching means for switching a working line or transmission line for transmitting an information sequence in units of cells to a protection line or transmission line. The transmitting device includes at least a switching signal insertion unit that inserts a switching signal indicating the end of an information sequence into a real cell immediately before switching in a working line or a transmission line; and a real cell into which the switching signal is inserted. First line switching control means for switching the working line or transmission line to a protection line or transmission line by the switching unit at the break of the cell after passing through the switching unit, and the receiving-side device includes at least: Switching signal detecting means for detecting the switching signal of the information sequence sent from the working line or transmission line, and a real cell of the information sequence sent from the protection line or transmission line And a real cell storage means for temporarily storing the switching signal, and the switching signal is detected by the switching signal detecting means. After the real cell containing the switching signal passes through the switching means, the switching circuit detects the current line or transmission line at the cell division. A second line switching control means for switching a path to a protection line or a transmission path, and thereafter controlling to read out the actual cells in the cell storage means and send the read out cells to the switching means. Switching method.