JP2589369B2 - Remote control signal transmission / reception system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a remote control signal transmission / reception system for reducing power consumption.

(Prior Art) In Japanese Patent Application Laid-Open No. 62-269427, as shown in FIG. 6, a transmitter transmits a leader pulse DR which continues for a predetermined time prior to transmission of data D1 to D4, and a receiver transmits a leader pulse DR. A receiving operation is performed intermittently for a short time t3 with a period t2 shorter than the DR duration t1, and when it is detected that the leader pulse DR is transmitted during the intermittent reception, a predetermined data receiving time t4 is set by the operation holding unit. A technique for keeping the receiver in a receiving operation state during the period is disclosed.

(Problem to be Solved by the Invention) The conventional technology can reduce power consumption by intermittent reception, but the transmitter uses data D1 to
In addition to transmitting D4, the power consumption increases by the amount of transmitting the leader pulse DR, and the receiver needs to judge two types of signals, the reader pulse DR and the data D1 to D4, and the configuration of the receiver is complicated Becomes

The present invention has been made to solve such a problem. By synchronizing the transmission and reception timings, the transmission time can be set to a predetermined time regardless of the reception cycle, and the transmission time can be reduced. It is an object of the present invention to provide a remote control signal transmission / reception system with reduced power consumption.

(Means for Solving the Problems) Means taken by the present invention to solve the problems and achieve the object are as follows.

In the system according to the present invention, the transmitter temporarily stores the command input in the storage unit, and transmits a remote control signal related to the command input stored based on the transmission timing signal generated periodically by the transmission timer unit, The receiver intermittently applies power to a receiving circuit for a short time required to detect the presence or absence of a remote control signal based on a reception timing signal synchronized with the transmission timing signal generated by a reception timer means. In a reception operation state, when a reception output is generated from the reception circuit during the reception operation, the reception circuit is held in the reception operation state for a predetermined time by the reception state holding means.

(Operation) In the system according to the present invention, since the transmission timer means on the transmitter side and the reception timer means on the receiver side are synchronized, the transmitter temporarily stores the command input, and at the next transmission timing. When a remote control signal relating to the command input is transmitted and the receiver detects that the remote control signal is being transmitted by intermittent reception, the receiver can continue the reception operation for a predetermined reception time and receive the content of the command.

(Example) Hereinafter, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a general system, and FIG. 2 is a time chart for explaining the operation of the system.

In FIG. 1, reference numeral 10 denotes a remote control signal transmission / reception system (hereinafter, referred to as a system). The system 10 includes a transmitter 20 and a receiver 40.

The transmitter 20 uses the battery 21 as a power source, detects that the keys K1 and K2 have been operated by the key interface circuit 22, and the transmission control circuit 23 transmits the transmission time setting means 24 and the transmission code generation means based on each key input. Activate 25, the predetermined transmission time tS
During this period, a preset command code corresponding to the key input is repeatedly generated, and the carrier code (frequency f
c) is modulated, and an infrared light emitting diode LED in the transmission circuit 26 is driven by the output 23a to transmit a remote control signal using infrared light. Clock transmission circuit
Numeral 27 is for generating a reference clock using a crystal, a ceramic vibrator or the like X, and for generating a clock for various controls in addition to a clock for a carrier wave by a frequency dividing circuit (not shown).

The receiver 40 includes a light receiving diode PD for detecting (receiving) a remote control signal transmitted (emitted) from the transmitter 20;
A receiving circuit 41 for amplifying and detecting a signal detected by the light receiving diode PD; a determination processing means 42 for determining a command code based on a detection output 41a of the reception circuit 41 and generating an output corresponding to the command code; and a determination process. An output interface circuit 43 is provided for interfacing each output 42a, 42b of the means 42 to a controlled device (not shown). Terminals 43a and 43b are connection terminals for a controlled device or the like.

Further, the receiver 40 includes switch means 45 for turning on / off the supply of the power of the battery 44 to the receiving circuit 41.
The emitter of the PNP transistor 45a in the switch means 45 is connected to the positive terminal of the battery 44, the collector is connected to the power supply terminal 41b of the receiving circuit 41, and the inputs 45d and 45e of the NOR gate 45c.
When either of them is at the H level, the transistor 45a is turned on via the base resistor 45b, and the receiving circuit 41 is operated.

The receiving cycle control means 46 generates a reference clock using a crystal, a ceramic vibrator or the like Y, divides this clock by a frequency dividing circuit (not shown), and outputs an intermittent received signal at a predetermined timing.
It is configured to output a reception state holding forced release signal (hereinafter referred to as a release signal) 46b. The intermittent reception signal 46a is connected to the input 45d of the NOR gate 45c,
The signal b is applied to the reset input terminal 47a of the reception state holding means 47 via the OR gate 48.

The receiving state holding means (hereinafter referred to as holding means) 47 is constituted by a flip-flop having a reset input terminal 47a and a set input terminal 47b.
One detection output 41a is applied, and the Q output 47c of the holding means 47 is N
Connected to input 45e of OR gate 45c.

A counter for measuring the cycle of the detection output 41a of the receiving circuit 41 and its peripheral circuit (not shown) are provided in the judgment processing circuit 42, and the measurement result of this cycle (to the frequency of the command code, When the instruction content can be determined based on (corresponding to), a reception completion signal is output to the terminal 42c, and the reception completion signal is applied to the reset input terminal 47a of the holding means 47 via the OR gate 48. Connected so that

Next, the operation of the present system will be described while explaining the timing of various signals based on the time chart of FIG.

The transmitter 20 determines that the key K1 has a predetermined chatter monitoring time (second
When the switch is continuously turned on (FIG. 2A), the transmission time tS (for example,
During a period of 100 ms to several seconds), a carrier code having a frequency fc (for example, 38 kHz) is set to a command code corresponding to the key K1 input, for example, a frequency f1.
= 2 kHz, and if the key K2 is turned on (FIG. 2b), a remote control signal with the carrier intermittently transmitted at, for example, a frequency f2 = 1'kHz is transmitted (No. 2). 2 Figure c).

The receiver 40 includes an intermittent reception signal 46a of the reception cycle control means 46.
Accordingly, the switch means 45 is turned on for the reception time tR (FIG. 2d) in the reception cycle T0, and the reception circuit 41 is intermittently set to the reception operation state (FIG. 2f).

The reception cycle T0 is set to be equal to or shorter than the transmission time tS (T0 ≦ tS). The intermittent reception time tR is set to be longer than 1/2 cycle of the longer command code f2 of the command codes f1 and f2. Therefore, even if the transmission timing of the remote control signal of the transmitter and the intermittent reception timing of the receiver are asynchronous, the timing is set so that a part of the remote control signal can always be received.

When the receiver 40 receives the remote control signal (FIG. 2c) during the intermittent reception (tR), the holding means 47 is set by the detection output 41a, and the switch means 45 is turned on by the Q output 47c. And the receiving circuit continues the receiving operation.

Therefore, a counter (not shown) in the judgment processing means 42 is provided with a counter clock (not shown) from the first fall to the next fall of the detection output 41a (for example, by a frequency dividing circuit in the reception cycle control means 46). Can be supplied)
And the counting result (the time tf of one cycle of the command code)
1 or tf2), a command code is determined, a reception completion signal (FIG. 2i) is output, and the judgment output corresponding to the command code is output for an appropriate time (t2, t3 in FIG. 2) and the corresponding terminal 42a, Output to 42b.

The reception completion signal (FIG. 2i) resets the holding means 47 through the OR gate 47, and at this time, stops supplying power to the reception circuit 41.

When the detection output 41a is generated in the receiving circuit 41 due to external noise or the like at the timing of the intermittent signal and the continuous receiving state is established, the receiving operation stop control with the receiving complete signal (FIG. 2i) is not performed. The holding means 47 is reset by the forcible release signal shown in FIG. 2e. This prevents the receiving circuit 41 from entering a continuous operation state. Here, the time from the rise of the intermittent reception signal tR to the output of the forced release signal
t1 (FIG. 2e) is set to be equal to or longer than the transmission time tS of the remote control signal (t1 ≧ tS).

In the present embodiment, a clock signal having a different cycle is used for the command code corresponding to the command content. For example, the ratio between the H level and the L level (pulse duty) having a constant cycle is used.
It is also possible to repeatedly transmit this pulse code in correspondence with a pulse code of several bits, and determine the command content based on the duty or pulse code of the pulse received on the receiver side. good.

Next, an embodiment of the present invention will be described with reference to the block diagram of FIG. 3 and the time charts of FIGS. 4 and 5.

In FIG. 3, the system 50 comprises a transmitter 60 and a receiver 80. In this embodiment, the transmission / reception timing of the remote control signal is synchronized, and the same parts as those in FIG. 1 are denoted by the same reference numerals.

Hereinafter, the configuration of the present system 50 will be described focusing on the differences from the system 10 shown in FIG.

The transmitter 60 includes a storage unit 63 for temporarily storing a command input from the key K1 or K2, a transmission timer unit 67 for generating a transmission timing signal (FIG. 4a), and a synchronization timing signal (fourth).
A synchronizing timer means 68 for generating Fig. C) and a command code relating to the contents of the command and a command / synchronous code generating means (hereinafter referred to as a code generating means) 65 for generating a synchronizing code are provided.

The transmission timer means 67 divides the frequency of the reference clock 67a output from the clock generation circuit 27 by a frequency dividing circuit (not shown), and has a period T0 and an H-level time (for the transmission time) as shown in FIG. Generate a (corresponding) tS transmission timing signal.

The synchronization timer means 68 further divides the frequency-divided output of the transmission timer means 67 by a frequency dividing circuit (not shown) and, as shown in FIG. 4c, a period much longer than the repetition period T0 of the transmission timing signal (for example, T0 = Several 100 ms to several seconds T4 =
(Several hours) and a command signal transmission prohibition signal (FIG. 4b) synchronized with the synchronization timing signal. H level pulse width tP of the synchronization timing signal (FIG. 4c) (corresponding to the synchronization signal transmission time)
Is set so that the synchronization timing signal (FIG. 4c) is shorter than the transmission time tS and substantially at the center of the H level pulse width of the transmission timing signal (FIG. 4a). The L-level pulse width tI of the command signal transmission inhibition signal (FIG. 4b) corresponds to the transmission timing signal (FIG. 4a).
Is set wider than the pulse width.

Then, the transmission control unit 64 checks the storage content of the storage unit 63 at each transmission timing of the cycle T0, and
If it is stored that a key input has been made to the
And the clock generation circuit 27
Intermittently supplies the supplied carrier clock and outputs 64a
Drives the infrared light emitting diode LED in the transmission circuit 26 to transmit a remote control signal using infrared light.

Further, the transmission control means 64 outputs the synchronization timing signal (fourth
Based on FIG. C), a code is output to the code generation means 65, and the carrier code (frequency f
c) is interrupted and a remote control signal relating to the synchronization command is transmitted. At the timing of transmitting the synchronization signal, the transmission control means 64 gives priority to the transmission of the synchronization signal based on the command signal transmission prohibition signal (FIG. 4b) even if the key input is stored in the storage means 63. At this transmission timing, a command signal based on the key input storage content of the storage means 63 is transmitted.

In this embodiment, a command pulse corresponding to the key K1 is a clock pulse having a frequency fL (for example, 1 kHz), a command code corresponding to the key K2 is a clock pulse having a frequency fH (for example, 3 kHz), Frequency fM (eg 2kHz)
Clock pulse is used.

On the other hand, the receiver 80 includes a reception timer means 86 for generating a reception timing signal synchronized with the transmission timing signal. The reception timer means 86 generates a reference clock by the vibrator Y, divides the frequency of the reference clock by a frequency dividing circuit or the like (not shown), and as shown in FIG. A signal having a pulse width tV (tV ≒ tS) of an H level is output at the timing of receiving the synchronization signal at a timing corresponding to the intermittent reception time, which is set shorter than the transmission time tS. Have been. The reception timing signal (FIG. 5b) is output from terminal 86a. Further, the reception timer means 86 outputs the reception state holding forcible release signal to the terminal 86b for a short time after a predetermined time has elapsed from the fall of the reception timing signal (FIG. 5c), and is also input to the terminal 86c. The generation timing of the reception timing signal (FIG. 5c) is synchronized with the transmission timing of the transmitter 60 based on the synchronization signal detection signal 82d (FIG. 5f) of the judgment processing means 82.

In order to synchronize the transmission and reception timings when installing the system 50 or when replacing the battery, for example, a switch for initial synchronization is provided on the receiver 80 side, and when this switch is pressed, the receiver 80 enters a continuous reception state. , From the time when the first remote control signal (or synchronization signal) is received from the transmitter 60, a predetermined period T0 may be set to an intermittent reception state,
Further, the power-on initial circuit may be provided in the receiver 80 without providing a switch or the like, and the above operation may be performed from the time when the battery is mounted.

The determination processing means 82 has basically the same configuration as the determination processing circuit 42 shown in the first embodiment, but outputs a synchronization signal detection signal shown in FIG. 5f when detecting a synchronization signal. A circuit has been added.

With the above configuration, the clock generation circuit of the transmitter 60
The difference between the transmission and reception timings caused by the 27 and the reception timer means 86 independently generating the reference clocks is periodically corrected by the synchronization command, and the transmission and reception of the transmitter 60 and the receiver 80 are performed. The reception timing is synchronized.

Keys K1 and K2 input (command input) of transmitter 60 are stored in memory circuit 63
And a remote control signal (FIG. 4g) based on the command content is transmitted.

The receiver 80 synchronously sets the receiving circuit 41 to the receiving state for the receiving time tW by the received signal timing signal (FIG. 5b), and receives the remote control signal from the transmitter 60 during the receiving time tW. Then, the holding means 47 is set by the detection output 41a, and the reception state is continued. The determination processing means 82 determines the content of the command based on the detection output 41a, and if the content of the command can be determined, outputs the reception completion signal (FIG. 5e) to the terminal 47c and outputs the signal corresponding to the content of the command. Are output to the terminal 47a or the terminal 47b at appropriate times t5 and t6.

The reception completion signal (FIG. 5E) resets the holding means 48 via the OR gate 47. Note that even when external noise or the like is detected and the holding unit 48 is set, the holding unit 48 is reset by the forcible release signal 86b.
The receiving circuit 41 is prevented from entering the continuous power supply state.

At the synchronization timing, the H-level pulse width tV of the reception timing signal (FIG. 5b) is set substantially equal to the transmission time (tV = tS), and the reception circuit 41 continues the reception state during the time tV. . Therefore, the synchronization signal detection signal (fifth
By setting the frequency divider circuit and the like in the reception timer means 86 to a predetermined preset value using the fall of FIG. F), the reception timing can be accurately adjusted to the transmission timing. Since the synchronization signal is transmitted at the center within the transmission time tS, even if the reception timing on the receiver 80 side is slightly shifted,
The receiver 80 can detect the synchronization signal and synchronize.

In the embodiment shown in FIGS. 3 to 5, since the transmission and reception timings are synchronized, the transmission time tS of the remote control signal is set shorter than that of the asynchronous system shown in FIGS. Yes, and when transmitting pulse codes, etc.,
Transmission / reception is possible without repeatedly transmitting a pulse code relating to the same command content, so that the transmission time of the transmitter can be shortened, and the effect of reducing the power consumption of the transmitter is great.

Similarly, the intermittent reception time tW can be set to a shorter time, and the effect of reducing power consumption on the receiver side is great.

In each of the embodiments, the transmitters 20 and 60 can be constituted by a C-MOS one-chip microcomputer or a gate array, for example, except for the transmission circuit 26. The transmitters 40 and 80 also include the reception circuit 41. Except for this, it can be constituted by a one-chip microcomputer, a gate array or the like.

In each embodiment, two command inputs are shown. However, a plurality of command codes may be provided to transmit and receive a large number of command signals. The command code may be a signal obtained by combining a pulse cycle and a pulse duty. It may be.

(Effect of the Invention) As described above, the system of the present invention synchronizes the transmission and reception timings, so that the transmission time does not need to be set in accordance with the intermittent reception cycle of the receiver, and the command code Is transmitted at least once, the command content can be received by the receiver, the transmission time of the remote control signal of the transmitter can be extremely reduced, and the effect of reducing the power consumption of the transmitter is great.

Also, since the transmission and reception timings are synchronized,
Even if the intermittent reception time of the receiver is set shorter, the presence or absence of the transmission of the remote control signal can be detected, which contributes to the reduction of the power consumption of the receiver.

Further, even when a plurality of remote control systems coexist, it is possible to transmit and receive a remote control signal without causing interference by making transmission / reception timings of the respective systems different without transmitting / receiving an identification code.

[Brief description of the drawings]

FIG. 1 is a block diagram of a general remote control signal transmission / reception system, FIG. 2 is a time chart for explaining the operation of the system, FIG. 3 is a block configuration diagram of a remote control signal transmission / reception system according to an embodiment of the present invention, FIG. 4 is a time chart for explaining the operation of the transmitter of the system, FIG. 5 is a time chart for explaining the operation of the receiver, and FIG. 6 is a time chart for explaining the operation of the conventional system. In the drawings, 10, 50 is a remote control signal transmission / reception system (system), 20, 60 are transmitters, 40, 80 are receivers, 21, 44.
Is a battery, 23 is a transmission control circuit, 24 is transmission time setting means, 25
Is a transmission code generation means, 26 is a transmission circuit, 41 is a reception circuit,
42 and 82 are judgment processing means, 45 is switch means, 46 is reception cycle control means, 47 is reception state holding means, 63 is storage means, 64
Is transmission control means, 65 is command / synchronization code generation means, 67 is transmission timer means, 68 is synchronization timer means, and 86 is reception timer means.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Kyosuke Sakino 2-1-1, Nakajima, Kokurakita-ku, Kitakyushu-shi, Fukuoka Prefecture Totoki Kiki Co., Ltd. (56) References JP-A-62-269427 (JP, A) JP-A-61-111090 (JP, A) JP-A-62-195997 (JP, A)

Claims (1)

(57) [Claims] 1. A receiver which intermittently performs a short-time receiving operation at a predetermined period and detects a signal transmitted from a transmitter during the intermittent receiving operation. A remote control signal transmission / reception system that receives reception content transmitted from a transmitter, wherein the transmitter temporarily stores a command input in a storage unit and stores the command input based on a transmission timing signal periodically generated by a transmission timer unit. The receiver transmits a remote control signal related to the command input that has been performed, and the receiver has a short time required to detect the presence or absence of the remote control signal based on the reception timing signal synchronized with the transmission timing signal generated by the reception timer means. Only intermittently apply power to the receiving circuit to enter the receiving operation state,
A remote control signal transmission / reception system, wherein when a reception output is generated from the reception circuit during the reception operation, the reception state holding means holds the reception circuit in the reception operation state for a predetermined time.