JP2586541B2 - Counter test circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a test circuit for a counter. More specifically, the present invention relates to a counter test circuit capable of performing a counter operation test in a simple operation in a short time.

2. Description of the Related Art Conventionally, a built-in counter of an integrated circuit has been tested by the following method. That is, when the count value is input from the register to the counter and a value can be freely set in the register, a specific value is written to the register to operate the counter. Next, the operation result of the counter is
The quality of the operation of the counter is checked by reading from the data of the register relating to the operation of the integrated circuit or the output of the counter, and comparing it with an expected pattern. By repeating the above operation, the operation of all bits of the counter was tested.

Problems to be Solved by the Invention The above-described conventional counter test shows that, for all bits of the counter, “0” → “1” or “1” → “0” when there is carry, and when there is no carry, In order to confirm that the operation of “0” → “0” or “1” → “1” is performed, the operation of writing data to the respective registers, inputting the data from the registers to the counter, and operating the counter is repeated. It was going by.

For this reason, there is a drawback that when the operation for writing to the register and the operation for operating the counter are complicated, it takes an enormous amount of time to test the counter.

Means for Solving Problems According to the present invention, in a circuit for testing a counter built in an integrated circuit by inputting data from a register to a counter and operating the counter, the output of the counter is used as an input, A counter input data generator that repeats the operation of setting all lower bits of the "1" bit to "1" and outputting the same to the register, characterized in that the counter test circuit is provided.

The counter test circuit of the present invention receives the output of the counter as an input, and outputs data in which all bits lower than the most significant “1” bit are “1” to the count value register as the next test data. Its main feature is that it has a counter input data generator that repeats the operation.

The counter test is as follows: “0” → “1” or “1” → “0” when all bits of the counter have carry, and “0” → “0” or “1” when there is no carry → It must be confirmed that the operation of “1” is performed.
This test was performed by inputting a plurality of different data into the count value register.

In the counter test circuit of the present invention, all the bits below the highest order "1" of the output data from the counter are set to "1", and are used as the next test data. Therefore, no matter what the initial count value data is, when a counter test is started, test data is input into the count value register. Therefore, even for an integrated circuit in which the data of the count value register cannot be arbitrarily changed, the time required for the test hardly changes.

When a counter test is performed using the counter test circuit of the present invention, the count value data used for the test is
All bits below the most significant "1" bit are "1". Therefore, in the test in which the counter is operated at most (the number of bits of the counter + 2) times, it is possible to confirm both the operation when there is a carry and the function to save the value when there is no carry for all the bits.

EXAMPLES Hereinafter, the present invention will be described in more detail with reference to the drawings by way of examples. However, the following disclosure is merely an example of the present invention, and does not limit the technical scope of the present invention.

Embodiment 1 FIG. 1 shows a configuration diagram of an example of a test circuit of a counter of the present invention. In the test mode of the counter, as shown in FIG. 1, the test circuit of the counter according to the present invention includes a counter 2 to be tested, an input data generator 3 and an output latch 4 to which the output from the counter 2 is input. , And a count value register 1 which receives data generated by the input data generator 3 and outputs the data to the counter 2. In this embodiment, the counter 2 is an 8-bit counter.

The test circuit of the counter of the present invention shown in FIG. 1 operates as follows. When the count value data is input to the counter 2 from the register 1, the counter 2
Increments and outputs the count value output by.
The input data generator 3 detects the most significant “1” bit from the output of the counter 2 and all bits below it are “1”.
And outputs it to the register 1. The register 1 outputs the output of the input data generator 3 to the counter 2 again as count value data.

In the case of an 8-bit counter, the above-described operation is repeated up to 10 times to test the counter 2.

FIG. 2 shows the input and output of the counter 2 when the data first input to the counter 2 is "00000000".
4 shows a data transition diagram of an output of the counter input generator 3. FIG. In this case, the test is completed by operating the counter 2 continuously nine times. Further, in the test circuit of the counter according to the present embodiment, even if the data input to the counter 2 first has any value,
Is the value of any of the counter input data shown in FIG. 2, so that if the counter 2 is operated up to 10 times, the test is completed.

FIG. 4 shows the input data generator 3 of this embodiment. The input data generator 3 of this embodiment has 8 bits like the counter 2, and in FIG. 4, the left is upper and the right is lower.
The data output from the counter 2 is input from A of each bit, and all bits below the highest-order bit “1” are set to “1” and output from B to the register 1.

In FIG. 4, φ1 and φ2 are non-overlapping two-phase clock signals, and ▲ is an inverted signal of φ1.

In the circuit of FIG. 4, the MOS transistor connected to the input A forms a gate that is opened and closed by a clock φ1, and another MOS transistor G and two inverters F form a 1-bit memory. I have. Thus,
At the clock φ1, a binary signal is fetched from the input A into the memory, and at the clock φ2, the 1-bit memory becomes stable,
The writing ends.

The N-type MOS transistor E receiving such an output of the 1-bit memory (connected in series through all the bits) is turned on and off according to the state of the output of each 1-bit memory. Then, the clock φ2
Becomes high level, the N-type MOS transistor E connected to the ground at the left end in FIG. 4 becomes conductive, the P-type MOS transistor D connected to a predetermined voltage becomes conductive, and the output buffer C is activated. Thus, the N-type MOS transistor E receiving the output of each 1-bit memory is divided into right and left by the N-type MOS transistor E in the cut-off state.
The output buffer C connected to the MOS transistor E is similarly divided into left and right. As a result, one of the divided output buffers C receives the ground potential at its input, and the other divided output buffer C receives the predetermined voltage at its input. That is, a bit pattern in which all the bits below “1” of the most significant bit are “1” is output from B.

Embodiment 2 In this embodiment, an inverter is added before and after the input data generator 3 of the test circuit of the counter of the embodiment 1. Thus, the test at the time of decrementing of the counter 2 can be performed in the same manner.

FIG. 3 shows that the data first input to the counter is "11".
FIG. 11 shows a data transition diagram of the input and output of the counter and the output of the counter input generator in the case of 111111 ".

In this case, by operating the counter nine times as in the first embodiment, a test can be performed when the counter is decremented.

As described above, the present invention has an effect of greatly reducing the test time of a counter by adding a counter input data generator that outputs the output of the counter and outputs a counter test input to the conventional counter. .

According to the counter test circuit of the present invention, even if the counter on an integrated circuit cannot input arbitrary data as the count value, the maximum (the number of bits of the counter +
2) The test of the counter can be performed only by operating the counter. Further, by adding an inverter before and after the counter input generator of the test circuit of the counter of the present invention, and inputting and outputting data from the input data generator via the inverter, a test at the time of decrementing the counter is also possible. is there. If the connection to the inverter can be switched, the operation of both the increment and the decrement of the counter can be tested by operating the counter at most {2 × (number of bits of the counter) +3} times.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a counter test circuit according to the present invention, and FIG.
FIG. 3 is an example of a data transition diagram in a case where a bit counter increment test is performed. FIG.
FIG. 4 is an example of a data transition diagram at the time of a bit counter decrement test. FIG. 4 is an embodiment of an input data generator used in the test circuit of the counter of the present invention. [Main Reference Numbers] 1 ... register, 2 ... counter, 3 ... input data generator, 4 ... output latch, A ... input line, B ... output line, C ... clocked inverter, D: P-type MOS transistor, E: N-type MOS transistor, F: Inverter, G: CMOS transistor,

Claims (1)

(57) [Claims] 1. A data input from a register to a counter,
In a circuit for testing a counter built in an integrated circuit by operating a counter, an output of the counter is input, and all bits lower than the most significant "1" bit are output as "1" to the register. Repeat the operation,
A test circuit for a counter, comprising a counter input data generator.